JPS5972532A - Data transfer control method - Google Patents

Abstract

PURPOSE:To have directly a mutual transfer of the storage contents and to accelerate a processing speed, by using an NOP generator having an RAM address space and an image address space. CONSTITUTION:A decoder 7 decodes the address of an MPU1 and produces the signal to select an ROM2, an RAM3, a peripheral device controller 4 and an NOP generator 5. An OR circuit 8 selects both NOP5 and the RAM3 at a time and sets an address space of the RAM3 equal to the NOP5. a gate circuit 9 selects an NOP5 and separates the data bus of the MPU1 from the data bus set between the RAM3 and the controller 4. A selection circuit 10 transmits the contents A13 of the address bus of the MPU1 to the RAM3 and the controller 4. The controller 4 performs R/W of a byte every time the NOP selection signal is inverted 11 and supplied to the controller 4. In such a way, the data are transferred directly and mutually to accelerate the processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data transfer control method that allows high-speed direct transfer of storage contents between an external memory and a main memory using relatively simple means.

[Prior art]

A flowchart of an example of a conventional data transfer control method is shown in FIG. 1(a). This method is a method in which data is read into the internal register of a microprocessor (hereinafter abbreviated as MPU) and then written into the memory space at a specified address, and it takes time to complete the reading and writing procedures. However, the disadvantage was that high-speed data transfer was difficult.

To deal with this drawback, a direct memory φ access controller (hereinafter abbreviated as DMAC) is used to transfer data at high speed directly between external memory and main memory using the DMA method, without having to read the data to be transferred into registers in the MPU one by one. things have been done. The procedure for this method is shown in Figure 1 (b
), the start address of the RAM to which data is to be transferred, the number of words to be transferred, the transfer mode, etc. are specified to the DMAC, and high-speed data transfer is performed. In addition, IRQ
indicates an interrupt signal.

However, with this method, it is necessary to specify the start address of kLAM to which data should be transferred and the number of words to be transferred each time data is transferred, making the program complicated and requiring a large number of bins (for example, is a Hitachi DMAC (HD6844 is a 40-bin) expensive dedicated special LSI
There were disadvantages such as the need to use

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control method that eliminates the drawbacks of the prior art and allows high-speed data transfer with a simple program.

[Summary of the invention]

In order to achieve the above object, the present invention provides a NOP (instruction to prevent the MPU from executing any operations) generator that has an address space of RAM, which is a data storage location, and an address space related to images. , by accessing this NOP generator, the RAM
A desired address is accessed, a data transfer path separated from the MPU data bus is formed between the RAM and the peripheral device controller, and one block of data is transferred during the period corresponding to the IN0P command. Ml) It is fast because it is not transferred via the U internal register. It's the length.
Compared to direct memory access controllers, NOP generators are much simpler and cheaper to construct. In addition, read the address when accessing the NOP generator,
The program is simplified because it is made different depending on the write and the data transfer direction (J, whether to write data to LAM or read data from RAM) is specified by this difference.

[Embodiments of the invention]

The present invention will be explained below using the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

The MPUI operates according to a program stored in the ROM 2 or A M 3, and controls the peripheral device controller 4, the NOP generator 5, etc. The peripheral device controller 4 controls the connected floppy disk, hard disk, etc. It controls the drive 6 and normally connects the drive 6 to the data bus (Do to D7) of the MPUI to send and receive data.
In order to select the P generator 5, etc., A14 and Al5 of the MPUI address bus (AO to A15) are decoded, and the respective select signals (ROMC8, RF) are decoded.
, I 10 CS , N0PC8). When the NOP generator 5 is selected, the OR circuit 8
, AM3 is also selected at the same time, )(, AM3
The address space of the NOP generator 5 is made the same as that of the NOP generator 5. When the N (JP generator 5) is selected, the gate circuit 9 separates the data bus (Do to D7) of the MPU 1 from the data transfer path between the AM 3 and the peripheral device controller 4.

The selection circuit (MPX) 10 normally transmits the read/write (R/W) signal of the MPU 1 to the AM 3 and the peripheral device controller 4, but when accessing the NOP generator 5, the selection circuit (MPX) 10 transmits the read/write (R/W) signal of the MPUI. A13 of (Ao~A15)
The contents are switched so that they are transmitted to the RAM 3 and the peripheral device controller 4. The inversion circuit 11 converts a transfer acknowledge signal (TzAK) supplied to the peripheral device controller 4 into a NOP generator select signal (NOPC8).
). The peripheral device controller 4 reads or writes one write of data each time the previous transfer I acknowledge signal is input.

FIG. 3 shows a memory map in the embodiment shown in FIG. , ROM2 (E
This indicates that the addresses O00 to fi' FFF) are respectively arranged.

FIG. 4 shows a specific example of the NOP generator 5, which is composed of a tri-state buffer and has a select signal N0PCB.
is input, the M, PU1 data buses (Do to D7
) is outputted as data ``01''. This data 101'' corresponds to the NOP instruction (NOOPE) cATION) in the case of the Hitachi microprocessor unit H1) 6800. That is,
While accessing the NOP generator 5, M, P U 1 sequentially inputs the upper numbers of the address bus (Ao to A15) of the MPU 1.
It generates an address to be set to 1 and connects it to the MPUI data bus (D
data 101" from the NOP generator 5 on the

FIG. 5 is an explanatory diagram of the operations of the address decoder 7, the OR circuit 8, and the selection circuit (MPX) 10. Based on the memory map shown in FIG.
The respective select signals are generated from the address buses A14 and A15. Address space of NOP generator 5 (
4000 to 7FFF), kL at the same time
In order to access AM3, the select signal (RAMC8) of H and AM3 is 4 = A rs + select signal (几AM8toτ) to select 6 of RAM3.
) and the NOP generator select signal (N 013 C8) in an OR circuit 8. In the embodiment shown in FIG. 2, as shown in the memory map shown in FIG. 600
Read when selecting address 0 to 7FFF It
] A, i)) It becomes easier to act. In this embodiment, the NOP generator 5 is accessed (400O to 7
F1”), read/write (R/VJ) (i
As the f number, it is switched by the selection circuit 10 and uses the MPLJI address bus (Al1). This means that 4 and 5 in hexadecimal are (oioo) and ゛(01) in binary.
01) and Natsu° (Al1 is O, 6 and 7 in hexadecimal are (0110) and (0111) in binary, and A13 is 1, which allows you to specify whether it is normal or W. be.

FIG. 6 is a flowchart illustrating the operating procedure of this embodiment. The program is executed by selecting the address space of the NOP generator 5 using a JMP instruction (JUMP operation).

The address specified with the JMP command can be read (READ).
For operation, address 6000 to 7FFF, write (W) 1.
In the case of ITB) operation, the addresses are 4000 to 5FFF. The start address of RAM3 that stores the transfer data is R.
Since the address space of AM3 has an image (copy) relationship with the address space of NOP generator 5, it is only necessary to specify the address value as it is in the lower address Ao-Att specified by the JMP command. In other words, in the case of a READ operation whose start address is 0200, JMP62
It will be address 00. Note that the number of data transfers is specified in advance to the peripheral device controller 4, as in the case of using DMAC, and when the specified number of transfers is completed, the peripheral device controller 4 sends an interrupt signal 11 (, Q.The MPUI performs interrupt processing using the IRQ signal.In this embodiment, it simply outputs N.
The process is simply to cancel access to the OP generator 5. Although JMP instructions are used in Figure 6, JSI
(, JUMP TO5UBROUTINE) can be used in the same manner.

In the Hitachi microprocessor HD6800, the NOP instruction takes 2 machine cycles (microprocessor operation cycle), but the Hitachi microprocessor - 9 units 1 -
The HD 6301 VTEHA NOP instruction takes 1 machine cycle, and by using the 2MHz version, it takes 2 machine cycles.
Data transfer rates can be increased up to megabytes/second.

〔Effect of the invention〕

As explained above, according to the present invention, high-speed data transfer is possible with a simple and therefore inexpensive circuit configuration without using a special LSI such as a DMA controller.
It also has the advantage of being very simple to program.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are flowcharts showing conventional data transfer procedures, Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a memory map in the same embodiment, and Figure 4 is a NOP generator. FIG. 5 is a diagram illustrating the operation of the address decoder, etc. in the same embodiment, and FIG. 6 is a flowchart explaining the operation procedure of the same embodiment. 1...MPU 3...RAM4...Peripheral device controller 5...NOP generator 7...Address decoder 8
... OR circuit 9 ... Gate 10 ... Selection circuit rod / Calendar ((1) (b)
Exit 2 Bus Bus Figure 3 Figure 4

Claims (1)

[Scope of claims] , above 1 (AM
A NOP generator having an address space and an image-related address space is provided, and by accessing this NOP generator, the it AM and the external memory are connected via the peripheral device controller to the normal data processing via the microprocessor. A data transfer control method characterized in that memory contents are transferred directly to each other without relying on input/output procedures. (2) The address of the NOP generator at the time of reading and the address of the NOP generator at the time of writing are made different, and the transfer direction of the mutual transfer is specified by this difference in address. Data transfer control method.