JPS61283935A - Memory access system - Google Patents

Abstract

PURPOSE:To perform the control of a microprogram at a high speed by writing the microprogram data to a system data memory having a RAM constitution and performing the reading/writing operations to the system data memory. CONSTITUTION:The read/write address data is set to a micromemory address register 3A from an arithmetic unit 5. In a read mode this data is used as the address of a memory 10A by a selection signal SEL1 via a multiplexer 12A. Then the output data is extracted by the SEL1 as the output of a multiplexer 12B and then as the output of a pipeline register 7B with the next timing. This output is fetched by the unit 5 at a high speed through a bus 2. In a write mode the data bus of the register 3A is activated by the SEL1. Then the write data is set to a register 4A from the unit 5 and then written at a high speed to the memory 10A by a write control signal muWR.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a memory access method in microprogram control.

Summary of B0 invention The present invention relates to a device that performs microprogram control.

Prepare RAM configuration memory for micro program memory and micro system data memory.

The microprogram is written from the system memory by bootstrapping, and reading/writing to the system memory is performed to the microsystem data memory.

This makes it possible to use an inexpensive RAM 1 and yet achieve high-speed read/write operations.

C0 Prior Art Conventionally, microprogram control is configured as shown in FIG. Between system bus 1 and microsystem 7512 is memory address register 8. Memory data register 4
The micro system bus 2 is connected to the arithmetic unit 5. A sequencer 6 and a pipeline register 7 are coupled, and a ROM-configured microprogram memory 8 is coupled between the sequencer 6 and the pipeline V register. and pipeline register 7 are coupled. As shown in FIG. 7, the microprogram instructions written in the memory 8 include an ALU that specifies data processing, μm5EQ that specifies the next address of the sequencer 6, and μm BUSOP that specifies the microsystem bus and system pass gate. , 8Y8-
BUSOP is a field of BRANCH that defines conditional branching.

In such a configuration, read/write processing to the system memory IO connected to the system bus 1 is as shown in FIG. When a read/write request for data in the system memory ``0'' is issued from the arithmetic unit 5 to the microsystem bus (b in the same figure) in synchronization with the RPC (see figure 1), the output of the pipeline register 7 is sent to the memory. The load signal is taken into the address register 8 (0 in the same figure), and the read address data from the S register 8 (f in the same figure) is output to the t-system bus 1 side (d in the same figure).
address of the memory 10, and at the same time gives a read command (in the figure) to the memory 10. This),
The data at the address (g in the figure) is read from the memory 10 to the system bus 1, and this data is written to the memory data register 4 by the p-do signal from the pipeline register 7 (h in the figure). The data is read out onto the microsystem bus 2 (j in the same figure) by the output enable signal (the same figure) from the register 7, and the data is read out onto the microsystem bus 2 (j in the same figure), and
Used for input or address data to the sequencer 6. Data writing to the memory 10 is performed using a similar procedure. ``In such read/write processing, the output of the sequencer 6, the contents of the memory 8, and the output of the pipeline register 7 are as shown in FIG. 9 when reading the microphone quadrature program instruction.

Problems to be Solved by the D0-Start Mill In the conventional configuration, there was a problem in that the access time for data read/write processing from system memory "0" was long. To shorten this access time.

There are cases where the microprogram control clock is set to a high frequency, but in this case an expensive fuse ROM is required as the microprogram memory 8, and its power consumption also increases. 'Still, for read/write processing from the system memory 10, there is no data transfer via the system bus 1t-, and occupancy of the system bus 1 becomes a problem.Means and actions for solving the E0 problem □Book In view of the above-mentioned problems, the present invention employs a RAM configuration for the microphone memory, writes program data from the system memory to this memory by bootstrap control, executes the microprogram, and updates the system memory. By writing data to the RAM-configured microphone system data memory and reading/writing data to the system memory from the micro-system data memory, microprogram control can be executed at high speed using the RAM-configured memory. It is something to do.

F. Example FIG. 1 is a circuit diagram showing a detailed example of the present invention.

System bus 1 has system memory '0'.

A bootstrap memory (ROM) 11 is coupled. The output of the sequencer 6 is connected to a bootstrap microprogram memory 8A composed of a P-ROM and an RA.
The address data is the microprogram memory 8B having an M configuration and the microsystem data memory +OA having a RAM configuration via a multiplexer +2A'e. The outputs of the program memories 8A and 8B are output as data and control signals for regulating the next address through the pipeline register 7A. Furthermore, the data to be used in the calculation in the program memory 8B and the read data in the data memory IOA are selected by the multiplexer 12B and taken into the pipeline register 7B, and the output of this register 7B is transferred to the microsystem bus 2. micro system bus 2
A micro memory address register 8A and a micro memory data register 4A are coupled to each other, and the output of the address register 8A is sent to a sequencer 6 by a multiplexer 12A.
A selection is made between the address data output and the address data of the microprogram data memory +OA.

The output of the data register 4A is made the data input of the data memory 10A.

Memo IJ8A, 8B becomes data output enable with selection signal 8ELO, and multiplexer 12A,
12B selects register 8A and memory IOA with selection signal SELI.

In this configuration, the microwords are ALU and μm8EQ, as shown in Figure @2.

5YS-BUSOP, μ8YS-BUSOP.

BRANCH, the contents of the memory 11 are stored in the memory IOA by bootstrapping, and the memo! Obtain the board data for JIOA75. Hereinafter, the operation t in FIG. 1 will be explained in detail with reference to the time charts in FIGS. 8 to 5.

First, when the power is turned on, bootstrap control is performed.5.
/(When the power is turned on, the bootstrap memory 11 is connected to the system bus 1 by the sequence of 8 memories.
The memory 8BK stores microprogram data, and the memory A stores control data. This data transfer is performed in the same manner as reading data from the conventional system memory 10, and when the data transfer is completed, the microprogram sequence is transferred from the memory 8A to the memory 8B.

Thereafter, the microprogram by the microprogram memory 8B is executed. Operations corresponding to read/write operations for the conventional system memory 10 for executing this microprogram will be described below.

(a) Read operation As shown in FIG. 8, read address data from the arithmetic unit 5 is set in the micro memory address register 8A,
The data in this register 8A is sent to the address of the memory 10A by the selection signal 8EL1 through the multiplexer 12At-, and the output data of this memory IOA is sent to the address of the memory 10A by the selection signal 8EL1.
It is taken out as the output of the multiplexer 12B by 1L1, taken out as the output of the line register 7B by the primary clock timing, and taken in to the arithmetic unit δ through the microphone system path 2.

Therefore, data reading does not require any direct read operation to the system bus 10, resulting in a high-speed read operation from the memory 10^, and the system bus 1 is not occupied.

(b) Write operation As shown in Figure 4, the write address data from the arithmetic unit 5 is set to the micro memory address register 8Ak.
Activate the data bus of the register 8A by the selection signal BEL1, and at the same time write the write data from the arithmetic unit 5 to the micromemory data register 4AK-1)';
Data 1* of the register 4A is written to the memory IOA by the write control signal μWR.

Therefore, data writing also becomes a high-speed write operation to the memory 10A.

Next, a data write operation to the microprogram system memory IO is performed in the procedure shown in FIG. The arithmetic unit 5 outputs the write address and data directly, or uses good data from the memory 10A, etc., and sets the address in the register 8, and sets the address in the data register 4.
(by setting register 8.4 to active) address and data are placed on system bus 1 through each path.

Writing to the system memory 10 is performed by the scrubbing control signal WR.

Effects of the G1 Invention and More 91 According to the present invention, writing is performed in the program memory of the microphone using the RAM f: using a boot strap, and the system memory is read/write from the micro V stem formed by the fRAM. 'Since execution is performed on data memory, high-speed microprograms can be executed on inexpensive RAM, and the power consumption is reduced, thereby increasing efficiency during debugging.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an instruction field in Fig. 8, and Fig. 6 is a read, write and system diagram in Fig. 11. Each time chart of memory write. Figure 6 is a conventional circuit diagram, Figure 7 is a conventional instruction field, Figure 8 is a conventional read/write time chart, and Figure 9 is a conventional circuit diagram.
The figure is a chart of a conventional program readout tie. l...System bus, 2...My jlo system bus. 8...Memory address register, 4...Memory data register, 5...Arithmetic unit, 6...Sequencer,'
7 A. 7B'... Pipeline register, 8A... Micro program memory for bootstrap, 8B... Micro program memory, 10... System memory,
IOA...Micro system data memory, 11...
・Bootstrap memory, 12A, 12B・
...Multiplexer.

Claims (1)

[Claims] The microprogram memory has a RAM configuration, program data is written from the system memory to this memory by bootstrap control, and the microprogram is executed. Data in the system memory is written to the microsystem data memory with the RAM configuration, and data is written to the system memory. A memory access method characterized in that data read/write is executed on the microsystem data memory.