JPS61283935A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS61283935A
JPS61283935A JP12649185A JP12649185A JPS61283935A JP S61283935 A JPS61283935 A JP S61283935A JP 12649185 A JP12649185 A JP 12649185A JP 12649185 A JP12649185 A JP 12649185A JP S61283935 A JPS61283935 A JP S61283935A
Authority
JP
Japan
Prior art keywords
data
output
register
memory
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12649185A
Other languages
Japanese (ja)
Inventor
Wataru Iijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP12649185A priority Critical patent/JPS61283935A/en
Publication of JPS61283935A publication Critical patent/JPS61283935A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform the control of a microprogram at a high speed by writing the microprogram data to a system data memory having a RAM constitution and performing the reading/writing operations to the system data memory.
CONSTITUTION: The read/write address data is set to a micromemory address register 3A from an arithmetic unit 5. In a read mode this data is used as the address of a memory 10A by a selection signal SEL1 via a multiplexer 12A. Then the output data is extracted by the SEL1 as the output of a multiplexer 12B and then as the output of a pipeline register 7B with the next timing. This output is fetched by the unit 5 at a high speed through a bus 2. In a write mode the data bus of the register 3A is activated by the SEL1. Then the write data is set to a register 4A from the unit 5 and then written at a high speed to the memory 10A by a write control signal μWR.
COPYRIGHT: (C)1986,JPO&Japio
JP12649185A 1985-06-11 1985-06-11 Memory access system Pending JPS61283935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12649185A JPS61283935A (en) 1985-06-11 1985-06-11 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12649185A JPS61283935A (en) 1985-06-11 1985-06-11 Memory access system

Publications (1)

Publication Number Publication Date
JPS61283935A true JPS61283935A (en) 1986-12-13

Family

ID=14936522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12649185A Pending JPS61283935A (en) 1985-06-11 1985-06-11 Memory access system

Country Status (1)

Country Link
JP (1) JPS61283935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5417832A (en) * 1992-08-25 1995-05-23 The University Of Colorado Foundation, Inc. Enhancing performance of perfluorinated ionomer membranes via dopant incorporation, method of making thereof and the membrane

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5417832A (en) * 1992-08-25 1995-05-23 The University Of Colorado Foundation, Inc. Enhancing performance of perfluorinated ionomer membranes via dopant incorporation, method of making thereof and the membrane

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