JPS62168247A - Memory bank switching system - Google Patents

Abstract

PURPOSE:To branch the generated bank selection signals into the designated addresses by executing a branch instruction after providing a bank switching circuit only to an address bus of a program memory. CONSTITUTION:A branch instruction A whose branching destination is set at 'A' of a bank 0 of a program memory in case the programs execution of a bank 1 is needed while a CPU 1 is executing the program of the bank 0. When the instruction A is executed, the branch address 'A' is inputted to a bank switching circuit 13 through an address bus 7 for program memory. Thus a selection signal 19 is produced to the bank 1. Hereafter the bank 1 is enabled by the signal 19 at a time point when a branch instruction B is executed. Thus the branching is possible to the bank 1 with execution of the instruction B.

Description

[Detailed Description of the Invention] [Summary] A program memory each consisting of a plurality of banks;
In a computer system where the data memory address bus is separate, a jump subroutine instruction or a branch instruction branches to a specified address, and a bank switching circuit is provided only on the program memory address bus. By executing a branch instruction, a bank select signal for switching banks is generated, and when the bank is switched, a branch can be made to the address specified by the instruction.

[Industrial application field]

The present invention relates to a memory bank switching method in a computer system in which a program memory and a data memory each having a plurality of banks have separate address buses.

For example, in ultrasonic diagnostic equipment, etc., it is necessary to read image signals from a living body and perform image processing in real time.
High speed and securing the amount of memory to store two image data are essential conditions.

On the other hand, with the recent improvement in the performance of computer systems, small computer systems such as microcomputers have come to be used in the field of ultrasonic diagnostic equipment.

In general computer systems where operand access and operand access are carried out on a single bus, there is a problem in that the processing capacity required for the ultrasound diagnostic equipment cannot be obtained due to a bus bottleneck. A computer system with separate data buses is used, and a plurality of memory banks are connected to the address bus and data bus to ensure the amount of memory necessary to store image data.

However, in small computer systems, there is no special control line for switching memory banks, so for example, bank switching information is sent to the address bus and a bank select signal is generated using the decoded information. There is a need to.

Furthermore, since image data handled by an ultrasonic diagnostic apparatus requires continuous memory of, for example, one word/line, it is required to be able to access several banks of memory continuously without interruption.

[Prior art and problems to be solved by the invention] FIG. 4 is a diagram showing a conventional memory bank switching system.

Generally, in computer systems where program memory and data memory are separated, it is not allowed to write data to the program memory, but it is possible to write arbitrary data to a specific address in the data memory. Therefore, in the conventional memory bank switching method, as shown in the figure, a decoder 1) is provided on the data memory address bus 5, and a specific address sent to the bus is decoded and the bank switching circuit 13
, and generates a bank select signal 19 for selecting a specific memory bank from the data on the data bus 3.

Therefore, in the conventional method, the area of the data memory 15 corresponding to the data memory address for activating the bank switching circuit 13 cannot be used as a general data area, so it cannot be used as a general data area. There was a problem that it was not suitable for continuous use.

In view of the above-mentioned conventional drawbacks, the present invention provides a program memory,
The purpose of the present invention is to provide a method for simplifying the bank switching circuit and enabling efficient data memory use by using only the program memory address bus in a computer system where the data memory address bus is separate. That is.

[Means for solving problems]

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the present invention, in a computer system in which address buses for a program memory 17 and a data memory 15 each consisting of a plurality of banks are separated, only the address bus 7 for the program memory is used to connect the program memory 17 and the data memory 15. When performing the above bank switching of data memory 15, the central processing unit of the computer system (
A bank switching circuit 13 is provided that generates a bank select signal 19 by the CPU (CPU) 1 issuing and executing an instruction (for example, a branch instruction) that can specify an address from which an arbitrary bank of the program memory 17 can be selected;
The bank switching circuit 13 is configured to decode the branch address and generate a bank select signal.

[Effect]

That is, according to the present invention, in a computer system in which a program memory and a data memory address bus each consisting of a plurality of blocks are separated, a jump subroutine instruction or a branch instruction branches to a specified address. By using this function, a bank switching circuit is provided only in the address bus of the program memory, and by executing the branch instruction, a bank select signal for switching banks is generated, and when the bank is switched, the instruction is Since it is possible to branch to the address specified by , even if an instruction to switch banks is executed,
This has the advantage that the data memory can be used continuously without using a specific area of the data memory.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a map diagram of a program memory when the present invention is implemented, and FIG. 3 is a diagram showing a memory bank switching operation according to the present invention. 2 is a time chart diagram showing the bank switching circuit 13 in FIG. 1. and its related mechanisms are functional blocks necessary to implement the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

First, the operation when switching the banks (0 to n) 17 of the program memory will be explained with reference to FIGS. 1, 2, and 3.

When central processing unit (CPU) 1 is executing a program in bank O of program memory and it becomes necessary to execute a program in bank 1 of program memory, it issues a branch instruction A whose branch destination is "A" in bank 0. Execute.

Prepare another branch instruction B for the branch destination IAI,
The branch destination is set to an arbitrary address in bank 1 (for example, address O).

In this state, when the branch instruction A is executed, the branch address °A' is transferred to the program memory address bus 7.
is input to the bank switching circuit 13 through the bank 1
A bank select signal 19 is generated for.

Therefore, when branch instruction B is executed after that,
At that point, the bank 2 is enabled by the bank select signal 19, so that the branch to bank 1 can be executed by executing the branch instruction B.

A time chart showing the operation at this time is shown in Fig. 3.The central processing unit (CPU) 1 has an instruction fetch register (rFR) and an instruction execution register (IER).
Between these two registers, as shown in the figure,
It works like a vibe line.

As is clear from this figure, when branch instruction A is set in the instruction execution register (IER) and executed, a bank select signal is issued and banks are switched. When the branch instruction B prepared at the branch destination is moved to the instruction execution register (rER), bank switching has been completed and execution of the branch instruction B is guaranteed.

Next, the switching operation of the data memory banks (0 to m) 15 will be explained using the same diagram as above.

When switching data memory banks, a jump subroutine instruction is prepared instead of the branch instruction.

This jump subroutine instruction executes the branch destination instruction (for example, a no-operation instruction) specified by the instruction, and returns to the address next to the jump subroutine instruction (specifically, the branch destination address is This is an instruction that is only sent to the program memory address bus 7 and does not actually branch.

Therefore, by setting the branch destination address of the jump subroutine instruction to, for example, an address that can select bank 1 of the data memory, when the jump subroutine instruction is executed, the address bus 7 for program memory is As a result of the address being sent out and input to the bank switching circuit 13, a bank select signal 19 for selecting bank 1 of the data memory is generated.

As is clear from the above operation, when the present invention is implemented,
Each bank of program memory has program memory provided in this computer system.

It is necessary to allocate an address (n+m) for selecting a bank corresponding to the number (n+m) of banks of the data memory.

In the map shown in this figure, continuous areas are allocated, but considering the gist of the present invention, it is clear that continuous areas do not necessarily have to be allocated.

As described above, the present invention uses an instruction that can specify a specific address in a program memory, such as a branch instruction, to send the branch destination address to the program memory address bus, and send the address to the bank switching circuit. The feature is that it is decoded and a bank select signal corresponding to each address is generated.

〔Effect of the invention〕

As described above in detail, the memory bank switching method of the present invention is useful for jump/subroutine instructions or branching in computer systems in which program memory and data memory address buses each consisting of a plurality of banks are separated. Using the function that allows instructions to branch to a specified address, only the address bus of the program memory is used.
A bank switching circuit is provided, and by executing the branch instruction, a bank select signal is generated to switch the bank, and when the bank is switched, the branch can be made to the address specified by the instruction. Therefore, even if an instruction for bank switching is executed, a specific area of the data memory is not used, and the data memory can be used continuously.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a program memory map diagram when the present invention is implemented. FIG. 3 is a time chart diagram of the memory bank switching operation according to the present invention. FIG. 4 is a diagram showing a conventional memory bank switching method. It is. In the drawing, 1 is a central processing unit (CPU) and 3 is a data bus. 5 is an address bus for data memory. 7 is an address bus for program memory. 1) is a decoder, and 13 is a bank switching circuit. 15 is data memory, 17 is program memory. 19 is a bank select signal. are shown respectively.

Claims (2)

[Claims] (1) In a computer system in which address buses for program memory (17) and data memory (15) each consisting of a plurality of banks are separated, a bank select signal (1) is sent to address bus (7) for program memory.
9) A memory bank switching method characterized in that a means (13) for generating the data is provided to switch between the banks of the program memory (17) and the data memory (15). (2) means (13) for generating a bank select signal (19) on the address bus (7) for the program memory;
In order to perform the bank switching between the program memory (17) and the data memory (15), the central processing unit (CPU) (1) of the computer system is provided with a By issuing and executing an instruction specifying an address for selecting an arbitrary bank in (15), the bank select signal (19)
The memory bank switching system according to claim 1, characterized in that the means (13) for generating .