JPS6142035A - Logical type information processor - Google Patents

Abstract

PURPOSE:To expand a memory access space by setting an address for a memory access to four times at the time of read/write of a data with a tag, and converting it to an address of a word unit, in a logical type information processor. CONSTITUTION:An address for an access of a memory 10 is set to a register 30. At the time of read, a read-out data is set to a register 20, a result is sent to a microprogram controller 70 through an instruction and a tag decoder 50, and at the same time, an operand is sent to a register fiel 80 or a bus 90 through a tag mask circuit 60. At the time of write, a write data is set from the bus 90 and write is executed to the memory 10. At the time of read-out of a data with a tag, a shifter 100 shifts an address obtained from the bus 90, to the left by 2 bits in response to a shifting signal 201 and sets to four times, and sends out a read- out use address to the register 30.

Description

[Detailed description of the invention] [Criminal field of the invention] This article is based on a predicate theory similar to Prolog l111
In an information processor 311 II suitable for language execution, a tag section for identifying data attributes and a limb data section are included in one word.

Theory of having a method for expanding memory space] III Information Processing Device KI! do.

[Background of the invention]

FOR'rRAN Procedural language II (Pro@sdwral Lan)
gtIage), procedures and data are separated.

Prolog-like theory] In 1mtIl, depending on the evaluation of the data, [the processing content is determined.

Therefore, in order to efficiently execute such a logic language, fields for representing data attributes,
j! A second tag (T1) section is added to all data.

In this way, it is possible to concentrate data attributes in the tag part.
Therefore, the Akebono-dokoro system is K so that the processing can be performed more than K by evaluating the tag part.

Theory 11 mentioned above! ! It can improve language processing efficiency.

By the way, in many recent information processing devices, the basic data length is 32 bits, that is, 4 bytes, so while maintaining the bit length (32 bits) that represents this data, the 1-bit tag part is , the basic word length is generally one bit longer than 52 bits, as shown in FIG. 1(a)K.

For example, the New Generation Combination Technology Development Organization (LK)
Machine φQ logic 7'o/ announced by IC0T)
Ramin f '85 Con 7 Arens Record 7.2 (1
In 985)@, 1ml is formed by a 32-bit voice part and an 8-bit tag part.

Therefore, in machine φ, the length of the data part is 52 bits, but the length of one word is 40 bits.

Furthermore, if the 111 length is different from the bit length of the data, it becomes difficult to mix with the conventional mid-chip texture whose basic word length is 52 bits. Also.

Linkage with languages such as FORTRAN 4P Pa5cal will also become difficult.

Therefore, as a countermeasure to this problem, a method can be considered in which both the tag part and the data part are included in the basic word length of 52 bits, as shown in FIG. 1(b) K. With this method, the above-mentioned problems can be solved.

However, because 1 ml of the 52 pits, which have the basic word length, is allocated to the tag section, the bit length of the data section becomes shorter - that is, the number of bits for address specification decreases, and the memory access space becomes narrower. There was a drawback.

[Purpose of the invention]

An object of the present invention is to provide an information processing device.

A means is provided that can obtain sufficient memory access space even when the tag section and the data section are placed in the S2 pits F, which has the same basic word length as the conventional information processing 11 device.

There is a theory that provides an information processing device.

[Summary of the invention]

All the data handled by the W1 information processing device is added with a ℃gu, and memory access for reading and writing data is only in word units.

On the other hand, in an information processing device, addresses of one normal memory are assigned in units of bytes.

Therefore, when reading or writing tagged data, the memory access space can be expanded by multiplying the address for memory access by 4 (shifted 2 bits to the left) and converting it into a word unit address. .

The present invention has been made by paying attention to the above-mentioned circumstances, and has the following features: (l) one word is composed of 2n bytes, side) addresses are allocated in byte units, and K (to)) word units. to access.

Assuming that, by shifting the address for accessing the tagged data to the left by n bits (multiplying it by 2''), it becomes possible to access in word units and expand the access space. There is 41 mold at the point where I made it 5.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 6 ml.

FIG. 2 is a block diagram showing the overall configuration of an example of a logical information processing device to which the present invention is applied.

The processing device includes MEM + O, read register (RDR) 2G, and memory address register (MA).
R)80. phytodata register (WRD) 40,
Instruction and Tag Decoder (DIIC) 50. Tag mask circuit (M8K)60. Microprogram controller (
MPC) 70. Arithmetic logic unit and register 7 aisle circuit (RALU) 8G, bus (BU8) 90. and a shifter (SFT) 100 to quadruple the memory address
The main components are:

MAR 110K is set with an address for memory access to MEN 10. In the case of memory read, Ml! ! The data read from MIQ is set in RDR20.

In addition, in the case of memory write, first set the write data to WDR40 via BU890, and then
Writing to MgMIO is performed.

The instruction or operand read from MEM to and taken into cRDR20K is decoded by the DEC 60 (in the case of an operand, only the tag part is decoded). If the result of the decoding is the signal $
Sent from I200K to MP07G.

On the other hand, the RD120K imported operand is
The tag part is masked from 60K on MA8 and RAL
U 80 V distaff file or BU 890 K sent.

Eil'T too responds to the bit signal 201 generated from the MpC 7o when reading tagged data, and shifts the address 210 obtained from the BU 89O to the left by 2 bits, that is, multiplies it by 4.

Then, the BPT +00 sends out an address 20 for staring at the MAR110K.

The MPC 70 generates various signals for controlling the entire IJM information processing device.

The fifth W is a block diagram showing details of the MPC 70.

The MPC70 has a memory (WO2) 7 that stores microprograms, and a microinstruction register (MIR) 72 that stores microinstructions read from the WC871.
．． A selector (sgL) 7s that selects the address of the microinstruction to be read next; a circuit (coN) 74 that synthesizes addresses to perform multi-branching based on tag determination; The main component is an incrementer (INC) 75 that creates an address for reading the next microinstruction.

Figure 4 shows the brass shown in Figure 2] Il! I! FIG. 3 is a diagram showing an instruction format used in the information processing device. As is clear from the figure, K, one bit (in the illustrated example, the most significant bit)+10 is an assignment value to indicate whether or not tagged data is to be accessed.

For example, the 41st! The most significant bit of i+ ■0 means that ``no access is made to the tagged data''. means to have access to.

Further, the remaining digits of the instruction 7#-mat (the part indicated by the car mark in FIG. 4) Klt'01 or 111 are assigned.

In the DIC 50 shown in Figure 2, when decoding the instruction format transferred from the RDR 20, #instruction 7# - a bit indicating whether or not to access tagged data in the mat (hereinafter referred to as a single Kll specific bit) , and outputs the pre-purchased address of the microprogram corresponding to the cough command format to the signal line 200K.

Next, the operation of the MPC7G will be explained using Figure 5.

As mentioned above, the result of decoding the instruction is signal 1III.
Sent from 200. FJ the decoded instruction
It is selected by EL78 and output as an address to WCI97+. From this k, the microinstruction corresponding to the instruction is read out and sectored into the MIR 72.

絖L"C, IIM I R72K Depths the set microinstruction. At this point, the microinstruction is

If it is a set of main read addresses for reading or writing tagged data, MIlt72 to 8
A shift signal 201 to F〒100 is output.

Normally, one instruction consists of a plurality of microinstructions, so in order to read the first microinstruction, the INC75 increments the address of the current microinstruction by one and inputs it to the 8EL7M.

Further, as mentioned in 5 above, in the case of a new era, the processing is determined by the evaluation of the data.

In FIG. 3, the signal (signal on signal $9200) is the result of decoding the tag part of the read data.

MIR72 car tag judgment signal 20B and C0N74
By supplying K and synthesizing the addresses of microinstructions for performing processing corresponding to the data, the above processing decision is realized.

Since such a method of synthesis is already known, its explanation will be omitted.

#I5 diagram shows 8F when one word consists of 52 bits.
I will show you the details of 'r too. The SF? +00
is composed of two human-powered AND gates 101 to 164, two human-powered OR gates 165 to 1971, and an inverter 199.

Next, the operation of FIG. 5 when 4 bits out of the 52 bits of the basic word length are used as the tag part will be explained using FIG. 6.

In Figure 2.5 1, shift signal 2 from MPC 70
If 01 is not an important text (it is in a low state),
By inverter 199, odd numbered AND)
101, log, . . . 16δ is selected. Therefore, the input signal (address) 2IO to the SFT tGo is directly output as the input signal (address) 20 to the fMAR 50.

As a result, as shown in FIG. 6(1)K, the address 210 is set in MARMOK with the upper 4 bits assigned to the non-1 tag part being used as an address masked.

That is, in the same figure (@), IO- or '1# to represent address 20, which is the same as address 21[1, is sected to the 0th to 27th bits on the lower side of MARMO, but the upper bits are 28-51 bits all have IQ
I is set.

On the other hand, the second. In Fig. 5, when the shift signal 201 is output from MP070 (resulting in H gift card 11), even numbered AND goo) 102, 104. −・・・・・
164 will be selected.

At this time, as is clear, the input signal (address) 210 to 8FT +00 is entirely shifted to the left by 2 bits, and the lower 2 bits are set to 1O1.
It is output as an input signal (address) 211 to 0.

As a result, as shown in FIG. 6(b)K, the MAR 50 receives a new address 211 that is four times the input signal 210, which is the address sent via the BUS 90.
Set as address to MKM 10.

At this time, if the upper 2 bits of the original address of 1 are truncated, it becomes 5, but the upper 2 bits are allocated to the tag part and cannot be used as an address. There will be no problem since it will be done immediately.

As described above, since the address 211K set in the MAR 501c accesses the MEM 10, the memory access space can be quadrupled.

In addition, in the above, an embodiment was described in which one word consists of 4 bytes, that is, 2t bytes, but the present invention can generally be expanded to the case where one word consists of 2n bytes. It is.

In other words, one word consists of 2!1 bytes,
When addresses are read in bytes and memory is accessed in words.

When accessing tagged data, move the address part to the left.
By extracting bits, the memory access space is reduced by 2.
It can be tripled.

The embodiment shown in FIGS. 2 to 6 compiles a program written in the Ronmei language into an instruction format.1. Although a compiler system is shown in which each instruction is executed, the present invention is not limited to this, and may be applied to an interpreter system that interprets and executes a program.

In the case of an interpreter method, all memory access modes can be unified in word units. Therefore,
A mode flag indicating that the interpreter is operating is provided, and if this 7 lag is set, all addresses for memory access can be shifted to the left by n bits.

〔Effect of the invention〕

According to the present invention, in a logical device information processing device.

While keeping the basic word length the same as the conventional information processing W1a location.

Memory access space when data and a tag section indicating the attributes of the data are included in the basic word length.

4 times more than without the present invention (generally 2" times)
By expanding by K, it becomes possible to obtain sufficient memory space even when constructing a practical system using the @san type language.

[Brief explanation of the drawing]

111I is a diagram showing the data format used in the information processing device, FIG. 2 is a block diagram showing the overall configuration of the information processing device, which is an embodiment of the present invention, and FIG. Connection 21
1 in 1 Mike Ga Progera A:l Controller (MP
C) detailed page diagram; 4th all is a diagram showing the instruction format used in the logic information processing device shown in FIG. 2;
Figure 5 is now Figure 2! 1 is a detailed boot diagram showing the configuration of the 8FT. FIG. 6 is an explanatory diagram of the operation of the shifter (8FT) shown in FIG. 10...Memory (MUM), 20...Read l
/ Raster (RDR), ! O...Memory address register (MAR), 40...Write data register (WRD), 60...Instruction and tag decoder (DEC), 60...Tag mask circuit (M8K
), 70... Micro program controller (MP
C), 71...Memory (WO2). 72...Micro instruction register (MIR).

Claims (3)

[Claims] (1) Logical type information that includes a memory for storing tags and data, one word is composed of 2^n bytes, addresses on the memory are assigned in byte units, and the memory is accessed in word units. In the processing device,
A read register that temporarily stores data read from the memory, and an instruction taken into the read register,
a decoder that recognizes whether tagged data in the memory is to be accessed; a microprogram controller that is supplied with the output of the decoder and generates predetermined shift and mask signals; A tag mask that masks the tag part of the memory contents of the register and supplies it to the arithmetic and logic unit and the register file circuit or the bus, and a tag mask that masks the tag part of the memory contents of the register and supplies it to the arithmetic logic unit and the register file circuit or the bus, and the masked signal as described above is input as an address signal and the shift a shifter that outputs the address signal as is when no signal is generated, and shifts the address signal to the left by a predetermined bit when the shift signal is generated; and means for accessing the memory according to an output address of the logical information processing apparatus. (2) The logic type information processing device according to claim 1, wherein the masked signal is input to the shifter via an arithmetic logic unit and a register file circuit, or a bus. (3) The logical information processing device according to claim 1 or 2, wherein the planned number of bits is n.