JPS62297938A - Microprogram controller - Google Patents

Abstract

PURPOSE:To obtain a constant having a large range of expression with a single microinstruction by delivering the contents of the 2nd field of a holding means to only one of plural data generating means and connecting the outputs of other data generating means to use them as the constant data. CONSTITUTION:The selection signals SELO, 1, 2 and 3 are active when the byte position information BYTO/1 is equal to '00', '01', '10' and 11 respectively. The lower 8 bits of an instruction field and outputted to the outputs of the 8-bit data generating means 110-113 selected by signals SELO-3. However the zero data of 8 bits are outputted to the outputs of three sets of means 110-113 which are not selected since a 2-bit decoder 115 produces those signals SELO-3 so that they are exclusively active. Thus it is possible to obtain a 32-bit constant that sets the 8-bit data at an optional byte position.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to a microprogram control device.

In particular, it relates to means of generating constants used within microprograms.

[Conventional technology]

Generally in microprogrammed control devices.

A microprogram consisting of a series of microinstructions is stored in a control memory 201 as shown in FIG. 2, and is sequentially read out every microinstruction cycle and temporarily stored in a microinstruction register 202. After that, the output of this microinstruction register is sent to microinstruction decoder 2.
By decoding with 03, the information specified by the micro operation instruction (micro order) aaa-zzz
is generated and given to each control point such as the register file 204 and the arithmetic and logic unit 205.

Computes a microinstruction for transferring data between the register file 204 and the arithmetic and logic unit 205 via the data bus 206; computes a microinstruction to specify the type of operation in the arithmetic and logic unit; Control memory 201 stores microinstructions to be executed next to determine the sequence of microinstructions and microprograms.
A microinstruction that specifies a branch microinstruction is called a branch microinstruction, and a microinstruction that controls a control point that cannot be controlled by these microinstructions is called a control microinstruction.

As shown in Figure 3a, the microinstruction format is transfer, arithmetic, branch, and control microinstructions that are identified by the state of a specific bit or bit string (this bit or bit string is called an identifier ID) of some microinstructions. There is something to be done.

The function of each instruction is determined by other bit strings (function field F
With this instruction format (referred to as UNC), the instruction word length is short, so the control memory capacity is small. It has the disadvantage of being opposite.

On the other hand, as shown in Figure 3, all information regarding transfer, calculation, branching, and control functions is included in one instruction (
The respective fields are referred to as transfer field TRN, operation field Op, branch field BR1 and control field CNT. Since branching and control functions are rarely needed, unnecessary information is often included in microinstructions. The disadvantage is that there is little information.

Generally, as shown in Figure 3C, one instruction is assigned a dedicated field (here, the TRN for transfer instruction is assigned).
By flexibly changing the function of a microinstruction by having a field with a variable function, we have created a microinstruction format that has a short word length and can control multiple control points in one microinstruction cycle. There are many choices.

A transfer microinstruction specifies a register resource from which data is transferred, called a source operand, such as a register file or an arithmetic unit, and specifies a register resource at a destination, called a destination operand. However, register resources are not the only source operand resources (constants required in the microprogram may be selected).

If there are only a few types of constants used in a microprogram, the constants are fixed in constant registers in advance and designated as source operands as register resources. However, this method has the disadvantage that it is extremely inflexible because it is not possible to change the constant once set.

Another method for generating constants is to provide a field called a constant field as part of a microinstruction, and when a constant is specified as a source operand by a transfer microinstruction, the information in this field is transferred as a constant. . If a constant field is dedicated to a specific part of a microinstruction, it will contain useless information if the constant is not specified as the source operand of a transfer instruction. It can be considered to be used as

For this reason, the number of bits in the constant field is relatively smaller than the basic word length for data processing (16 to 32 bits for the internal bus) (about 8 bits for the basic word length of 16 to 32).
The R range of constants that can be expressed is also limited (8 pits and O~
255).

Next, an example of a conventional microinstruction format, particularly the structure of a constant field, will be explained with reference to the drawings.

FIG. 4 shows an example of the microinstruction format, which is composed of a transfer field 401 and an instruction field 402 specifying one branch or control of an operation. The transfer field 401 includes a field 403 (hereinafter referred to as S
RC field) and a field 404 for specifying a destination operand (hereinafter referred to as DST field). Furthermore, the instruction field 402 is
The meaning of the function field 406 changes to a calculation, branching, or control field depending on the value of the identifier 405, which is composed of an identifier 405 and a function field 406.

However, if a constant is selected as the 5R-c field 403, the identifier 405 and function field 406 (ie, instruction field 402) are invalidated in their conventional meaning and are used as a constant field.

FIG. 5 is a diagram showing the configuration of a microprogram control device that employs microinstructions having the conventional instruction format. With reference to this drawing, data transfer in the microprogram control device, particularly constant transfer operation, will be described. The microinstruction stored in control memory 502 specified by microaddress register 501 is stored in microinstruction register 503. The output of the micro-instruction register 503 is connected to the micro-instruction decoder 504, which outputs the micro-order I according to the contents of the transfer field and the instruction field (outputs src and id corresponding to the SRC field and identifier ID at 1%).
Generate MD, OPR, BR, and CNI. The micro-order IMD indicates that a constant was specified as the source-operand in the SRC field 403. Micro order 0 PJBit, CNI 4 @ identifier 40
5 This indicates that the operation, branching, and control functions are specified. However, the micro-orders of IL and CNT (8 in SaC field 403 (0PJ if a constant is specified as the source operand)) are not generated. The output func of the microinstruction register 503 corresponding to the function field 402 is:
Each is connected to an arithmetic control device 505, a branch control device 506, and a control device 507, and each control device is a micro-order OPa, Bl (.

When CNT becomes active, it interprets the contents of fune and generates further subdivided micro-orders.

5L (IC field 403 and DST field 4
Output sr of microinstruction register 503 corresponding to 04
c and dst are bus 523
and source operand decoder 510 via destination operand bus 524, respectively.
and destination operand decoder 51
Connected to 1. Source operand decoder 510
generates a read selection signal RDn for register file 521 connected to data bus 520 according to the contents of src. Data in register Rn in register file 521 corresponding to read selection signal RDn is read onto data bus 520.

Meanwhile, the testing operand decoder 511
generates a write selection signal WRn for register file 521 according to the contents of dst. Register file 521 corresponding to write selection signal WRn
The data on the data path 520 is written to the register R,n in the register R,n. Source operand decoder 51
0 and destination-operand decoder 5
11 generates a read selection signal RDn and a write selection signal WRn for the register file 520, as well as a read selection signal READn and a write selection signal WRITEn for other register resources 522 connected to the data bus 520. Data Bus in Method 5
Controls data transfer between register resources via 20. When a constant is specified in the SRC operand field 403 and a micro-order IMD is generated by the micro-instruction decoder 504, the constant buffer 512 to which the output op of the micro-instruction register 503 corresponding to the instruction field 402 is connected is selected, and Op is the data・Pass 5
It is output to the 200 lower order. At this time, the constant buffer 512
The upper side of OP outputs a plurality of 0s to the upper side of data bus 520 and zero-extends the contents of OP.

[Problems to be solved by the present invention]

During the conventional constant transfer, if a constant larger than the value that can be expressed in the instruction field 402 (hereinafter referred to as a long immediate, and a constant that can be expressed in the instruction field 402 is referred to as an immediate) is generated, it is called an immediate transfer. A long immediate must be generated using arithmetic instructions such as multi-bit shift and OR, and many microinstructions are required to generate a long e-immediate.

In one example, data bus 520 is 32 bits wide;
If the instruction field 4020 bit width is 8 bits, the values that can be expressed as an immediate are 0 to 255.
(0 to 28-1), 32-bit long
To obtain an immediate, it is necessary to execute a microinstruction as shown below.

■ Transfer the 8-bit immediate to register R1.

■ Shift the contents of R1 to the left VC8 bits.

■ Add new 8-bit immediate to register I (2
Transfer to.

■ Store in the logical sum of R1 and R2.

■ Repeat steps from ■ to ■ twice.

In this way, it is necessary to execute 10 steps of micro-instructions and to provide one insufficient register (processor 2) for calculations to obtain a long Φ immediate of 32 bits in register RIK.

[Means for solving problems]

The present invention provides means for temporarily holding microinstructions, means for detecting a bit pattern of a first field of said holding means, and a plurality of bits for outputting predetermined data or the contents of a second field of said holding means. the data generating means outputs the contents of the second field of the holding means to only one of the plurality of data generating means according to the bit pattern detected by the detecting means; It is characterized in that the outputs of a plurality of data generating means are combined and used as constant data.

〔Example〕

Next, the configuration and operation of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an instruction register 10
Input the output src corresponding to the 008RC field and the output id corresponding to the identifier IDK or input t, -+r or
Microinstruction decoder 1o21 selection signal 8ELQ to 5E that generates -J"IMD, OPR, BJCN'!'
When L3 is active, selects the lower 8 bits of the instruction field of the micro fo instruction register 100,
Otherwise, means 110-113 for generating 8-bit zero data. The outputs of the four 8-bit data generating means 110 to 113 are read out, and when No. 13 XMD is active, a 32-bit data buffer 114 connected to the 32-bit data bus 101, byte position a
(Selection signal 5EL is selected according to the content of W report BYTQ/l.
It consists of a 2-bit decoder 115 that generates o-8ELs. If the byte position f# information BYTO/1 is 00, the selection signal 5ELO is used, and if it is Ol, the selection signal 5ELI
If it is 10, the selection signal 8BL2 becomes active, and if it is 11, the selection signal 8EL3 becomes active. Selection signal 8BLO~8
8-bit data generation means 110 selected by EL3
The output of 113 contains the lower 8 bits imd of the instruction field.
However, since the 2-bit decoder 115 generates the selection signals 8BLo-8EL3 so as to be exclusively active, three sets of the unselected 8-bit data generation means 110-113 are output. 8 for output
Bit zero data is output. Therefore, when read signal IMD becomes active, the data output from 32-bit data buffer 114 to 32-bit e-data bus 101 is as shown below, depending on the contents of byte position information BYTO/1.

oooooooooooooooooo
o.

10 00000000 nnnnnnnnn
n11 nnnnnnnnn QOOOO
OOOBYTO/1 bit, (8,,15 pieces b
it, (o,, 7) 00 00000000
nnnnnnnnnn01 nnnnnnnn
n 00000000io ooo
ooooooooooooo.

However, here the expression bus, (x,,y) is 32
It shows the range from bit X to bit y of the bit data bus 101, and nnnnnnnnn shows the contents of func (the lower 8 bits of the instruction field).

FIG. 6a shows an example of the instruction format of the microinstruction applied to this embodiment. This instruction format consists of a 6-bit 88C field, a 6-bit DST field, and a 3-bit ID.
field and an 8-bit FUNC field. When the SBC field is 101010, specify the constant as the first operand. The ID field contains the time branching function of Qxx (X is 0 or 1), 1000
Specifies that the FUNC field, which is a 1010 hour control function, has a time calculation function, but if the SRC field is 101010, that is, if it is specified to transfer a constant, then the FUNC field specifies θ ~ 25
It is used to specify in which byte position any 8-bit data having a value up to 5 is to be placed in order to configure it as 32-bit data. That is, the ID field is
In the case of 00, XO is used as the lowest 8-bit data.
In the case of I, as the 8-bit data of the next byte,
In the case of IO, it is used to specify that it is used as 8-bit data in the next byte, and in the case of Xll, it is used as 8-bit data in the most significant byte.

Next, the operation of this embodiment will be explained.

Among the outputs of the microinstructions stored in the 23-bit wide microinstruction register 100, bits src corresponding to 8 RC fields and bits id corresponding to the ID field are connected to the microinstruction decoder 102, and the contents of the transfer field and the instruction field are connected to the microinstruction decoder 102. Micro-order IMD, OPR, BR, and CNT are generated according to the following. The relationship between the output of the micro-instruction register 100 and the micro-orders IMD, OPR, BR, and CNT is as shown below.

src id Generated micro-order 101010 XXX IMD (constant transfer) ------ OXX BR (branch function) src
id Micro-orders that occur --
--1000PR (arithmetic function) -----101CNT (control function) However, here -m--- indicates a value other than 101010.

The micro-order IMD is connected as a read signal for the 32-bit data buffer 114 and also the micro-instruction register 1000 bits.

[8]) and bit 9 (bit, (9) ) are ノ(
Bit position information BYTO/1 is connected to the 2-bit decoder 115, and bits 0 to 7 (fuoc) of the microinstruction register 100 are connected to the 8-bit decoder 115.
It is connected to data generating means 110-113.

Next, the constant generation operation in this microprogram control device will be explained.

Now 101010010 in microinstruction register 100
Assuming that the data 101 010 01111010 is held as a microinstruction, the microinstruction decoder 102 activates the microorder IMD because the src has a pattern of 101010, and writes the corresponding microorder 0PI (, BR).

Make CNT inactive. Since bits (8, 9) of the i microinstruction register 100 are 10, the 2-bit decoder 115 activates only 8EL2.
Set SEL□, 5EL1.8EL3 to ear 7 tape. Therefore, only 112 of the 8-bit data generation means 110 to 113 has the same value as func, that is, 01111.
010, other 8-bit O data generation means 110,
111 and 113 generate ooooooooo. Since the 32-bit data buffer 114 is connected to the 32-bit data bus 101iC by the micro-order IMD, the 32-bit data bus 101 has 0 bits.
0000000 01111010 Qθ00000
You can get 0oooooooo.

As explained above, by using this embodiment, a 32-bit constant with 8-bit data set at an arbitrary byte position, that is, m"(256"rl) (m is 0 to 25
5, n can be obtained as θ~3).

In this example, values from 0 to 255 (256"3) can be expressed, but the negative precision is only 8 bits, so it is difficult to obtain arbitrary 32-bit data, but the microprogram The constants used in this section often extract specific bit strings, or use data without weights concentrated on specific byte data, so they can be used as is for many applications. .

Furthermore, in order to obtain arbitrary 32-bit data, an 8-bit shift operation is not required compared to the conventional execution of a microinstruction for constant generation, so the process can be simplified as follows.

■ Transfer 32-bit immediate to register RIK.

■ Transfer the next 32 immediates to register 82;

■ Store the logical sum of R1 and R2 in R1.

■ Transfer the next 32-bit immediate to register R2.

■ Store the logical sum of R1 and R2 in R1.

■ Transfer the next 32-bit immediate to register R2.

■ Store the logical sum of R1 and 82 in R1.

Whereas the conventional microinstruction for generating arbitrary 32-bit data mentioned above required 10 steps,
It can be seen that in this embodiment, the process can be shortened to 7 steps.

Next, another embodiment of the present invention will be described.

FIG. 7 shows another embodiment of the present invention and shows a selection signal 8EL.
When O~8F, L3 is active, the lower 8 bits func of the instruction field of the microinstruction register 100 are selected. Otherwise, the output selection signal ZERO selects 8 bits.
It is characterized by having means 810 to 813 for generating 0-bit data or 8-bit all-1 data.

As in the previous embodiment, the byte position information BYTQ/1 is
If it is 0, the selection signal 5ELo is selected, and if it is 01, the selection signal 5E is selected.
If LI is 10, the selection signal 5EL2 becomes active, and if LI is 11, the selection signal 8EL3 becomes active. Selection signal 5
The lower 8 bits of the instruction field (func) are output from the 8-bit data generating means 100 to 113 selected by the ELO-8BL3, but the 2-bit reference decoder 11
5 generates the selection signals 8ELQ to sgL3 to be exclusively active, so that the selection signals 8ELQ to sgL3 that are not selected are
8-bit zero data or all 1's are output to the outputs of three sets of bit data generating means 110-113 in response to an output selection signal ZERO.

Therefore, when the read signal IMD becomes active, 32
Bit-data buffer 114 stores 32-bit data.
The data output to path 101 is as shown below.

Og zzzzzzzz zzzzzz
zzzzQl zzzzzzzzzz
zzzzzzzzlozzzzzz nnnnnnn
nnn11 nnnnnnnnn
22222!22BYTO/1 bit
, (8,,15) bit(0,,7]00
zzzzzzzz nnn
nnnnnn01 nnnnnnnnn
Zzzzzzzzzlo zz
zzzzzzzzzzzzzzll
zzzzzzzzzz
zzzzzzzz and here buS, the expression [xo, y] indicates the range from bit X to bit y of the 32-bit data bus 101, and nnnnnnnnn indicates the contents of the lower 8 bits imd of the instruction field. ,z
zzzzzzzz is 11 if the output selection signal ZERO is 1
If it is 111111.0, it is ooooooooo.

FIG. 6 shows an example of the instruction format of the microinstruction applied to this embodiment.
When a constant is selected in the field, the most significant bit of the ID field has the meaning of specifying whether to set the 24-bit data, which is not a valid byte for the 32-bit ψ immediate, to O or IK. be.

In other words, if the ID field is OXX, all zeros.

If it is 1XX, all 1s are selected.

Next, the constant generation operation in this embodiment will be explained. Now 1010100 in microinstruction register 100
If the data 10101 100 10100110 is held as a micro-instruction, the micro-instruction decoder 102 will actuate the micro-order IMD and perform other micro-order OPRs since there is a pattern of 5rc101010.

Make BR and CNT inactive. Since the bits (J, 9] of the microinstruction register 100 are 00, the 2-bit decoder 115 makes only 5ELO active and 5ELI, 8EL2, and 5EL3 inactive. Therefore, the 8-bit data generation means 81
Among 0 to 813, only 810 generates the same value as func, that is, 10100110, and the other 8-bit data generators 6s1x, s1z, and s13 generate 11111111 because the output selection signal ZE_O is 1. The micro-order IMD allows the 32-bit data buffer 114 to connect to the 32-bit Q data bus 101K.
11 1111111111111111 10100
You can get 110.

This 32-bit data is ooooooo.

00000000 00000000 0111010
It is a two's complement number of 32-bit data.

In this example, the range of values that can be expressed is from 0 to 2'''32
-1. Furthermore, microprograms that require integer constants can easily represent negative numbers.

FIG. 8a is a diagram illustrating in more detail the 8-bit data generation means used in FIG.
D game) 1030 to 1037 and the above two-person AND
Game) 2-person OR game with outputs 1030 to 1037 as one input) 1040 to 1047, and 2-person AN
D game) 1038, inverter 1050, 2
The other inputs of the manual AND gates 1030 to 1037 are connected to the selection signal SEL, and the two manual OR gates 104
The other input from 0 to 1047 is a two-person AND game) 1
Output of 038 (two-person AND game that will be connected) 1
One input of 038 is connected to the output K of an inverter 1050 whose input is selection signal SEL, and one input of 038 is connected to output selection signal ZEROK. If the selection signal SEL is active (1), 2-person AND game) 1030 to 1037
The output of will be the same as the input INO~7. On the other hand, two-man power AN
Since the output of the D game) 1038 is O, the outputs of the two-man OR games 1040 to 1047 are the same as the outputs of the two-man AND gates 1030 to 1037. Therefore, the same data as the inputs INO-7 appears at the outputs 0UTQ-7.

Further, when the selection signal SEL is inactive (0) and the output selection signals ZER, O are O, the outputs of the two-man power AND game) 1030-1037 are all 0 regardless of the values of the inputs INQ-7. On the other hand, 2 people AND game) 10
4Em, since one input ZERO is 0, it is O, and the output of 1040 to 1047 is 2
It is the same as the output of human power AND game) 1030 to 1037. Therefore, all outputs 0UTO to 7 become O. Further, when the selection signal SEL is inactive (O) and the output selection signal ZER,0 is 0, the output of the two-man power AND gate 1048 becomes 1, and the two-man power OR gate 104
The output of 0 to 1047 is the two-man AND gate 1030 to
Regardless of the output of 1037, it will all be 1. Therefore, all outputs 0UTO to 7 become 1.

〔Effect of the invention〕

As explained above, by using the present invention, a constant having a large expression range can be obtained by executing a single microinstruction without increasing the bit width of the microinstruction. Furthermore, constants having arbitrary values can be obtained quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional microprogram control device. 4 is a format diagram showing the format of a conventional microinstruction, FIG. 5 is a circuit block diagram of constant generation using a conventional microprogram control device, and FIGS. FIG. 7 is a block diagram showing another embodiment of the present invention; FIGS. 8a and b are details of the 8-bit data generation means used in the embodiment of the present invention. It is a circuit block diagram showing. 100...23-bit microinstruction register, 101...32-bit data bus, 10
2...Micro instruction decoder, 110 to 113
...8-bit data generation means, 114...
...32 bits - data buffer, 115...
...2-bit decoder, 201... Control memory, 202... Microinstruction register, 203...
...Microinstruction decoder, 204...
Register file, 205...- Arithmetic logic unit, 206... Data bus, 401...
. . . Transfer field, 402 . . . Command field. 403...sp, c field, 404...
...DST field, 405...Identifier,
406...Function field, 501...
・Micro-address register, 502...
Control memory, 503 --- Microinstruction register,
504... Microinstruction f''-da, 505...
... Arithmetic control device, 506 ... Branch control device, 507 ... Control device, 510 ...
Source operand decoder, 511... Destination operand decoder, 512...
...Constant buffer, 520...Data bus, 521...Register board, 52
2...Other register Q sources, 523...
...source operand bus. 524...destination operand
Bus, 1000-1007...2-person AND gate, 1030-1038...2-person AND gate, 1040-1047...2-person OR game), 1050... ...Inverter. Patent attorney Uchihara 3. −． 1. No. 2nd Ward (4th Ward to the subordinate Iυ Ministry)

Claims (1)

[Claims] means for temporarily holding a microinstruction; means for detecting a bit pattern of a first field of said holding means;
and a plurality of data generation means for outputting predetermined data or the contents of the second field of the holding means, and according to the bit pattern detected by the detection means, one of the plurality of data generation means A microprogram control device characterized in that the content of the second field of the holding means is output to only one, and the outputs of the other plurality of data generating means are combined and used as constant data.