JPS63208942A - Microprogram memory circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a microprogram memory circuit by selecting a single microinstruction out of the data read out of a memory based on a control signal inputted separately to store it temporarily and producing specifically a control signal from the address information contained in said microinstruction. CONSTITUTION:The capacity of a single memory 1 is set at (mX2<n>) bits together with the address number set at 2<n-2> and the output width set at (mX2<a>) bits respectively (m>n>a). A single microinstruction is red out of the data read out of the memory 1 by a multiplexer 2 based on the signal of a branch deciding circuit 6 and stored temporarily in a microinstruction register 3. The n-bit address information contained in an output instruction is supplied to an address register 5. Then the lower rank (a) bit of the address information are inputted to the circuit 6 and this address information is qualified by a branch instruction when this instruction is given. While the address information is kept as it is when no branch instruction is given. Then a control signal of the multiplier 2 is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram memory circuit that sequentially reads stored microinstructions, and particularly relates to a microprogram memory circuit that performs conditional branching depending on the execution result of the microinstructions. .

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional example of this type of microprogram memory circuit.

The storage devices 208 to 2n1 are prepared as many as the number of conditional branches (four in this conventional example), respectively.

An m-bit microinstruction is stored at each address of 2n-2 ([1 (n is a positive integer of 3 or more).
This register stores microinstructions read from 8 to 2n1, and each microinstruction includes n bits of address information of the next microinstruction to be executed. One of the outputs of the microinstruction registers 201 to 204 is selected by the multiplexer 205, and the remaining m-n bits excluding the address information are output as they are as the microinstruction Ml, and the n-bit address information is sent to the path 2H. Address register 20 through? guided by. Among the outputs of the address register 207, the upper n-2
The bits are commonly given to the storage devices 208 to 2n1, and microinstructions at the same address are read out and stored in the instruction registers 201 to 204 at the same time.The 0 branch determination circuit 2n2 selects the remaining bits from the output of the address register 207. 2 bits and a branch signal JUMP based on the execution result of the microinstruction signal Ml that was output immediately before, the branch signal JUMP modifies, synchronizes, and decodes the 2 bits of regular address information, and the control is controlled by the output. The multiplexer 205 is controlled via the signal line 2n3, and one of the four microinstruction registers 201 to 204 to be executed next is selected and output.

[Problem that the invention seeks to solve]

The conventional microprogram memory circuit described above requires memory circuits and microinstruction registers whose number corresponds to the branch direction, and the outputs from each independent memory circuit must be collected and one of them selected by a multiplexer. This method has disadvantages in that it requires a significant increase in hardware and design complexity, such as the need for wiring to give the same address to each storage device.

[Means for solving problems]

The storage device of the microprogram memory circuit of the present invention includes:
The capacity is m x 2n bits, the number of addresses is 2n-a (m is the number of microinstruction bits, n and a are any positive integers, and m > n > a), and it has an output width of m x 2'' bits. The sequence control device includes a multiplexer that selects one microinstruction from m×2' bit width data read from the storage device according to a control signal input separately, and a multiplexer that temporarily stores the microinstruction selected by the multiplexer. an address register that inputs the n-bit address information included in the microinstruction output from the microinstruction register and accesses the storage device using the n-a bit address in the output; The address information of the remaining a bits is input, and when a branch instruction based on the execution result of the output microinstruction is input, the address information is modified by the branch instruction, and when there is no branch instruction, the address information is It has a branch determination circuit that generates the control signal from each address information.

[Effect]

Thus, with a simplified configuration using a single storage device and a single microinstruction register.

Just like the conventional circuit, microinstructions can be selected and sequentially output from a plurality of microinstructions read out from the storage device, depending on conditional branching when necessary.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the microprogram memory circuit of the present invention.

The storage device 1 is a single storage device that stores microinstructions, and its capacity is m x 2n bits and the number of addresses is 2 tons (1).
m is the number of bits of the BIC instruction, n and a are arbitrary positive integers, and m>n>a), and has an output width of m×2n bits. The multiplexer 2 selects one microinstruction from a set of m×2° bit width data read from the storage device 1 according to a control signal.

The microinstruction register 3 temporarily stores the microinstruction selected by the multiplexer 2 to be executed. The address register 5 inputs n bits of the microinstruction outputted from the microinstruction register 3 as address information of the microinstruction to be executed next via the path 4;
0 branch determination circuit 6 that outputs the upper n-n bits of address information as an address signal for accessing the storage device 1
receives the remaining n-bit address information from the address register 5, and if it executes the branch instruction JUM based on the execution result of the microinstruction MI output from the microinstruction register 3.
When P is given, the n-bit address information already input from the address register 5 is sent to the corresponding branch instruction JUM.
If there is no branch instruction JUlilP, the address information is left as is and the control signal for the multiplexer 2 is generated and output by decoding each of them. Note that the control signal line 7 connecting the branch determination circuit 6 and the multiplexer 2 is composed of 2a lines, and control signals corresponding to 2a microinstructions read out to the multiplexer 2 are transmitted via each line.

Next, the operation of this embodiment will be explained.

The microinstruction has an n-bit address field as address information for the next microinstruction to be executed. First, the address information is removed from the microinstruction register 3, and the data of m−n bits is stored in the microinstruction Ml. is output and the microprogram starts running. In parallel with this, n bits of address information in the address field are transmitted to the address register 5 via the path 4, and of the output of the address register 5, the lower n bits are transmitted to the branch decision circuit 6, and the remaining n- The n bits are given to the memory device l as an address for access and reading thereof is started. On the other hand, in the 1-branch determination circuit 6, if the microinstruction being executed at that time is a conditional branch instruction and the execution result requests a branch (for example, when the operation result overflows),
, a part or all of the n-bit address information that has already been given is modified by the branch signal JUMP that conveys this fact, and is further decoded to create a 2nL tree with multiplexer 2. Only one of the corresponding control signal lines 7 is activated. Therefore, this output is given as a control signal to the multiplexer 2 before and after the readout of the storage device 1 is completed, and one control signal is activated from among the 2n microinstructions read out. The fact that the n-bit address information input to the 0-branch determination circuit 6 where the microinstruction at the address corresponding to line 7 is selected and the conditional branch instruction completes in one cycle is not modified at all means that operations are performed in the normal order. This means that the microinstructions in the storage device I are arranged accordingly.

〔Effect of the invention〕

As explained above, the present invention uses a single storage device and a single microinstruction register, and enables the same operation as the conventional example with a smaller wiring configuration, thereby reducing the number of hardware. In addition, the degree of freedom in the physical arrangement and combination of microinstructions on multiple sides that are read simultaneously in the storage device that stores the microprograms can be significantly reduced, and the degree of freedom in the physical arrangement and combination of microinstructions on multiple sides in the storage device that stores the microprograms can be significantly reduced. In particular, the configuration of the multiplexer can be simplified by arranging corresponding bits of microinstructions that are read at the same time adjacent to each other, and the structure of the multiplexer can be simplified in conjunction with the microinstruction register. This has the effect of providing an integrated microprogram memory circuit that is easy to design with good regularity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the microprogram memory circuit of the present invention, and FIG. 2 is a block diagram showing a conventional example of the microprogram memory circuit. 1...Storage device, 2...Multiplexer, 3...Microinstruction register, 4...
Route, 5...Address register, 6...Branch judgment circuit, 7...Control signal line. JUMP...Branch signal, Ml...Micro instruction. Patent applicant: NEC Corporation Figure 1

Claims (1)

[Scope of Claim] A microprogram memory circuit comprising a storage device in which a microprogram is stored and a sequence control device that sequentially reads microinstructions from the storage device, the storage device having a capacity of m×2^. n bits, number of addresses is 2^n^-^a (m is the number of bits of microinstruction, n
and a is any positive integer, and m>n>a), m×
The sequence control device has an output width of 2^a bits, and the sequence control device selects one microinstruction from data of m x 2^a bit width read from the storage device according to a control signal input separately. A multiplexer, a microinstruction register that temporarily stores the microinstruction selected by the multiplexer, and n-bit address information included in the microinstruction output from the microinstruction register are input, and the n-a bit address in the output is input. When a branch instruction based on the execution result of the output microinstruction is input by inputting the address register for accessing the storage device and the address information of the remaining a bits from the address register, the address information is input by the branch instruction. A microprogram memory circuit comprising a branch determination circuit that modifies the address information and generates the control signal from each address information while leaving the address information as it is when there is no branch instruction.