JPS6395540A - Memory interface circuit - Google Patents

Abstract

PURPOSE:To shorten the processing time by using a memory interface circuit containing plural data processors, a memory and a token input part to perform the memory reading/writing actions. CONSTITUTION:In a memory interface circuit 10, the value of an address register 11 is used as an address to read a memory 20 based on the decoding result of the tokens supplied to a token input part 16 from data processors 21 and 22 in case an identifier showing a read token containing a read address is prepared together with a flag showing execution of the indirect addressing and a data part serving as the read address. While the set value of the register 11 is used as an address and the value of a data register 13 is written into the memory 20 in case an identifier showing a write token containing a write address is prepared together with a flag showing execution of the indirect addressing and a data part serving as the write address. In such a way, the processing speed is increased with a memory interface circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory interface circuit, and particularly to a memory interface circuit (2) that executes read/write operations from a data flow processor to a memory.

[Conventional technology]

Conventionally, there is μPD7281 manufactured by NEC Corporation as a data flow processor. μPD930 manufactured by NEC Corporation is used as a memory interface circuit in the arithmetic processing system using the data flow processor.
There are 5.

To explain the memory access operation of the μPD9305, this circuit transfers data and performs arithmetic processing using a data flow method, and the unit of input/output data is called a token. A token is a data unit composed of a data portion having a data value, an identifier indicating the meaning of this token, and a destination tag indicating the destination of the token. For example, in the case of memory reading, a read token that has a data part that is a read address, an identifier indicating that it is a read token with a read address, and a destination tag indicating that the destination is the memory interface circuit is input to the memory interface circuit. do. When a read token is input, the memory interface circuit outputs a read address of the token and a memory read signal to the memory, and instructs a read operation. The memory executes the read operation according to the above instruction, and when the read operation is completed, it issues an access end signal to the memory interface circuit, and the memory interface circuit generates and outputs a token containing the read data, and ends the memory read operation. In addition, in the case of memory writing, there is a data part which is the write data, a write data token which has an identifier indicating that the data token has write data and a destination tag whose destination is the memory interface circuit, and a write address. A data portion, an identifier indicating that the data token has a write address, and a write address token having a destination tag indicating that the memory interface circuit is the destination are input to the memory interface circuit in this order. When a data token is input, the memory interface circuit sets and holds the write data of the data section in the data register, and when the next write token is input, it sets the write data read from the data register and the data of the write token. Outputs the write address in the section and the memory write signal to the memory,
Instructs write operation. The memory executes the write operation according to the above instruction, and when the write operation is completed, it issues an access end signal to the memory interface circuit, and the memory interface circuit thereby ends the memory write operation.

[Problem that the invention seeks to solve]

In a device using the above-mentioned memory interface circuit, when performing so-called indirect addressing, in which a memory read or write operation is performed again using a value in memory at an address specified by a program as an address, this is done by a program on a data flow processor. It had to be realized in software. For example, when reading memory using an indirect address, the data flow processor sends a read token whose data value is an address indicating the location where the address value is stored in memory to the memory interface circuit, and this causes the read token to be read from memory. A procedure in which a value is sent from the memory interface circuit to the data flow processor, a read token with the address read in the previous operation is created in the data section in the data flow processor, and after sending it to the memory interface circuit, the memory read operation is performed again. will be used.

However, this method requires many parts to be processed by the data flow processor program.
This creates a software burden and requires processing time for the token to go around the ring connecting the data flow processors at least twice.

[Means for solving problems]

A memory interface circuit of the present invention is connected to a plurality of data flow processors connected in a ring shape and a memory, and includes: a token input section for inputting a token, which is a unit of data input from the data flow processor; a data register that holds write data input from the input section to the memory; a multiplexer that selects and outputs one of the data input from the memory and the token input section; and a data register that holds write data input from the multiplexer to the memory. an address register that holds read/write addresses; a token generation unit that uses the data read from the memory to generate a token to be output to the data flow processor; It is composed of a token output section that outputs to the data flow processor, and a memory access control that is connected to the memory, the multiplexer, the token generation section, and the token input section and controls memory read/write operations for these.

[Effect]

In the memory interface circuit of the present invention, depending on the decoding result of the token input from the data flow processor to the token input section, (a) when the circuit has a flag indicating that indirect addressing is not performed, it is different from the case in the conventional memory interface circuit. In addition to performing the same operation, (b) if it has an identifier indicating that it is a read token with a read address, a flag indicating that indirect addressing is to be performed, and a data portion that is the read address, the data Inputting the token from the flow processor is temporarily prohibited until the second read operation is completed, and the read address of the data section of the read token is set in the address register, and then the data read from the memory is stored in the address register using that address as the address. control to read the memory using the value of the address register as an address.
(C) Also, if this has an identifier indicating that it is a write token with a write address, an indirect address, a flag indicating that tsshing is to be performed, and a data part that is a write address, the token is input from the data flow processor. is temporarily prohibited until the next write operation is completed, and
Set the data in the data portion of the write token in the address register, then set the data read from the memory as an address in the address register, further set the value of the set address register as the address,
Control is performed to perform a write operation to the memory using the value of the data register as write data. In this way,
Indirect addressing can be achieved by just one access from the data flow processor to the memory interface circuit of the present invention.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing one embodiment of the present invention, a memory interface circuit 10 includes a multiplexer 23, a memory access controller 15, an address register 11, a data register 13, a token input section 16, a token generation section 17, and a token output section 18. The signal line 10
0.101 to data flow processors 21 and 22, which are connected to each other by a signal line 102, and to the memory 20 via signal lines 105-108. This memory interface circuit 10 performs data transfer and arithmetic processing using a data flow one-way system. FIG. 2 shows an example of the data format of a token, which is a unit of input/output data. The token is composed of a data portion 86 having a data value, a destination tag 80 indicating the destination of the token, and fields 81 to 84 having information such as an identifier indicating the meaning of the token.

Next, referring to FIG. 3 showing the detailed configuration of the memory access controller 15, the memory access controller 15 has an address/data flag register 51 which receives the signal 63 from the token input section 16 and latches it with the signal 121. , a read/write flag register 52 which receives the signal 64 from the token input section 16 and latches it with the signal 121; and the token input section 1.
an indirect flag register 53 that receives the signal 65 from the input section 16.6 and latches it using the signal 121; input signal 121 from memory 2.
Memory read/write operation selection signal 105 to 0, latch signal 117 to data register 13, latch signal 118 to address register 11, selection/command signal 110 to multiplexer 23, token generation command signal 115 to token generator 17 and) - a gate array 50 which outputs the busy signal 116 to the input section 16.

In FIG. 1, a token input from a data flow processor 21 to a memory interface circuit 10 is decoded by a token input section 16. The token input section 16 shows this memory interface circuit 10 in which the value of the field 80 of the destination tag of l.-kun input in synchronization with the clock 120 via the signal line 100 is set in the token input section 16 in advance. If it is not a value, this input token is output to the signal line 114 as a passing token. This passing token is directly output from the signal line 101 to the outside of the memory interface circuit 10 via the token output section 18. On the other hand, if the value of the field 80 of the destination tag of the input card is a value indicating this memory interface circuit 10, the token input section 16 inputs the address/data flag 81, read/write flag 82 of the token information.
, the information in each field of the indirect flag 83 is output to the signal lines 63, 64, and 65, the data section 86 is output to the signal line 113, and the read data token generation information field 84 is output to the signal line 103, indicating input of a token. Signal line 1
Further, when the busy signal 116 is "1", the token input unit 16 does not input a token from the data flow processor 21 during that period.

In the memory access controller 15, input signal 1
By changing 2 to 1, the information in each field of the address/data flag 81, read/write flag 82, and indirect flag 83 sent from the token input unit 16 via the signal lines 63, 64, and 65 becomes the address. - Latched in the data flag register 51, read/write flag register 52, and indirect flag register 53.The above token input section 16 and memory access controller 1
The operation No. 5 is called the token input waiting operation. Gate array 5
0, as shown in FIG.
20 is supplied, and after the above token input/output operation,
While the signal 121 is "1", the registers 51, 5
According to the outputs 60, 61, and 62 of 2.53, input/output operations are performed according to the input/output correspondence table shown in FIG. In Figure 5,
121.60, 61, 62, 119, 120 on the left are input signals to the memory access controller 15, 116
indicates the state of the output signal, and 105.117,1 on the right
18, 110, 115, and 116 indicate outputs when these input states are given. Further, each row indicated by 40 is used when there is no input to the memory access controller 15, each row indicated by 41 is used for the first half of a read and write operation by indirect addressing, and each row indicated by 42 is used for a read operation by indirect addressing. In the second half of the case, each line marked 43 is for a write operation with indirect addressing, each line marked 44 is for a read operation with normal addressing, and each line marked 45 is for a write operation with normal indirect addressing. In the case of an operation, each row indicated by 46 corresponds to a data set operation.

Details of a memory access operation performed using a token whose destination indicated by a destination tag is a memory interface circuit will be described below.

First, a read operation for the memory 20 will be explained. When performing a memory read operation, the data flow processor 21
The data section which is the read address and the memory interface circuit 1 are sent to the memory interface circuit 10 from
A read token with a destination tag of 0 and an indirect flag 83 is input. In the read)-kun, the address/data flag 81 is 1°'' and the read/write flag 82 is 1°'', indicating that it is a read token with a read address.Here, first, the indirect flag 83 is but,
The case where it is "0" will be explained. Token input section 1
When such a lead token is entered for 6,
Token input section 16, memory access controller 15
The above token input waiting operation is performed, and register 5 is
Output signals 60 and 61.62 of 1°52.53 are determined. Since the signal line 60 is "1", the gate array 50 selects the input from the signal line 113 and outputs a selection instruction signal to the multiplexer 23 via the signal line 110 to output it to the signal line 112. Signal line 118
outputs a latch signal via the signal line 112.
The data value of the upper input address is latched into the address register 11. Further, when the read/write flag 82 of the input token output on the signal line 61 is "1", the signal 105 becomes "0", and the memory 20 reads out the output signal 106 from the address register 11 as an address. The data read from the memory 20 is output to the signal line 108. Here, since the input indirect flag 83 is "0", the indirect flag register 5
The output signal 62 of No. 3 becomes "0", and the gate array 50 instructs the token generation section 17 via the signal line 115 to generate a token from the read data, and the token generation section 17 follows this and generates a token from the read data. 10
8 and the destination tag and identifier that the read data token should have included in the read data token generation information 103 to form an output token. It is output to the flow processor 22.

The above read operation is completed within one pipeline clock of the pipeline clock 119, and the token input section 16 changes the signal 121 to 0 in synchronization with the pipeline clock 119.
'', the memory interface circuit 10 completes the memory read operation.On the other hand, when the indirect flag is "°1" when the read token is input, the output signal 62 of the indirect flag register 53 becomes "1".

In this case, the memory interface circuit 10 performs a read operation by indirect addressing as follows, based on the addresses held by the reads 1 and 2. After a token input operation, if signal 62 is ``1'', busy signal 116 becomes 1'', which causes the
Input to the token input section is stopped, and successive output operations by indirect addressing are performed using a 2-vib line clock. After performing the first memory read at the first pipeline clock in the same manner as above, the gate array 50 receives the token generation command signal 1 because the signal 62 is 1''.
15 and multiplexer 23 by signal 110.
It selects the input signal 108 and instructs it to be output to the signal line 112, and outputs the latch signal 118. Further, the data read from the memory 20 by the first memory read is latched in the address register 11 as the second read address of indirect addressing, and the memory read operation is performed in the same way as the first pipeline clock.
Data read from memory 20 is output to signal line 108. Thereafter, the signal line 115 becomes 1'', and the token generation unit 17 accordingly generates the read data sent from the signal line 108 and the read data token included in the read data token generation information field 84 sent from the signal line 103. A destination tag and an identifier are combined to generate an output token, and this output token is output to the data flow processor 22 via the signal line 104, the token output section 18, and the signal line 101, and the memory interface circuit 10 performs memory readout using indirect addressing. Finish the operation.

Next, a write operation to the memory 20 will be explained. When performing a memory write operation, first, a data token having a destination tag whose destination is the data section, which is write data, and the memory interface circuit 10 is input from the data flow processor 21 to the memory interface circuit 10 . In the data token, its address/data flag 81 is ``
A value of “0” indicates that the token is a data token having write data. When a token is input, the above-mentioned token entry operation is performed, and the write data of the data section 86 of the input token is output to the signal line 113, the address/data flag 81 is output to the signal 63, and the gate array 50 is latched. Since the output signal 60 of the address/data flag register 51 latched by the signal 121 is "0" indicating a data token, the latch signal 117 is output, and the memory interface circuit 1
0 completes the data setting operation within one pipeline cycle. Next, the data flow processor 21 sends a write token to the memory interface circuit 10 that has a data section that is a write address, a destination tag with the memory interface circuit 10 as the destination, and also has an indirect flag. Enter. In the write token, the address/data flag 81 is 1”, and the read/write flag 8
2 being "O" indicates that it is a write token with a write address. When a write token is input, the above-described token entry operation is performed, and in the case of a data write operation in which indirect addressing is not performed in the gate array 50, signals 60, 61, and 62 are set to "1 pass" and "0", respectively. , "°0'°, the signal 105 is set to "1" for the memory 20, and the signal 106 output from the address register 11 is thereby set as the write address, and the previously set data register 1 is set.
Instructs a write operation using the signal 107 output from 3 as write data. The memory 20 executes the write operation in accordance with this, thereby completing the memory write operation within one pipeline cycle. On the other hand, when the signal 62 indicating the presence or absence of indirect addressing inputted to the gate array 50 is "1", the memory interface circuit 10 performs two pipelines according to the address of the write token as follows. A write operation using indirect addressing takes cycles. First, as in the first pipeline cycle when a memory read token whose indirect flag is '0' is input, the busy signal 116
is set to "'1°", and the data portion of the input address register 11 is latched and the memory read is performed using the signal line 105, and the data read from the memory 20 by the first memory read is transferred to the indirect addressing. The second read address is latched into the address register 11.Subsequently, the gate array 50 sets the signal 105 to "'1'', thereby setting the signal 106 output from the address register 11 as the write address, and latches it into the address register 11. The memory 2 performs a write operation using the signal 107 output from the data register 13 set as write data.
0, and memory 20 performs a write operation. With the above operation, the memory write operation is completed within two pipeline cycles.

〔Effect of the invention〕

As explained above, according to the present invention, indirect addressing is enabled by a single access from a data flow processor to a memory interface circuit, and compared to the conventional case where this is achieved using a data flow processor program, This reduces the burden on software and delays in processing due to twice accessing the memory interface circuit from the data flow processor during processing execution, and speeds up processing.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the data format of input I-Kun, and FIG.
This figure is a more detailed configuration diagram of the memory access controller in FIG. 1, and FIGS. 4 and 5 are diagrams for explaining the operation of the memory access controller. 10...Memory interface circuit, 11...Address register, 13...Data register, 15...
Memory access controller, 16... heat input unit, 17... token generation unit, 18... token output unit, 20... memory, 21.22... data flow processor, 23... Multiplexer, 50...
Gate array, 51...Address/data flag register, 52...Read/write flag register, 53
...Indirect flag register, 60-65.100-10
8.110-121...Signal line. 2nd side\p+ side S

Claims (1)

[Scope of Claims] A token input unit connected to a plurality of data flow processors connected in a ring shape and a memory, and inputting a token that is a unit of data input from the data flow processor; and the token input unit. a data register that holds write data input from the memory unit, a multiplexer that selects and outputs one of the data input from the memory and the token input unit, and a data register that holds write data input from the multiplexer to the memory; - an address register that holds a write address; a token generation unit that uses data read from the memory to generate a token to be output to the data flow processor; and a token generation unit that uses the data read from the memory to generate a token to be output to the data flow processor; a token output section that outputs to the processor; and a memory access control that is connected to the memory, the multiplexer, the token generation section, and the token input section and controls memory read/write operations for these. Features a memory interface circuit.