JPH0362183A - Semiconductor integrated circuit and data processing system using the same - Google Patents

Abstract

PURPOSE:To obtain a semiconductor IC which need not execute an instruction at its internal part and can access an external part and in addition, can execute another program at the time of the access by connecting one port, at least, among plural ports directly to the external part. CONSTITUTION:A two-port RAM 2 is provided with an address port AP0, a data port P0 and further, a write port W0 which are accessed from the external part, and these ports are constituted so that they are connected to an exclusive address input terminal 11, an exclusive data input/output terminal 10 and a write signal input terminal 12 through latches 64, 61, 63 respectively. In this configuration, when the RAM 2 is accessed from the external part, the data of an address is inputted to the port AP0 connected to the external part, and the data is inputted or outputted directly from the external part to the RAM or from the RAM to the external part through the port P0, and the write signal for the buffer control of the latch 61 is given to the port W0. Thus, since during the period, it need not execute any instruction, it can execute the processing of another program.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit such as a digital signal processor having a built-in memory having a plurality of ports, and a data processing system using the same, and particularly to a data processing system using the same. The present invention relates to a semiconductor integrated circuit that allows direct access to memory from a circuit.

[Conventional technology]

Figure 8 is a block diagram showing the configuration of the main parts of a signal processing processor, which is a conventional semiconductor integrated circuit with a built-in RAM (2 baud).
SY87-56) r24-bit floating point signal processor/ll5P2J. In the figure, 1 is a signal processing processor (DigitalS
signal processor (hereinafter referred to as DSP)
The DSP 1 inputs and outputs data to and from other ASPs via the general-purpose data input/output terminal 14. In the DSP 1, a fetched instruction is decoded by an instruction decoder (not shown), and an address generator 3 generates address data of an operand used for the decoding. The generated address data is stored in the address register 31 or 32. Further, external address data stored in the data register 7 can also be applied to the address register 31 or 32 via the general-purpose data input/output terminal 14 via the internal data bus 5.

The address data in the address registers 31 and 32 are output to address ports APO and AP of the 2-baud RAM 2, respectively. (2 baud) RAM 2 can be accessed individually according to address data input to the respective address ports APo and APt. Also 2-bot RAM
2 is designed to input and output data separately at data ports Po and P+, and data is input from the internal data bus 5 to data ports P, , P, and data port 1
'From Po and Pt, the internal data bus 5 and selector 23
．． Data is output to one end of 24. Selector 23.2
Data from the internal data bus 5 is given to the other end of 4, and one of the two input data is selected and output to the arithmetic unit 4, where the data is processed according to the fetched instruction. An operation is performed. The calculation result in the calculation section 4 is given to the internal data bus 5.

In the conventional DSP configured as described above, the operation when the built-in 2-point RAM 2 is accessed from the external DSP 101 via the external data bus will be described. Figure 9 shows the 2-bot RAM of DSP 1.
2 is a block diagram illustrating a conventional data processing system in which data processing apparatus 2 is accessed from an external DSP 101.

In this data processing system, first, the DSP 101 is a DS
The address to be accessed is generated from the 2-baud RAM 2 built in the Pl, and is output from the general-purpose data output terminal 14 of the DSP 101 to the external data bus 15 as address data.

Next, the DSP 1 takes in the address data on the external data bus 15 from the general-purpose data output terminal 14 into the data register 7, and transfers it to the address register 31 (or 32) via the internal data bus 5. address register 3
The address data stored in 1 (or 32) is transferred to one address port AP6 (or 32) of 2-point RAM 2.
The two-point RAM 2 is accessed separately according to the address data input to the respective address boards (APo and APt).

At the time of reading, data is output to each data port Pa, P+, so the data of the corresponding data port P, , P is sent to the data register via the internal data bus 5, and the external data is output from the general-purpose data input/output terminal 14. Output to bus 15. When the DSP 101 takes in the output data from the general-purpose data output terminal 14, it receives two inputs from the outside.
Reading of AM 2 is completed.

In addition, in the case of data writing, the address data is similarly transferred to the address register 31 (or 32), and then the write data is transferred to the data register 7 through the same route as the address data.
2 baud) and sent to the RAM 2 via the internal data bus 5 and data port Pa (or PI) for a write operation.

In addition, in order to execute the above-mentioned processing such as transfer of address data to the address register, access using the address data of 2-bottom RAM 2, transfer of read data, and capture of write data, transfer, access, etc. It is necessary to execute multiple instructions.

[Problem to be solved by the invention]

In conventional DSPs, when an external DSP accesses an arbitrary address in a 2-bottom RAM, it is necessary to execute multiple instructions in order to perform the access processing in the accessed DSP, as described above. There is a problem in that it takes a long time to complete the process, and other programs cannot be executed on the accessed DSP during the access period.

This invention was made to solve the above-mentioned problems, and by directly connecting at least one port out of a plurality of ports to the outside, a storage device can be connected to a semiconductor integrated circuit on the side to be accessed. A semiconductor integrated circuit and a data processing system using the same, which can access any address from the outside without the need to execute instructions, shorten access time, and execute other programs when accessed from the outside. aim to provide.

[Means to solve the problem]

A semiconductor integrated circuit according to the present invention is characterized in that at least one port among the plurality of ports is connected to the outside directly or via a selector, and a data processing system according to another invention is characterized in that at least one port among the plurality of ports is connected to the outside directly or via a selector. The semiconductor integrated circuit according to claim 1 is used as the semiconductor integrated circuit on the accessed side of the circuit.

[Effect]

In the semiconductor integrated circuit of the present invention, when the storage device is accessed from the outside, data at the accessed address is input to the address port connected to the outside, and data from the outside to the storage device or from the storage device to the outside is input to the data port. Data is input and output directly. At this time, the semiconductor integrated circuit does not need to execute any instructions, so it can process other programs.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings showing one embodiment thereof. FIG. 1 is a block diagram showing the configuration of a DSP which is a semiconductor integrated circuit according to the present invention. In the figure, l is a DSP, and DSP 1 has a built-in RAM 2 (2 baud) with a capacity of 512 words.

The RAM 2 has a port 0 consisting of an address port AP+ and a data port P which are accessed from the outside, and a port 1 consisting of an address port AP+ and a data port PI which are accessed internally. Address data latched at the timing of the timing signal ΦB is input from the dedicated address input terminal to the address port APo via the latch 64, and the data port Po is input to the address data via the human output buffer and latch 61 and the dedicated data input/output terminal 10. Output the data manually. In addition, the write signal -3 is latched from the write signal input terminal 12 via the latch 63 at the timing of the timing signal ΦB.
0 is given. The write signal -80 is also applied to the human output buffer and latch 61, and controls the human output buffer and latch 61 so that it functions as an output buffer 1 during reading and as an input buffer during writing.

On the other hand, the address port ^P, which is accessed by the command of the DSP 1 of the 2-boat RAM 2, has an address generator 3.
The address data of the operand generated in accordance with the fetched instruction is given, and 2 ports 1-RA2 are accessed. Further, the data port PI inputs and outputs data to and from the internal data bus 5. The internal data bus 5 is connected to the general-purpose data input/output terminal 14 via the data register 7, and performs data input/output with the external data bus 15 (see FIG. 6), and also performs various calculations. It inputs and outputs data to and from the arithmetic unit 4 that performs.

Further, the instruction fetched by the DSP 1 is stored in an instruction register 8, which is applied to a decoder & control circuit 9, and a control signal as a result of decoding is output to each element at the timing of a timing signal ΦB. For example, a write signal -31 (2 baud) is applied to the write port Wl of the RAM 2, data is read and written according to the timing signal ΦA, and a control signal for calculation is applied to the calculation unit 4. Various calculations are performed on the data input to the calculation unit 4 at the timing of the timing signals ΦA and ΦB.

Note that the timing signals ΦA and ΦB are signals whose phases differ by half a period, and are generated by the timing generation circuit 17.

Next, the access operation of the DSP 1 of the present invention configured as described above will be explained. FIG. 2 is a timing chart explaining the access operation of the DSP. FIG. 2(a) is reading from osp i, FIG. 2(b) is writing, FIG. 2(C) is reading from outside, FIG. 2(d) shows the external writing operation.

The access operation by the DSP 1 will be explained.

The DSP 1 performs three-stage pipeline processing of fetching, decoding, and executing instructions at the cycle of the timing signal ΦA. Address data to be accessed at the rising edge of the timing signal ΦB during decoding is generated by the address generator 3 and applied to the address port AP+ of the two-vote RAM 2.

The 2-bot RAM 2 follows the write signal WS+ from the decoder & control circuit 9 input to its write port W+.
When it is “L”, read operation is performed (Figure 2 (a))
, when the signal is "H", the write operation is performed from the rising edge of the timing signal ΦA (FIG. 2(b)). Write data is applied from internal data bus 5, and read data is output to arithmetic unit 4.

Note that these processes are controlled by control signals generated by decoding the commands in the command register 8 by the decoder & control circuit 9.

On the other hand, access at address port ^P0 is DS
Not under the control of the command processed by P1, external terminals, namely dedicated data output terminal 10, dedicated address input terminal 1
1 and a write signal input terminal 12, it can be accessed directly from the outside. 2 baud from outside) RAM 2
When accessing, the address data generated by the external DSPlol (see FIG. 6) and input to the dedicated address input terminal 11 is output by the latch 64 to the timing signal ΦB.
It is latched on the rising edge of and applied to address port APo. In this case, the external write signal -80 is “
At the time of "L" (FIG. 2(C)), that is, at the time of reading, this is latched by the latch 63 at the rising edge of the timing signal ΦB, and is applied to the write port W0.
The output buffer and latch 61 is supplied to control it to function as an output buffer. Then, the access starts from the rising edge of the timing signal Φ^, and after the access is completed, the read data is output from the data port P0, and is outputted to the dedicated data output terminal 10 via the output buffer & latch 61.

On the other hand, when the write signal -30 is "H" (Fig. 2 (d)
) Similarly, address data and write signal -30 are latched and applied to address port AP6 and write port ()We input/output buffer latches 61, respectively. Further, write data from the DSP 101 is applied to the dedicated data input/output terminal 10, and is latched by the human output buffer & latch 61 at the rising edge of the timing signal ΦB. Then, it is applied to data port P0 and written to the accessed address of 2-point RAM 2.

In this way, access by the external DSP 101 is
Since control by Pl instructions is not required, accesses by the DSP 1 and accesses by the DSP 101 can be processed in parallel.

Next, other embodiments will be described. In the embodiment described above, address port APo, write port W0, and data port P0 were exclusively accessed from outside, but in this embodiment, they can be accessed from either side. FIG. 3 is a block diagram showing the configuration of a DSP according to another embodiment. Note that explanations of parts common to FIG. 1 will be omitted.

Address port AP6, write port W, and data port P0 are provided with respective signals via selectors 65, 66, and 67.
6. A boat 0 unused signal US indicating that boat O is not used is sent from the decoder & control circuit 9 to the switching terminal 67.
is given, so that each selector 65°66, 67
Switch.

One end of the selector 65 is given address data from the latch 64, and the other end is given address data from the address generator 3. Also, one end of the selector 66 receives the same write signal from the latch 63.

is applied, and the write signal -510 from the decoder & control circuit 9 is applied to the other end. Further, one end of the selector 67 performs input/output with the human output buffer & latch 61, and the other end performs input/output with the internal data bus 5b.

The internal data bus 5a is the data port P of the 2-point RAM.
The internal data bus 5b inputs and outputs data to and from the I% calculation unit 4 and the data register 7, and the internal data bus 5b inputs and outputs data from the calculation unit 4 and the data register 7 in addition to the selector 67.

Next, the access operation of this embodiment will be explained. Fourth
The figure is a timing chart explaining the read operation.
A description of the write operation will be omitted. The decoder & control circuit 9 identifies whether or not to use port 0 when decoding an instruction, and outputs the “H” port O unused signal US0 from the decoder & control circuit 9.
”, “L” causes each selector 65, 66, 67 to be set to DS.
Select data from P 101 or DSP 1. That is, boat O unused signal US.

When is "H", each selector 65, 66, 67 selects data from the outside, and RAM 2 (2-port) is accessed by address data B from the outside.

Further, when the port O unused signal Use is "L", each selector 65, 66, 67 selects the data from the DSP I, and the address data A generated by the address generator 3,
The 2-bot RAM is accessed according to the data on the data bus 5b and the write signal WIO.

Next, still another embodiment will be described. FIG. 5 is a block diagram showing the configuration of a DSP according to still another embodiment. In this embodiment, all boats are provided with a selector, and internal and external can be selected for all boats. That is, address data is given to address port AP+ via selector 68, and write port W1 is given address data via selector 70.
A write signal is applied via the data port P, and the data port P outputs data to the selector 69. Also selector 6
5.66.67 has the port 0 external access permission signal AS from the decoder & control circuit 9, and the selector 68,
Similarly, at 69.70, the boat 1 external access permission signal A
S+ is given to each. In the second embodiment described above, the externally accessible boat is fixed to the boat O, but in this embodiment, the decoder & control circuit 9 detects the one of the two boats that is not being used by the DSP 1 during decoding. From there, each selector 65-67 (or 68-70
> To boat O (or boat 1) external access permission signal A
So (or AS+) is output, and when this is "H", each selector 65 to 70 selects external data, and when it is "L", selects internal data.

This further improves the utilization efficiency of RAM 2 (2 baud).

In the above embodiment, a DSP with a built-in 2-bot RAM is used.
However, the present invention is not limited to this, and can be applied to multi-board RAMs and R□Ms, and it goes without saying that the semiconductor integrated circuit is not limited to DSPs.

Next, a data processing system according to a second invention will be explained. FIG. 6 is a block diagram showing the configuration of the data processing system of the second invention, in which the DSP 1 of the invention and the conventional DSP 101 communicate data via an external data bus 15 and general-purpose data input/output terminals 14 and 14. Human output is being performed. Further, from the external data bus 15, different data is given to the dedicated data output terminal 10, the dedicated address terminal 11, and the write signal input terminal of the DSP 1.

In this data processing system, the operation when the DSP 101 accesses the two-bottom RAM 2 (see FIG. 1) built into the DSP 1 will be described.

DSP 101 generates the address to be accessed and provides it from general purpose data output terminal 14 via external data bus 15 to dedicated address input terminal 11 of DSP 1 .

The DSP 1 reads the 2-point RAM 2 according to the address data of the dedicated address input terminal 11 without using internal instructions.
access the corresponding address. For writing,
After the address data is latched by DSP 1, the data to be written and the write signal -80="H" are 1) S
Output from the general-purpose data output terminal 14 of P101,
The signal is input to the dedicated data output terminal 10 and write signal input terminal 12 of the DSP 1 via the external data bus 15. This input data remains as it is in the internal 2-vote R.
Written on AM 2. When reading, the write signal WSo ``'``L'' is output from DSPLol, the internal 2-baud RAM 2 is accessed according to the read address, and the read data is transferred from the dedicated data input/output terminal IO to the external data bus 15. Output.

Data on the external data bus 15 is taken into the DSP 101 from the general-purpose data input/output terminal 14 of the DSP 101.

Next, other embodiments will be described. FIG. 7 is a block diagram showing the configuration of a data processing system according to another embodiment,
In this embodiment, the general-purpose data input/output terminal 14 of the DSP 101 is directly connected to the dedicated data input/output terminal 10 and the dedicated address input terminal 11 of the SP 1 without going through the external data bus 15.
, are connected to the write signal input terminal 12. Therefore D
Since the external data bus is not used when accessing from SP 101 to DSP 1, at that time, external data bus 15
Other processing using can be performed in parallel.

〔Effect of the invention〕

As described above, according to the present invention, an arbitrary address of a storage device having a plurality of ports built into a semiconductor integrated circuit can be set to an address from an external terminal without being controlled by program commands inside the semiconductor integrated circuit. And you can directly access the data according to ↓. Therefore, when the semiconductor integrated circuit of the present invention is used in a data processing system composed of a plurality of semiconductor integrated circuits, the access time is shortened by not executing instructions, and other programs can be executed internally when accessed from the outside. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a DSP which is a semiconductor integrated circuit according to the present invention, FIG. 2 is a timing chart showing an access operation, and FIG. 3 is a block diagram showing the configuration of a DSP according to another embodiment. 4 is a timing chart showing the access operation of another embodiment, FIG. 5 is a block diagram showing the configuration of the DSP of still another embodiment, and FIG. 6 is a diagram showing the configuration of the data processing system according to the second invention. Block diagram, FIG. 7 is a block diagram showing the configuration of a data processing system according to another embodiment of the second invention, FIG. 8 is a block diagram showing the configuration of a conventional semiconductor integrated circuit, and FIG. 9 is a block diagram showing the configuration of a conventional semiconductor integrated circuit. FIG. 1 is a block diagram of a processing system. 1...DSP 2...2 point RIM 3...
・Address generation section 10... Dedicated data input/output terminal
11... Dedicated address input terminal 12... Write signal input terminal In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A semiconductor integrated circuit including a memory device having an address port for inputting an address signal and a data port for inputting/outputting a data signal, comprising a terminal for inputting/outputting each of the above-mentioned signals to/from the outside, and at least one of the above-mentioned signals. A semiconductor characterized in that an address port and a data port are connected to the terminals directly or via a selector that switches between each signal from the inside and each signal from the outside, and is configured to be accessed directly from the outside. integrated circuit. (2) having a plurality of semiconductor integrated circuits interconnected via a bus, the memory device built in the semiconductor integrated circuit according to claim 1 is accessed from another semiconductor integrated circuit via the terminal; A data processing system characterized by: