JPH05100901A - Microcomputer - Google Patents

Abstract

PURPOSE:To execute the executing state confirmation of a branch instruction in a microcomputer in a real time without changing an execution object program. CONSTITUTION:From a memory write control circuit 14 to which a branch instruction executing signal 24 generated from an EXU(executing unit) 11 at the time of executing a branch instruction, and a branch instruction condition forming signal 25 generated at the time when a condition of the branch instruction is formed are inputted, a condition formation signal 26 and a condition non--formation signal 27 are outputted. A signal of its branch instruction executing state is held in a condition formation storage memory 15 and a condition non-formation storage memory 16. and also, an execution object program is executed in a real time, and thereafter, in an execution range of the branch instruction by a superviser CPU 2. by an executing state read-out control circuit 17, the signal of the branch instruction executing state stored in the condition formation storage memory 15 and the condition non-formation storage memory 16 is read out, and outputted from a data interface control circuit 101, by which the branch instruction executing state is confirmed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a function for confirming a branch instruction execution state of a microcomputer including a semiconductor integrated circuit, which is used in a microcomputer development support device.

[0002]

2. Description of the Related Art A conventional microcomputer of this type is placed in a development support device and has a first control terminal 4 and a second control terminal 5 as shown in FIG. Microcomputer 7 formed on the semiconductor chip, external supervisor CPU 2, emulation memory 3 for storing the execution target program
It is composed of.

Next, the operation of confirming the execution state of a branch instruction using a conventional microcomputer will be described.

The function for confirming the execution state of a branch instruction has additional processing A, additional processing B, and additional processing C as shown in FIG. 4 for all branch instructions before executing the program to be executed as shown in FIG. Also, the supervisor CPU 2 adds the program processing for confirming the branch instruction execution of the additional processing D. That is, the areas for the branch instruction execution confirmation programs A, B, C and D are secured in the emulation memory shown in FIG. Further, in each additional processing, the additional memory areas A, B, C and D are similarly secured in the emulation memory, and then the execution target program of FIG. 4 is executed in the microcomputer 7. At that time, if the additional processing A is executed, the condition-satisfied signal of the branch A is written in the additional memory area A, and if the additional processing B is executed, the condition-unsatisfied signal of the branch A is written in the additional memory area B. Also additional processing C
Is executed, the condition non-fulfillment signal of the branch B is written in the additional memory region C, and the additional process D is executed, the condition fulfillment signal of the branch B is written in the additional memory region D.

With the supervisor CPU 2 shown in FIG.
The values of the additional memory areas A, B, C and D are read from the external bus 41 connected to the second input / output terminal 5 by using the emulation memory control signal 20, and the additional memory area A is signaled to satisfy the condition of branch A. Is written and the value of the additional memory area B is not a value indicating that the condition of the branch A is not satisfied, the branch instruction A is executed and the branch condition is satisfied. Therefore, it can be confirmed that the branch that does not satisfy the condition is not executed. If the value of the additional memory area A is not a value indicating that the condition of the branch A is satisfied and the value of the additional memory area B is a value indicating that the condition of the branch A is not satisfied, the condition not satisfied branch is executed. It can be confirmed that the taken branch is not executed. If the value of the additional area A is a value indicating that the condition of the branch A is satisfied and the value of the additional memory area B is a value indicating that the condition of the branch A is not satisfied, it can be confirmed that both conditional branches have been executed. Similarly for the branch B, the execution state of the branch instruction can be confirmed by referring to the values of the additional memory areas C and D by the additional programs C and D.

As described above, the function of checking the execution state of the branch instruction is realized by rewriting the program to be executed by the supervisor CPU 2 and then writing the branch instruction execution result in the emulation memory 3.

[0007]

In order for the above-mentioned conventional microcomputer 7 to realize the function of confirming the execution state of a branch instruction, an external supervisor CPU 2 adds a specific program to the program to be executed. Therefore, it takes a long time to execute an additional program other than the program to be executed, and real-time execution becomes impossible.

It is an object of the present invention to provide a microcomputer capable of performing real-time emulation by executing a program to be emulated by eliminating the drawbacks of the prior art.

[0009]

A microcomputer of the present invention includes means for generating a branch instruction execution signal regardless of whether a branch instruction is executed when executing a branch instruction, and branching when a condition of the branch instruction is satisfied. Means for generating an instruction condition satisfaction signal and, when the branch instruction condition satisfaction signal is generated, generate a condition satisfaction signal and a write signal, and write the condition satisfaction storage memory, and the branch command condition satisfaction signal is not generated. And a means for generating a condition unsatisfied signal and a write signal and writing the condition unsatisfied storage memory in the condition unsatisfied storage memory, and a means for reading a branch instruction execution state signal from the condition satisfied storage memory and the condition not satisfied storage memory. There is. It is possible to have means for externally inputting a read control signal of the signal reading means in the branch instruction execution state.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the microcomputer of the present invention. The microcomputer 1 formed on one semiconductor chip of the present embodiment has a first input / output terminal 4 and a second input / output terminal 4 arranged around this chip.
Input / output terminal 5, control terminal 6, BCU (bus control unit) 10, data interface control circuit 101, bus control circuit 102, PFU (prefetch unit) 12, IDU (instruction decode unit)
13, EXU (execution unit) 11, sequencer 111,
ALU (arithmetic logic unit) 112, REG (register) 113, memory write control circuit 14, condition satisfied storage memory 15, condition not satisfied storage memory 16, execution state read control circuit 17, emulation memory control signal 20, execution state Read control signal 21, first execution control signal 22, second execution control signal 23, branch instruction execution signal 24, branch instruction condition satisfied signal 25, condition satisfied signal 26, condition not satisfied signal 27, condition satisfied storage memory control The signal 28, the memory control signal 29 for storing unsatisfied conditions, the bus control signal 30, the internal data buses 40 to 47, and the external data buses 40 to 41. The microcomputer 1 constitutes a microcomputer development support device together with an external supervisor CPU 2 and an emulation memory 3.

Next, the operation of this embodiment will be described.

In FIG. 1, the microcomputer 1 in the microcomputer development support device is a BCU.
Address data is output from the bus control circuit 102 in 10 to the external bus 41 through the second input / output terminal 5, and data interface control is performed from the external emulation memory 3 through the external bus 15 and the first input / output terminal 4. Data is read into the circuit 101. During this operation, the data read during the instruction code read cycle is sent to the PFU1 via the data interface control circuit 101.
2, the IDU 13 and the EXU 11 are sequentially transferred. EX
In U11, the sequencer 111 generates the control signals 22 and 23 necessary for assembling and executing the instruction execution order. The data in the temporary storage device of the REG 113 is sent to the ALU 112 via the data bus 45. ALU112
Then, a logical operation is performed and a series of instructions is executed. When the instruction resulting from the execution is a branch instruction, the branch instruction execution signal 24
Occurs. Further, when the branch is executed because the condition is satisfied for the instruction, a branch command condition satisfied signal 25 is generated and input to the memory write control circuit 14. When the branch instruction execution signal 24 and the branch instruction condition satisfaction signal 25 are both input, the memory write control circuit 14 receives the condition satisfaction signal 26.
To occur. When the branch instruction condition satisfied signal 25 is input and the branch instruction condition satisfied signal 25 is not input, the condition not satisfied signal 27 is generated.

In either of the above states, the address data to be written is held on the internal data bus 46. When the condition-satisfying signal 26 is generated, the data for confirming the condition-satisfying state is written from the condition-satisfying storage memory 15 to the memory at the address held in the internal data bus 46. In addition, the condition not satisfied signal 27
When the error occurs, the data for confirming the condition is written from the memory 16 for storing the condition not satisfied to the memory of the address held in the internal data bus 46. These operations are executed by the external supervisor CPU 2 in the necessary address range. After the execution is completed, the execution state read of the branch instruction by the supervisor CPU 2 is executed as follows.

In the address range set by the execution state read control signal 21 input to the control terminal 6 and the signal of the external data bus 41, the memory control signal 28 for storing the condition of the execution state read control circuit 17 and the condition are stored. By the unsatisfied storage memory control signal 29, the signal of the branch instruction execution state stored in the condition-satisfied storage memory 15 and the unsatisfied storage memory 16 is read, and the data interface control circuit is passed via the internal data bus 47. By outputting from 101, the function of confirming the execution state of the branch instruction can be realized.

[0016]

As described above, since the microcomputer of the present invention has the function of storing the execution state of the branch instruction inside, the conventional microcomputer has the function of confirming the execution state of the branch instruction. As a method of implementation, a specific program was added to the execution target program by an external supervisor CPU, but it took time to execute the additional program other than the execution target program, and real-time execution was impossible. This has the effect of solving the drawback and enabling the execution of real-time simulation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer of the present invention.

FIG. 2 is an example of a flowchart of an execution target program in the microcomputer of the present embodiment.

FIG. 3 is a block diagram showing an embodiment of a conventional microcomputer.

FIG. 4 is an example of a flowchart of a program to be executed in a conventional microcomputer.

FIG. 5 is a diagram of a memory map of an emulation memory in one embodiment of a conventional microcomputer.

[Explanation of symbols]

 1 Microcomputer 2 Supervisor CPU 3 Emulation Memory 4 First Input / Output Terminal 5 Second Input / Output Terminal 6 Control Terminal 7 Conventional Microcomputer 10 BCU (Bus Control Unit) 11 EXU (Execution Unit) 14 Memory Writing Control circuit 15 Memory for condition satisfied storage 16 Memory for condition not satisfied 17 Execution state read control circuit

Claims (2)

[Claims] 1. A means for generating a branch instruction execution signal regardless of whether a condition is satisfied or not when executing a branch instruction,
Means for generating a branch instruction condition satisfied signal when the condition of the branch instruction is satisfied, and generating a condition satisfied signal and a write signal when the branch instruction condition satisfied signal is generated, and writing the condition satisfied storage memory When the branch instruction condition satisfied signal is not generated, a condition not satisfied signal and a write signal are generated, and means for writing to the condition not satisfied storage memory, and a branch instruction execution from the condition satisfied storage memory and the condition not satisfied storage memory And a means for reading out a status signal. 2. The microcomputer according to claim 1, further comprising means for externally inputting a read control signal of the means for reading the signal of the branch instruction execution state.