JPS6250855B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system, in particular,
This invention relates to a microprogram control system having a conditional branching function.

Generally, a microprogram control method using a microprogram consisting of a series of microinstructions is widely used as an execution control method for information processing devices. In this microprogram control method, an information processing device sequentially reads microinstructions stored in a high-speed (usually accessible in one machine cycle) storage device called a control memory to provide instructions for operations to be executed in each machine cycle. It is something to be carried out. This microinstruction not only controls the execution unit, but also determines the address of the control memory to be read next, so the microinstruction read from the control memory performs the functions of the complex sequential control circuit instead. Its features include simplification of hardware and ease of logical changes.

An example of a conventional microprogram control system is shown in FIG.

Microinstructions 21 read from control memory 2 to control execution unit 1 are held in microinstruction register 3.

A microinstruction is set in the microinstruction register 3 at the beginning of a machine cycle (= at the end of the previous machine cycle), and the value of the execution control field 31 is sent to the execution unit 1 to control the execution unit in that machine cycle. Determine the operation of step 1. By the end of the machine cycle, the execution results obtained as a result of the execution in the execution unit 1 are set in various registers and flip-flops within the execution unit 1.

On the other hand, the value of the address control field 32 in the microinstruction register 3 is sent to the address control section 4, and the address control section 4 determines the control memory address 41 to be read next according to the contents and provides it to the control memory 2. At the end of that machine cycle, the microinstruction to be executed in the next machine cycle is read from the control memory 2 and set in the microinstruction register 3.

The control memory address that directs the next microinstruction is
In addition to the case where the address is unconditionally given by the address control field 32, the control memory is obtained in the form of a two-way or multi-way branch depending on the values 11 of various registers and flip-flops in the execution unit 1. It may be a street address. In such a microprogram control system in which the next microinstruction is read in parallel with execution, wasted machine cycles often occur when microprogram branching is performed depending on the execution result.

For example, if we consider an operation in which an arithmetic operation is performed in an information processing device and there is no overflow, the result is written back to a register (visible to software), the operation is performed in the first machine cycle,
The calculation result is stored in an accumulator (an accumulation register that is invisible to the software), and at the same time an indicator is set to indicate the presence or absence of an overflow. In the next, second machine cycle, it is checked whether or not microprogram branching is possible based on the value of this indicator, and then address calculation is performed.

Then, in the third machine cycle in which the branch result is determined, the operation result is transferred (to a register visible to the software). In this example, one cycle is required to determine the calculation result, and the execution unit does not perform any effective operation during that cycle.

In order to avoid these essential weaknesses of the conventional microprogram control system and speed up processing, it is conceivable to use hardware control for conditional operations, that is, the portion that performs operations according to conditions.

In such cases, the microprogram control method uses a conditional microinstruction that says, ``If the overflow indicator is 0, transfer the contents of the accumulator to a register (visible to software).'' In the second cycle, the calculation result is transferred to a register or the like.

However, with such a microprogram control method, the necessary operations must be anticipated from the beginning of the design and incorporated into the hardware design in advance. This is not a problem if the specifications are simple, but if the microprogram control method requires complex microprogram control and it is unclear what kind of functions will be added in the future, hardware control may be necessary. There are limits to the solution of making the microinstructions run, and while the microprogram control method is easy to change specifications, it actually puts constraints on performance. In order to perform the corresponding action, each microinstruction must be created according to the condition and action.
Furthermore, if the conditions of the conditional branch microinstructions overlap, a huge variety of microinstructions must be prepared, which is impractical.

In conventional microprogram control systems, when the operation differs depending on the presence or absence of a certain condition, the program first branches using a conditional branching microinstruction that does not involve a valid execution operation, and then performs the desired operation.
The drawback was that it was not possible to shorten the execution time of microinstructions.

By standardizing the conditional control of microprogram branching and the control of inhibiting execution of microprogram operations, the execution time of microinstructions can be shortened.
Another object of the present invention is to provide a microprogram control method that can reduce the number of conditional operation type microinstructions.

The microprogram control method of the present invention includes a control memory for storing a microprogram consisting of a series of microinstructions, a microinstruction register for storing microinstructions to be executed read from the control memory, and a microinstruction register for storing microinstructions to be executed next. Microprogram address control that creates a microinstruction address, reads the next microinstruction to be executed from the control memory, and generates a branch instruction signal when the address control field of the microinstruction to be executed indicates a conditional branch. and an execution section in which execution of the microinstruction to be executed is inhibited by an execution inhibition signal generated in response to the branch instruction signal.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which an execution unit 1', a control memory 2', a microinstruction register 3', a microprogram address control unit 4', a branch condition signal 11,
The execution control field 31, address control field 32, and control memory address 41 to be read next of the microinstruction 21' read from the control memory are the first
Same as the figure. Address control field 32 is branch condition signal selection field 33 and address field 3.
It consists of 4. The value of the branch condition signal selection field 33 is determined by the microprogram address control section 4'.
It controls a condition signal selection circuit 42 in the execution section 1' and selects one of the branch condition signals 11 sent from the execution section 1' as a branch instruction signal 43. Branch instruction signal 43 is combined with the value of address field 34 to become the control storage address 41 to be read next. A branch condition signal 1 in which one bit in the branch condition signal selection field 33 is selected is sent to the condition signal selection circuit 42.
1, and thereby also realizes unconditional branching.

The microinstruction 21' stored in the microinstruction register 3' includes the microinstruction 21 shown in FIG.
Execution inhibition control fields 35 and 36 have been added to this, and both of these fields are composed of 1 bit. The logic gate 52 is a so-called exclusive OR element, and outputs "1" when the value of the execution inhibition control field 36 and the value of the branch instruction signal 43 are different.
Further, an AND gate 51 performs a logical product with the value of the execution inhibition control field 35, and the resulting execution inhibition signal 13 is applied to the execution inhibition control terminal 12 of the execution unit 1'.

Although details of the execution unit 1' are not shown, the first
In order to suppress the operation of the machine cycle regardless of the value of the execution control field 31 when the execution unit 1 and the execution inhibition control terminal 12 shown in the figure are "1", an inhibit gate, which is one of the operation inhibition control means, is activated. An execution inhibition signal 13 is supplied to the inhibit terminal to control whether or not to inhibit the operation. The simplest means for inhibiting this operation is to stop the clock supplied to the execution section 1' from its source. However, if the clock stop control as the operation inhibiting means is not sufficient in time, the operation inhibiting means may be provided immediately before the write control terminal of each register or flip-flop in the execution section 1'. At this time, instead of suppressing writing to all registers and flip-flops, only the portions whose operations are to be suppressed, such as registers visible to software and flip-flops that activate main memory access, may be suppressed to the necessary minimum. In any case, it is a common technique that is easy for those skilled in the art.

The operation of such an embodiment will be explained below using the example of the arithmetic overflow check mentioned above. After the operation is performed in the preceding machine cycle, the microinstruction 21' that executes the machine cycle instructs the transfer from the accumulator to the register in the execution control field 31, and sets "1" in the execution inhibition control field 35 to inhibit execution. control field 36
Set “0” to “0”. Further, the condition signal selection field 33 is set to select the overflow indicator, and the address field 34 is set to the address for reading the next microinstruction. This address is the same as for normal conditional branching, and is determined by the value of the overflow indicator.
However, at the same time, if the value of the overflow indicator is "1", the output of the logic gate 52 becomes "1", which is passed through the AND gate 51 and transmitted to the execution inhibit control terminal 12, and this machine Register transfers that were scheduled to be executed in cycles are suppressed. If the value of the overflow indicator is "0", the register transfer is executed. Since the clock to the microinstruction register 3 cannot be suppressed, the conditional branch operation itself is executed, and the microinstruction at the branch destination address is executed in the next machine cycle.

Note that the method of conditional branching in a microprogram is not to embed a conditional signal in a part of the bits at the specified jump address as described above, but to embed the conditional signal in a part of the bits at the designated jump address. There is a format in which a choice is made between branching to a specified jump destination or proceeding to the next (+1) address from the current address, but many conditional signals are ultimately connected to one signal line by a selection circuit. The circumstances of the collection are the same, and the present invention can be easily applied. Furthermore, if it is useful to inhibit the operation of a part of a multi-directional branch instead of a two-way branch, a person skilled in the art will be able to extend the operation inhibition field 36 and make detailed operation inhibition specifications. It would be easy to do so.

In this embodiment, an independent field is set apart from the execution control field and the address control field for inhibition control, but due to the constraints on the width of the microinstruction word, it is necessary to code and incorporate it into the address control field. An implementation method may also be considered in which it is incorporated as one of dozens to hundreds of types of microinstructions that are coded and defined in one field of an execution control field divided into two.

The microprogram control method of the present invention suppresses execution by using an execution inhibit signal generated in response to a branch instruction signal generated at the time of a conditional branch instruction, instead of constantly executing the operation of the execution unit.
This has the effect of shortening execution time because an operation that can be accomplished with multiple microinstructions can be executed with a single microinstruction.

Furthermore, as an additional effect, by linking execution suppression to the conditional branches of a microprogram, there is no need to create many conditional microinstructions that perform actions corresponding to the individual conditions of each microinstruction. This also has the effect of inhibiting execution with the same degree of freedom as the programming freedom of microprograms.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1 and 1'...execution unit, 2 and 2'...control memory, 3 and 3'...microinstruction register,
4 and 4'...Microprogram address control unit, 11...Branch condition signal, 12...Execution inhibition control terminal, 13...Execution inhibition signal, 21 and 2
1'...Microinstruction, 31...Execution control field, 32...Address control field, 33...Branch condition signal selection field, 34...Address field, 35, 36...Execution inhibition control field,
41... Control memory address to be read next, 42...
Condition signal selection circuit, 43...branch instruction signal, 51
...AND gate, 52...Exclusive OR gate.

Claims (1)

[Claims] 1 Create a control memory that stores a microprogram consisting of a series of microinstructions, a microinstruction register that stores the microinstructions to be executed read from the control memory, and the address of the next microinstruction to be executed. a microprogram address control unit that reads a microinstruction to be executed next from the control memory and generates a branch instruction signal when an address control field of the microinstruction to be executed indicates a conditional branch, and the branch instruction signal; 1. A microprogram control method, comprising: an execution unit in which execution of the microinstruction to be executed is inhibited by an execution inhibition signal generated in response to the execution of the microinstruction.