JPS63104156A - Information processor - Google Patents

Abstract

PURPOSE:To easily extend a data area and a stack area by using an address generating circuit to produce address signals in response to an operand read signal, an operand write signal and a stack read signal respectively. CONSTITUTION:A CPU 1 writes 'O' to the operand read signal register of a register file 200 by means of an input/output instruction. Then the CPU 1 executes an operand reading job and selects an operand read address signal out of a multiplexer 300 via a control signal line 100. In this case, a basic memory 2 is selected since the operand read address signal is kept at 'O' and the read data received from the memory 2 is read into the CPU 1. The CPU 1 executes an operand writing job by the next instruction and selects an operand write address signal. Then the operand data is written to an additional memory 3 from CPU 1. In such a way, the operand data are written to the memory 2 from the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device that performs address extension using a CPU.

[Conventional technology]

Conventionally, this type of information processing apparatus has accessed memory that exceeds the address capability of the CPU by extending the address by a method (hereinafter referred to as bank switching method) of extending the address signal using the upper bits of the address.

[Problem that the invention seeks to solve]

In the conventional information processing device described above, when using the bank switching method, a part of the memory area is allocated to overlapping addresses, and one area of the overlapping memory area is selected by specifying the bank. Because the memory is not allocated to a contiguous area, the addresses seen from the peripheral device side and the addresses seen from the CPU side are different, and this difference in addresses must always be taken into account when creating a program. There is a drawback.

[Means for solving problems]

The information processing device of the present invention includes a CPU, a basic memory that can be addressed by the CPU, an additional memory that can be addressed beyond the addressability of the CPU, and a The address generating circuit includes an operand read signal, an operand write signal, a stack write signal, and an address generation circuit that generates an address signal according to the stack read signal.

〔Example〕

Next, let's look at the drawings of the present invention! I will refer to and explain.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 1 is a CPU, 2 is a basic memory that can be addressed by the CPU 1, 3 is an additional memory that can be addressed beyond the address capability of the CPU 1, 4 is an address generation circuit that generates an address signal, and 5 is a peripheral device,
10 is a data signal line, 20 is an address signal line, 30 is an address signal line specifying additional memory, and 100 is an operand read.

This is a control signal line that indicates whether an operand write, stack read, or stack write is being executed.

FIG. 2 is a detailed block diagram of the address generation circuit of FIG. 1.

In FIG. 2, 200 is a register file containing address signals that specify the additional memory 3, 300 is a multiplexer that selects address signals, and 51 to 53 are used during operand read, operand write, stack read, and stack write, respectively. Indicates an additional address signal.

Next, the operation of transferring operand data from the basic memory 2 of the operation of the present invention will be explained.

First, "0" is written into the operand read signal register of the register file 200 using an input/output command from the CPU, and an upper address signal for addressing the additional memory 3 is written into the operand write signal register.

When CPU1 executes operand read with the next instruction,
The CPU 1 is connected to the multiplexer 3 via the control signal line 100.
Select the operand read address signal from 00. At this time, the operand read address signal is “0”, so
Basic memory 2 is selected, and read data from basic memory 2 is read into CPU 1.

When the CPUI executes an operand write with the following instruction,
The CPU 1 is connected to the multiplexer 3 via the control signal line 100.
Select the operand write address signal from 00. At this time, since the operand write address signal includes the upper address, the additional memory 3 is selected, and the operand data is written from the CPU 1 to the additional memory 3.

Similarly, by resetting the operand data in the register file 200, processing such as reading from the additional memo 1 and J3 and writing to the basic memory 2 is performed.

〔Effect of the invention〕

As explained above, the present invention provides an operand read signal,
By providing an address generation circuit that generates address signals in response to operand write signals, stack write signals, and stack read signals, there is an effect that the data area and stack area can be easily expanded. Note that although instructions cannot be run in the memory area expanded by the present invention, in systems that mainly use only data or stack areas, such as image processing, this does not cause any practical problems and makes it easier to create programs. This has the effect of making the hardware easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a detailed block diagram of the address generation circuit shown in the figure. 1... CPU, 2... Basic memory, 3... Additional memory, 4... Address generation circuit, 5... Peripheral device,
10...Data signal line, 20.30...Address signal line, 51-53...Additional address signal, 100...
・Control signal line, 200...Register file, 300
...Multiplexer.

Claims (1)

[Claims] A CPU, a basic memory that can be addressed by the CPU, an additional memory that can be addressed beyond the addressability of the CPU, and an operand read signal and an operand write signal of the CPU when an instruction of the CPU is executed. An information processing device comprising: an address generation circuit that generates an address signal according to a stack write signal and a stack read signal.