JPS6113629B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a data exchange path between processors in a multiprocessor.

FIG. 1 shows the configuration of a common bus type multiprocessor. Here, to simplify the explanation, it is assumed that the number of processors is two, and that there is one interrupt input between each processor.

In FIG. 1, 1 is a processor 1, 2 is a processor 2, 3 is a common bus, 4 is a common memory, 5 is an interrupt signal line from processor 11 to processor 22, and 6 is a line from processor 22 to processor 11.
This is the interrupt signal line for the

As a method of exchanging data between the processor 11 and the processor 22, there is a method using an interrupt. Conventionally, in this method, when the processor 11 provides some data to the processor 22, the processor 11 first transfers data to the common memory 4.
The data is written to a specific address in the processor 11, and then an interrupt is given to the processor 22 via the interrupt signal line 5. This causes the processor 22 to know that data is being given from the processor 11, and to respond to the given interrupt. The procedure is to accept the request, reset the interrupt signal 5, and then read data at a specific address in the common memory 4.

In this way, when transferring data using the conventional method, the processor 11 that provides the data executes two types of instructions: an instruction to write data and an instruction that generates an interrupt, and the processor 2 that receives the data executes two types of instructions: an instruction to write data and an instruction to generate an interrupt.
It was necessary to execute two types of instructions on the second side: an instruction to accept interrupts and an instruction to read data.

This invention enables each processor to transmit and receive data between two processors, unlike the conventional method.
It is designed to process data exchange and interrupts at the same time by simply executing one instruction in each processor, without the need to execute any other instructions.
This will be explained in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, where 1 to 4 are similar to those shown in FIG. 1, 7 is an interrupt signal generation circuit for the processor 11, and 8 is an interrupt signal generation circuit for the processor 22.

When processor 11 provides data to processor 22, processor 11 writes the data to address a assigned to interrupt signal 5 to processor 22 within common memory 4 address area. At the same time, the interrupt signal generation circuit 8 for the processor 22 inputs and decodes the address signal in the common bus 3, and since the address is the address a assigned to the interrupt signal 5 to the processor 22, the interrupt signal generation circuit 8 for the processor 22 An interrupt is generated by activating the interrupt signal 5. When an interrupt occurs, the processor 22 reads out the memory contents at the address a assigned to the interrupt signal 5 to its own processor in the common memory and receives the data. At the same time, the interrupt signal generation circuit 8 for the processor 22 decodes the address a and resets the interrupt signal generated for the processor 22. As a result, the data exchange from the processor 11 to the processor 22 is
This is possible by having each processor execute only one instruction.

FIG. 3 shows an embodiment of the interrupt signal generation circuits 7 and 8 according to the present invention, in which 1 to 7 are similar to those in FIG. 1 or 2, 9 is an address bus from the common bus 3, and 10 is an address bus from the common bus 3. A decoder that decodes the address assigned to the interrupt signal to each processor, 11 is an address decode signal line that becomes active by address decoding, 12 is a memory write signal line from the common bus 3, and 13 is a memory read from the common bus 3. signal line, 14 is an interrupt set signal line, 15 is an interrupt reset signal line,
16 is a flip-flop for generating interrupt signal 6;

When the processor 22 provides certain data to the processor 11, the processor 22 executes a data write command to the address b assigned to the interrupt signal 6 to the processor 11 in the common memory 4. At this time, a normal memory write operation is performed on the common memory 4 through the common bus 3, and data is written to the memory at address b. At the same time, the decoder 10 in the interrupt signal generation circuit 7 for the processor 11 receives an address from the address bus 9, decodes the address b, and makes the decode signal line 11 active. On the other hand, since the memory write operation is in progress, the memory write signal line 12 which is active on the common bus 3 is taken in, and these two signals 11 and 12 are
The interrupt set signal line 14 is activated by the AND condition, and the interrupt generation flip-flop 1 is activated.
6 and makes the interrupt signal line 6 for the processor 11 active. Through this interrupt, processor 11 learns that it is being given data by processor 22, and processor 11 executes a memory read instruction for the same address b. At this time, a normal memory read operation for address b is performed on the common memory 4 through the common bus 3, and the processor 11 reads the data written by the processor 22. At the same time, the decoder 10 in the interrupt generation circuit 7 for the processor 11 decodes the address b and makes the decode signal line 11 active in the same way as when the interrupt occurs. On the other hand, the memory read signal line 13, which is active because the memory read operation is in progress, is taken in, and the AND of these two signals 11 and 13 is carried out.
Depending on the conditions, the interrupt reset signal line 15 is made active, the interrupt generation flip-flop 16 is reset, and the interrupt signal 6 to the processor 11 is made inactive.

In the above explanation, we have described the case where the number of processors is 2 and the number of interrupt signals to each processor is 1, but if three or more processors are connected to the common bus 3, each processor can be Even when two or more interrupt signals are input, an interrupt signal generation circuit is provided that allocates an address within the common memory 4 address area for each interrupt signal input to each processor and generates the interrupt signal in each processor. Therefore, it can be applied to data exchange between arbitrary processors.

As described above, the present invention relates to the data exchange path between processors, and simultaneously uses signals for memory write operation or memory read operation for interrupt signal generation or reset operation.
By making it possible to transfer data by just executing one instruction by each processor, there is an effect that the operation of transferring data between processors is simpler and faster than in the past.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a conventional multiprocessor, FIG. 2 is a schematic block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the function of an interrupt signal generation circuit in the present invention. In the figure, 7 is an interrupt signal generation circuit for processor 1, 8 is an interrupt signal generation circuit for processor 2, 9 is an address bus,
10 is a decoder for addresses assigned to interrupt signals to the processor, 11 is a decode signal line, 12 is a memory write signal line, 13 is a memory read signal line, 14 is an interrupt set signal line, 15
1 is an interrupt reset signal line, and 16 is an interrupt signal generation flip-flop. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1. A plurality of processors that perform processing simultaneously and independently, a common memory that can be commonly accessed by each processor, and address signals, data signals, and memory write control signals (hereinafter referred to as memory write signals) for common memory access from each processor. ), memory read control signals (hereinafter referred to as memory read signals), each processor receives an address signal indicating a preset address within the common memory address area, and a corresponding bus. means for inputting a memory write signal to the memory at the address from a common bus and converting it to the processor as an interrupt signal from another processor; and a means for inputting a signal and resetting the interrupt signal, and when one processor executes a data write instruction to a common memory set to another processor, it corresponds to the corresponding address in the common memory. At the same time as writing data to the memory, an interrupt is generated to the processor to which the address is set, and then when the processor that receives the interrupt executes an instruction to read data to the set address, A multiprocessor characterized in that, at the same time as reading data in a memory corresponding to the set address in a common memory, an interrupt signal generated for its own processor is reset.