JPH04255062A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To improve throughput by setting up specific addresses for generating interruptions in the memories of respective processors constituting a multiprocessor system and processing information written in an inter-processor communication memory by interruption. CONSTITUTION:Respective processors 2 to 4 are connected to a common bus 1. The processors 2 to 4 are respectively provided with interprocessor communication memories 5 to 7, interruption signal generating parts 8 to 10 for generating interruption signals, and so on. The specific addresses for generating interruption are previously set up in respective memories 5 to 7. In the case of transmitting data from the processor 2 to the processor 4, the processor 2 writes data in the specified address of the memory 7 in the processor 4. Then information is written in the specific address. At the time of writing the information in the specific address, an interruption signal generating part 10 in the processor 4 outputs an interruption signal. A central processing unit 13 process the information inputted from the processor 2 by interruption processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-processor communication system in a multiprocessor system for communicating between processors via a common bus.

0002

[Prior Art] Conventionally, each processor used in a multiprocessor system has a memory for inter-processor communication, and an inter-processor communication method involves writing information to the inter-processor communication memory of its own processor. The program periodically checks whether the
If it is written, the corresponding processor performs the corresponding processing.

0003

[Problems to be Solved by the Invention] In the processors used in the conventional inter-processor communication method described above, when information is written from another processor to the inter-processor communication memory of the own processor, the processor to which this information has been written interrupts. Since the processor does not have a function to generate a message, it is necessary to periodically check whether information has been written to the own processor from another processor using a program. Therefore, the transmission of information is delayed, and the processing is also delayed, resulting in a drawback that the processing ability of the processor cannot be improved.

0004

Means for Solving the Problems In the inter-processor communication system of the present invention, first and second processors are connected to a common bus, and the first and second processors receive access from the common bus and their own processor. In an inter-processor communication system in a multiprocessor system where each processor has a storage section that can be accessed from the central processing section of the processor and the processors communicate via this storage section, a specific address for generating an interrupt is specified. The information is predetermined in the storage unit, and the second processor is notified that the information transmitted from the first processor via the common bus has been written to the specific address of the storage unit of the second processor. If the interrupt signal generating section identifies the interrupt signal, the interrupt signal generating section is configured to output an interrupt signal for the interrupt to the central processing section of the second processor.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram for explaining one embodiment of the present invention. In this example, three processors 2, 3, and 4 are connected to a common bus 1.
The processors 2, 3, and 4 each have interprocessor communication memories 5, 6, and 7, interrupt signal generators 8, 9, and 10 that generate interrupt signals, and receive interrupt signals. and central processing units 11, 12, and 13 each configured of a microprocessor that performs interrupt processing. FIG. 2 is a diagram showing an example of an interrupt signal generation section in FIG. 1, which includes a comparator 20 and a flip-flop 21, and generates an interrupt signal when writing is performed from the common bus side to a specific address of the interprocessor communication memory. Occur.

Next, the operation when the processor 2 transmits data to the processor 4 will be explained. First, a specific address for generating an interrupt is set in advance in the interprocessor communication memories 5, 6, and 7 of the processors 2, 3, and 4, respectively. In this state, the processor 2 writes data indicating the communication content to the designated address of the interprocessor communication memory 7 of the processor 4 via the common bus 1. Next, the processor 2 writes information to a predetermined specific address.

The interrupt signal generating section 10 of the processor 4 determines whether the information transmitted from the processor 2 has been written to a predetermined specific address of the interprocessor communication memory 7. That is, when an address that matches a predetermined address (address setting value) is input to the comparator 20 as a write address (memory address), the comparator 20 outputs a match signal, and this signal is sent to the flip-flop 21. At this time, a memory write signal input from the common bus side is latched at the same time as the above-mentioned address, and an interrupt signal is output to the central processing unit 13.

[0008] As a result, the central processing unit 13 to which the interrupt signal has been input recognizes that data from another processor, in this case processor 2, has been written to the interprocessor communication memory 7, and periodically checks the program. The information written in the inter-processor communication memory can be retrieved without any delay, thereby facilitating processing.

In this embodiment, the case of data transfer from the processor 2 to the processor 4 has been described, but other cases can be similarly executed.

0010

As explained above, in the present invention, a specific address for generating an interrupt is predetermined in the storage section of each processor, and the information transmitted from the first processor via the common bus is When the interrupt signal generation section of the second processor identifies that the data has been written to a specific address in the storage section of the second processor, the interrupt signal generation section sends a message to the central processing section of the second processor. Since the configuration is configured to output an interrupt signal for an interrupt, the information written in the storage section of each processor used for inter-processor communication can be processed without delay. This has the effect of improving the processing capacity of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the present invention.

FIG. 2 is a diagram showing an example of an interrupt signal generating section in FIG. 1;

[Explanation of symbols]

1 Common bus 2, 3, 4 Processors 5, 6, 7 Inter-processor communication memory 8, 9, 1
0 Interrupt signal generation unit 11, 12, 13 Central processing unit 20 Comparator 21 Flip-flop

Claims (1)

[Claims] 1. A first and a second processor are connected to a common bus, and the first and second processors are storage units that can be accessed from the common bus and from a central processing unit of the own processor. In an inter-processor communication method in a multiprocessor system in which the processors each have a storage unit and communicate between the processors via the storage unit, a specific address for generating an interrupt is predetermined in the storage unit, and the first When the interrupt signal generation unit of the second processor identifies that the information transmitted from the processor via the common bus has been written to the specific address of the storage unit of the second processor, The interrupt signal generation unit provides the central processing unit of the second processor with the following information:
An inter-processor communication method characterized by outputting an interrupt signal for an interrupt.