JPH03147046A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the execution speed of a data processor from being deteriorated even if the occurrence frequency of resetting and interruption is increased by setting a pair of data consisting of the address of an I/O port and data which is set in the I/O port in an initial state in a memory from a certain address. CONSTITUTION:In the initial state, MPU 8 sets a state flag in MPU 8, generates an address A and reads a pair of data 10. Then, MPU 8 writes prescribed data 10b in a pair of data 10 in the I/O port 2 which the address 10a of a pair of data 10 designates. Then, a macro instruction is executed. When a resetting signal or a special interruption signal is given to MPU 8 halfway, MPU 8 returns to the initial state after the execution of a processing such as an interruption processing. Thus, the I/O port 2 is initialized and the macro instruction is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data processing, and particularly to a data processing device equipped with an I10 port for exchanging data with the outside.

[Conventional technology]

FIG. 3 is a block system diagram showing a conventional data processing device, and FIG. 4 is an explanatory diagram showing the contents of the memory of the data processing device shown in FIG.

First, the configuration of a conventional data processing device will be explained with reference to FIGS. 3 and 4. In FIG. 3, the data processing device 1 is connected to an external control signal line 3 via an I10 port 2.
connected to. As a result, the data processing device 1 connects to an external peripheral device (not shown) connected to the external control signal line 3.
control and exchange data.

A microprocessor (hereinafter referred to as rMPUJ) 4 is, for example, an MPU such as an 8086, and is connected to a memory 6 and an I10 board 2 through an internal bus 5. Then, the MPU 4 reads the macro instruction stored in the memory 6, and according to this macro instruction, 10 votes 2. Performs operations such as data transfer between the MPU 4 and the memory 6, data transfer between the I10 port 2 and the external control signal line 3, and data processing within the MPU 4 (hereinafter referred to as "predetermined operations"). . Here, addresses are assigned to the I10 boat 2 and memory 6.

Further, FIG. 4 shows the initial setting of the memory 6, and the instructions 1. Command 2. Command 3. ..., instruction n... are all macro instructions. In FIG. 4, command 1. Command 2. Command 3. . . , instructions n, . . . are stored sequentially from address 8 on the memory 6.

Next, the operation will be explained. Here, in order to simplify the discussion, we will explain instruction 1. Command 1. Command 3. ..., instruction n, ...
It is assumed that the macro instructions are executed in the order of .

First, in the initial state, the MPU 4 generates an address A after setting a status flag (not shown) inside the MPU 4, and reads an instruction 1 from the memory 6. After performing the predetermined operation according to instruction 1, the MPU 4
An address where instruction 2 is stored is generated, and instruction 2 is read from memory 6. Similarly, command 2. Command 3.
...and the macro instruction is executed.

However, if a reset signal or a special interrupt signal is given to the MPU 4 in the middle, the MPU 4 returns to the initial state after performing some kind of processing such as interrupt processing, so the instruction 1. Command 2. Command 3. ..., instruction n, ...
・Execute macro instructions in the order shown.

[Problem to be solved by the invention]

In the data processing apparatus shown in FIGS. 3 and 4 above, the MPU 4 can return the internal state of the MPU 4 to its initial state when a reset or a certain type of interrupt occurs, but it is necessary to do this accordingly. It is not possible to initialize other parts, for example, initialize the I10 boat 2. The initial settings of I10 port 2 are macro instructions starting from address A, such as instruction l, instruction 2, instruction 3, and so on. ..., instruction n, .... This causes a problem in that the execution speed of the data processing device decreases as the frequency of occurrence of resets and certain types of interrupts increases.

The present invention has been made in view of these points, and its purpose is to provide a data processing device in which the execution speed of the data processing device does not decrease even if the frequency of occurrence of resets and certain types of interrupts increases. It's about getting.

[Means to solve the problem]

In order to achieve such an object, the present invention provides one or more addressed input/output units for inputting and outputting data, and a memory to which an address other than the address assigned to this input/output unit is assigned. In the data processing device, the storage unit stores a data pair consisting of an address value and a data value at a specific address in the storage unit. The processing unit stores at least one pair of data from a specific address in the storage unit at the time of initial setting or a certain special interrupt, and writes the data value to one or more input/output units specified by the address value. This is what I did.

[Effect]

The data processing device according to the present invention sets in memory a data pair consisting of the address of the I10 boat and predetermined data to be set in the I10 boat in the initial state, and When this occurs, the MPU automatically reads the data pair from the above address and sets predetermined data in the I10 port. This makes it possible to eliminate necessary macro instructions and increase the processing speed of the data processing device.

[Embodiment] FIG. 1 is a block system diagram showing an embodiment of a data processing device according to the present invention, and FIG. 2 is an explanatory diagram showing the contents of the memory of the device in FIG. 1.

First, the configuration of an embodiment of a data processing apparatus according to the present invention will be described with reference to FIGS. 1 and 2. In FIGS. 1 and 2, the same or equivalent parts as in FIGS. 3 and 4 are given the same reference numerals, and their explanations will be omitted.

The MPU 8 as a processing unit of the data processing device 7 normally reads macro instructions stored in the memory 9 and performs predetermined operations according to the macro instructions, like the conventional MPU 4. The operation in this state is different from the conventional one.

The memory 9 is assigned the same address as the memory 6. FIG. 2 shows the initial setting of the memory 9, and the address of the I10 boat 2 and the initial state of the I1
A data pair 10 consisting of predetermined data set to 0 port 2, an instruction 1 which is a macro instruction, an instruction 2 . Command 3.
. . , instructions n, . . . are stored sequentially from address 8 on the memory 9.

Next, the operation will be explained. Again, to simplify the discussion, the macro instructions are instruction l, instruction 2, and so on. Command 3. ...,
It is assumed that instructions n, . . . are executed in order.

First, in the initial state, the MPU 8 generates an address A after setting a status flag (not shown) inside the MPU 8, and reads the data pair 10 from the memory 9.

Then, the MPU 8 selects the address 10a of the data pair IO.
Initialization of the I10 port 2 is achieved by writing the predetermined data 10b of the data pair 10 to the I10 port 2 designated by the I10 port 2. After this, as in the conventional data processing device 1, command 1. Command 2. Command 3. ...Instruction n,
...and the macro instruction is executed.

Furthermore, if a reset signal or a special interrupt signal is given to the MPU 8 during the process, the M P tJ 8 returns to the initial state after performing some kind of processing such as interrupt processing, so the MPU 8 repeats the above operation again. The I10 port 2 is initialized and macro instructions are executed.

In addition, in the above embodiment, the I10 boat 2 and the data pair lO
Although an example has been described in which one number of I10 ports 2 and the number of data pairs 10 that must be initialized are the same, it is sufficient that the number of I10 ports 2 and the number of data pairs 10 that must be initialized are the same, and even if there are a plurality of them, the same effect as described above can be achieved.

〔Effect of the invention〕

As explained above, the present invention stores at least one data pair consisting of an address value and a data value from 219 specific addresses, and at the time of initial setting or a certain special interrupt, the data pair is stored from a specific address in the storage section. By reading the data value and writing the data value to one or more input/output units specified by the address value, it is possible to eliminate the macro instructions that were previously required, increasing the processing speed of the data processing device. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of a data processing device according to the present invention, FIG. 2 is an explanatory diagram showing initial settings of the memory of the device in FIG. 1, and FIG. 3 shows a conventional data processing device. The block system diagram, FIG. 4, is an explanatory diagram showing the initial setting of the memory of the device of FIG. 3. 2... Bow 10 boats, 3... External control signal line, 5...
・Internal bus, 7...data processing device, 8...MPU
, 9...Memory.

Claims (1)

[Scope of Claims] One or more addressed input/output sections that perform data input/output, a storage section to which an address other than the address assigned to this input/output section is assigned, and the input/output section and a processing unit that instructs reading and writing to the storage unit, wherein the storage unit stores at least one data pair consisting of an address value and a data value from a specific address of the storage unit. The processing unit reads the data pair from the specific address of the storage unit at the time of initial setting or a certain special interrupt, and the processing unit reads the data pair from the specific address of the storage unit, and transfers the data value to the one or more input/outputs specified by the address value. A data processing device characterized in that a data processing device writes data to a part.