JPH07271575A - Register expansion circuit - Google Patents

Abstract

PURPOSE:To eliminate the need of changing the specifications of a CPU and to reduce the number of program steps required at the time of accessing a register by directly writing data appearing next when an expansion instruction code is discovered in a data bus monitoring circuit. CONSTITUTION:When an expansion register mode is set, in an expansion register access control circuit 14, it is outputted to the data bus monitoring circuit 16. The data bus monitoring circuit 16 becomes a data bus monitoring mode corresponding to it, and when the expansion instruction code is detected, transmits detection to an expansion register selection signal generation circuit 18. When such detection of the expansion instruction code is transmitted, the expansion register selection signal generation circuit 18 selects an expansion register 12 so as to write the data appearing after the expansion instruction code into the expansion register 12. Thus, compared to a conventional case, the number of the program steps required at the time of writing the data in the expansion register 12 is reduced.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CPU (central proc
essing unit) and a register expansion circuit used in a CPU system having an address bus and a data bus connected to the CPU, and particularly, a specification change such as an increase in the instruction set of the CPU on the side accessing the register. The present invention relates to a register expansion circuit that can reduce the number of program steps required to access a register without requiring it.

[0002]

2. Description of the Related Art In a computer system, I / O
I / to which (input / output) and registers are assigned
The O address space is allocated to the memory address space, for example. Such I / Os and registers are called memory-mapped I / Os. Further, there is also one in which the I / O address space is independently allocated to the memory address space. This is generally I / O mapped I / O
It is called. In a general computer system, access to an I / O or a register is generally performed by a CP even if it is an I / O mapped I / O or a memory mapped I / O.
It is performed through U.

On the other hand, in Japanese Patent Publication No. 57-47510, I /
When accessing an O or register, specify its address as C
There is disclosed a technique in which a preset address register is used instead of the PU directly. The Japanese Patent Publication No. 57-
The 47510 includes an address register for storing the address of the internal register to be accessed, and
When actually accessing the register, the target internal register is addressed by the address stored in the address register. Therefore, according to the Japanese Patent Publication No. 57-47510, I / O to be accessed
It is not necessary to provide a large number of address lines for O and internal registers, and it is possible to reduce the number of input pins, for example.

FIG. 11 is a diagram showing a program example for accessing two registers in the Japanese Patent Publication No. 57-47510.

In this program example, CP
U is Z80 manufactured by Zilog Corporation in the United States. In addition, the Japanese Patent Publication Sho 5
It is said that the address of the address register corresponding to 7-47510 is "F0h" and the address of the internal register is "F1h".
It is an address in hexadecimal notation as indicated by "h". Moreover, what is shown by "b" is a binary notation. ).

Further, in the program shown in FIG. 11, one unit is processed every two steps. In particular,
The processing of steps 40 and 41 and the processing of steps 44 and 45 are for setting the address register when accessing the register. On the other hand, step 4
The processes of 2 and 43, the processes of steps 46 and 47, and the processes of steps 48 and 49 are processes for actually writing data in the internal register.

First, in step 40, the CPU register
To data A, immediate data n ₁Write. The a
Medium data n₁To the address register
This is the data to be written.

Then, in step 41, the data stored in the register A of the CPU is written into the address register indicated by the immediate data "F0h". Specifically, since the immediate data n ₁ is stored in the register A, the step 41
Is the immediate data to the address register
n ₁ will be written.

When the immediate data n ₁ is set in the address register in steps 40 and 41, the process of actually writing the data in the internal register is performed.

As the processing, first, at step 42, the immediate data n ₂ is written into the register A.
The immediate data n ₂ is data to be written in the internal register.

Then, in step 43, the data stored in the register A is written to the I / O address indicated by the immediate data "F1h". "F1h" of the immediate data is an I / O address which serves as a path for writing data to the internal register. The immediate data n ₂ is sent to the register A.
Is stored, the step 43 is to write the immediate data n ₂ to the internal register.

As described above, the Japanese Patent Publication No. 57-47510
Then, when trying to write the data n ₂ to the internal register indicated by the address of “n ₁ ” via the I / O address indicated by the address “F1h”, the setting process of the address register and the actual process are actually performed. This is a two-step process of writing data to the internal register. In this program example, steps 40 and 41-2
The address register is set in the three steps, and the actual 8-bit data is written in the internal register in the two steps 42 and 43.

In the following steps 44 to 49, "
This time, 16-bit data n ₄ is written to the internal register indicated by the address of n ₃ ″. Steps 44 and 45 are steps 40 and 41 described above.
The address register is set. Steps 46 to 49 correspond to steps 42 and 43 described above, and actually write 16-bit data to the target internal register.

FIG. 12 is a diagram showing program data of the above-mentioned conventional program example of FIG.

The total of 10 steps shown in FIG. 11, that is, steps 40 to 49, each become 2-byte program data. Further, the program example shown in these steps 40 to 49 is the address "20" in FIG.
The program data is stored in the memory space of 00h "to" 2013h "as program data.
It becomes a total of 20 bytes of program data.

13 and 14 show that 8-bit data is written twice. In other words, the "n _A " address to the 8-bit internal register "
The data of "n _B " is written, and the data of "n _D " is written to the 8-bit internal register indicated by the address of "n _C ".

[0017]

However, in the past,
When trying to access an I / O or a register, the processing is performed through the CPU and requires some program steps.

For example, in Japanese Patent Publication No. 57-47510,
It was necessary to set the address register. Also, C
Those that access I / O and registers via PU
The data to be written is temporarily written in the register A in the CPU. Therefore, it requires several program steps.

In order to reduce the number of program steps required to write data to the register, for example, CP
It is also possible to consider changing the specification of the U instruction set. However, LSI (large scale integrated
A circuitized CPU requires a design change of its integrated circuit pattern, which is not practical.

It is also possible to use a DMA (direct memory access) technique or the like. However, this requires complicated hardware such as many logic gates. Further, not only the control contents become complicated, but also various settings need to be made by the program in order to perform the DMA, so that the number of program steps is rather increased for the access of extremely small amount of data. DMA is not realistic.

The present invention has been made in order to solve the above-mentioned conventional problems, and does not require a specification change such as an increase of the instruction set of the CPU on the side of accessing the register, and when accessing the register. An object of the present invention is to provide a register expansion circuit capable of reducing the number of required program steps.

[0022]

SUMMARY OF THE INVENTION The present invention is a register extension circuit used in a CPU system having a CPU and an address bus and a data bus connected to the CPU, and an extension register connected to the data bus. , An extension register mode is set as a mode for accessing the extension register, and an extension register access control circuit storing the mode setting and a data bus monitoring mode corresponding to the extension register mode are set on the data bus. A data bus monitoring circuit that monitors the appearance of an extended instruction code in the memory, and if the extended instruction code is found in the data bus monitoring circuit, the extension register is written in order to write the data that appears next to the extended instruction code. The above-mentioned problems can be achieved by providing an extension register selection signal generation circuit for selection. In which the (corresponding to claim 1).

Further, the register extension circuit is provided with a plurality of the extension registers, and an extension address register for storing an extension register address indicating any one of the plurality of extension registers. When the extension register selection signal generation circuit finds the extension instruction code in the data bus monitoring circuit, the extension register address stored in the extension address register for writing the data appearing after the extension instruction code. By selecting the extension register indicated by
The number of accessible registers can be increased without expanding the address space such as the / O address space (corresponding to claim 2).

Further, in the register extension circuit, the extension register access control circuit simultaneously sets the mode of the extension register mode by setting and writing the number of registers of the plurality of extension registers to be accessed. Is automatically performed, and after the mode is set, the mode setting is automatically canceled after the extension registers are accessed the number of times of the number of registers, thereby achieving the above-mentioned object. This is intended to further reduce the number of program steps when accessing a plurality of registers (corresponding to claim 3).

[0025]

When writing data to a certain register, if the data is once transferred to a register in the CPU and then transferred again to a desired register, generally two steps of processing are required. Here, if the data to be written is directly written to the desired register, only one step is required. However, such an instruction set is not included in a general CPU. For example, the Z80 does not have such an instruction set. In the present invention, such data writing to the register can be performed in only one step (excluding preprocessing) by adding a relatively simple circuit.

FIG. 1 is a block diagram showing the gist of the present invention.

As shown in FIG. 1, the register extension circuit 10 of the present invention firstly includes an extension register 12.
Furthermore, the extension register access control circuit 14, the data bus monitoring circuit 16, and the extension register selection signal generation circuit 18
With.

First, the extension register 12 is connected to the data bus D. A CPU 1 is also connected to the data bus D. Regarding the extension register 12,
The present invention does not limit the number thereof, and it is sufficient that at least one is provided.

The extension register access control circuit 14
When the extension register mode is set as the mode for accessing the extension register 12,
The mode setting is stored. In addition, when the extension register mode is set, the extension register access control circuit 14 sets the extension register access control circuit 14 to the data bus monitoring circuit 1.
Output to 6. The present invention does not limit this mode setting. For example, in the embodiment described later, the mode is set by the data written in a specific dedicated register, that is, the control word register.

When the extension register access control circuit 14 inputs that the setting of the extension register mode has been made, the data bus monitoring circuit 16 goes into the data bus surveillance mode in response to this. In such a data bus monitoring mode, the data bus monitoring circuit 16 monitors the appearance of a predetermined instruction code, that is, an extended instruction code, on the data bus D. When the data bus monitor circuit 16 detects the extension instruction code, the data bus monitor circuit 16 transmits the detection to the extension register selection signal generation circuit 18.

Such an extended instruction code is input and monitored by the data bus monitoring circuit 16 and, of course, is also input to the CPU 1. This is because in the present invention, the C
This is because the operation of PU1 is not stopped. DMA that stops CPU operation during data transfer
The present invention differs from the art in this respect. In this way, the extended instruction code is monitored by the data bus monitoring circuit 16 and is also read by the CPU 1, so that it does not adversely affect the operation of the CPU 1 and is next to the extended instruction code. Immediate data must be present.

The extended instruction code may be of any type as long as such conditions are satisfied, and the present invention is not limited to this. For example, in an embodiment described later, an instruction code for writing immediate data to a register (register A, register HL, etc.) in the CPU 1 that does not cause a problem in program execution is used. The extension register selection signal generation circuit 18 detects the extension instruction code as described above by the data bus monitoring circuit 16.
From the extension instruction code, the data appearing after the extension instruction code is written to the extension register 12, so that the extension register 12 is selected. Specifically, it selects the extension register 12, for example, outputs an extension register selection signal.

As described above, in the present invention, the extension instruction code as described above is defined, and the data appearing after the extension instruction code is directly written to the extension register 12. Therefore, the number of program steps required when writing data to the extension register 12 can be reduced as compared with the conventional case. Further, since such an extended instruction code is defined and the instruction set itself of the CPU 1 is not changed, there is an advantage that cost increase due to hardware change and the like is small.

In the present invention, the above Japanese Patent Publication No. 57-
A device corresponding to the address register of 47510 may be provided. That is, a plurality of extension registers 12 are provided, and an extension address register that stores an extension register address indicating any one of the plurality of extension registers 12 is provided. Even in this case, according to the present invention, the number of required program steps can be reduced. That is, although it is necessary to set the address to the extension address register in advance, subsequent data writing to the extension register 12 can be performed directly to the extension register 12 without passing through the CPU 1. Is.

When a plurality of extension address registers 12 are provided in this way, it is necessary for the extension register selection signal generation circuit 18 to select any one of the plurality of extension registers 12. is there. That is, since the extension register selection signal generation circuit 18 writes the data appearing next to the extension instruction code when the extension instruction code is found in the data bus monitoring circuit,
One of the plurality of extension registers 12 indicated by the extension register address stored in the extension address register is selected.

When a plurality of extension registers 12 are provided in this way, the inventor also considers automatic setting and automatic cancellation of the mode setting of the extension register mode. Although the present invention is not limited to this, the extension register access control circuit 14 is configured to simultaneously write the extension register access control circuit 14 by setting and writing the number of registers (the number of writes) to which data is to be written among the plurality of extension registers. The extension register mode is automatically set. Further, the extension register access control circuit 1
In 4, the mode setting is automatically canceled after the access to the extension register is completed the number of times of the number of registers after the mode setting. By doing so, the extension register mode is set and released more automatically, and the number of required program steps can be further reduced.

[0037]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of a register circuit of an embodiment to which the present invention is applied.

In FIG. 2, the register circuit 50 is
It is connected to the address bus A and the data bus D to which the CPU is connected. The CPU of this embodiment is a Z80.
Is. A bus release signal BA, an I / O read signal IOR, and an I / O write signal IOW are input from the CPU to the register circuit 50.

First, the bus release signal BA is, for example, D
CPU for bus request signal issued from MA device etc.
Is a signal output by. The bus release signal BA is output to the device that has output the bus request signal, after the bus request signal is input and after the instruction being executed at that time is terminated.

When the bus release signal BA is output, a signal not directly related to the CPU is output to the data bus D. Therefore, in the register circuit 50, when the bus release signal BA detects that the bus is not occupied by the CPU, the register expansion circuit 10 suspends the processing such as writing data to the register. To do so. As a result, it is possible to prevent erroneous application of the present invention to monitor the appearance of the extended instruction code on the data bus D.

The I / O read signal IOR and the I / O read signal I / O
The O write signals IOW are all signals output from the CPU. These I / O read signal IOR and I / O write signal IOW are output when the CPU accesses I / O and registers. First,
The I / O read signal IOR is used by the CPU when reading data from an I / O or register.
It is output immediately after the address is output to.
On the other hand, the I / O write signal IOW outputs the write data to the data bus D immediately after the CPU outputs the address to the address bus A when writing the data to the I / O or the register. It is output after it is output.

Next, the register circuit 50 includes a register extension circuit 10 including a total of four extension registers 12A to 12D, as will be described later with reference to FIG. 4, in addition to a total of three registers 40A to 40C. Be prepared. Furthermore,
A data bus buffer 44 is provided for each of the registers 40A-40C. Further, the register circuit 50 includes an address decoder 46.

First, each of the registers 40A to 40C is an 8-bit register. These registers 40
Addresses "FCh" to "FFh" are sequentially assigned to A to 40C and the control word register included in the register expansion circuit 10.

Therefore, the address decoder 46 is one of the address lines A0 to A15 forming the address bus A, particularly the address lines A0 to A7 used for addressing the I / O address space. A7
Are all "1", decoding is performed according to the signals on the address lines A0 and A1 as shown in FIG. Also, according to the decoding result, the register selection signals SR1 to S
R4 is output.

These register selection signals SR1 to SR4
Are sequentially output to the data bus buffer 44 provided corresponding to each of the registers 40A to 40C and the register expansion circuit 10. The I / O write signal IOW is also input to each of the data bus buffers 44, thereby controlling the data input / output direction.

FIG. 4 is a block diagram showing the configuration of the register expansion circuit used in this embodiment.

As shown in FIG. 4, the register expansion circuit 10 includes a total of four expansion registers 12A to 12D. Further, the register expansion circuit 10 includes an expansion register access control circuit 14, a data bus monitoring circuit 16, an expansion register selection signal generation circuit 18, and a data bus buffer 42 arranged in each part.

First, the extension registers 12A and 12B
Are all 8-bit registers. The extension registers 12C and 12D are both 16-bit registers. Also, these extension registers 12
A data bus buffer 42 is provided in each of A to 12D. Furthermore, these extension registers 12A-1
These data bus buffers 4 provided for each 2D
On the other hand, on the data bus D side, another data bus buffer 42 which operates by the data enable signal DE is provided.

The extension register access control circuit 14
Is provided with the control word register 14a shown in FIG. 5 or FIG. The control word register 14a has its role defined for each bit as shown in FIG. 5 or FIG. In addition, in a predetermined bit of the control word register 14a, an extension register address for addressing any one of the four extension registers 12A to 12D in total is stored.

Further, the control word register 14a
The extension register access control circuit 14 is
It is stored that the mode setting of the extension register mode is performed as a mode for accessing any one of the extension registers 12A to 12D. That is, the mode setting of the extension register mode is performed by the control word register 14a (the address from the CPU is "FF").
This is done by writing data to h ").

Further, regarding the one shown in FIG.
Further, also in the case shown in FIG. 6, when the extension register mode is set, this is transmitted to the data bus monitor circuit 16 as the monitor enable signal WTC as shown in FIG. When the extension register mode is set, the extension register access control circuit 14 outputs the data enable signal DE and inputs the data enable signal DE.
Make 2 active.

FIG. 5 is a diagram showing a first example of the control word register.

In FIG. 5, the role of each bit of the 8-bit control word register 14a is shown. First, the write register is selected by bit B0 and bit B1 of the control word register 14a. This write register is selected by the extension register 1
It is to select any one of 2A to 12D, that is, to store the extension register address.
Further, the number of write bytes is set in the bit B2. That is,
The number of times of continuous writing to the extension registers 12A to 12D is set. Also, the presence or absence of a write request is set in bit B3.

That is, in the first example of the control word register 14a shown in FIG. 5, when it is attempted to write data to any of the four extension registers 12A to 12D in total, this request is sent to the bit B3. By setting to, the extension register mode is set. Further, after the mode setting, the bit B is added to the extension registers 12A to 12D.
When the access is completed the number of times set to 2, the bit B3 is reset to "0", and the setting of the extension register mode is automatically released.

Next, FIG. 6 is a diagram showing a second example of the control word register 14a in the present embodiment.

In FIG. 6, bits B4 and B5
The number of write bytes is set in the same manner as the bit B2 in FIG. In FIG. 6, when 2-byte data writing is set by the bits B4 and B5, the selection of the first-byte write register and the selection of the second-byte write register can be performed individually. Has become.
That is, like the bits B0 and B1 of FIG. 5, the write register can be selected.

Further, in the second example of the control word register 14a shown in FIG. 6, the mode setting of the extension register mode is simultaneously performed by setting and writing the number of write bytes to the bits B4 and B5. It is supposed to be done automatically. Further, after the mode setting, the mode setting is automatically canceled after the set number of times of writing data to the extension registers 12A to 12D. That is, after writing all data, both the bits B4 and B5 are reset (“0”),
The mode setting is automatically canceled.

In FIG. 4, the data bus monitoring circuit 16 enters the data bus monitoring mode when the setting of the extension register mode is transmitted by the monitoring enable signal WTC. When the data bus monitoring mode is set in this way, the data bus monitoring circuit 16 monitors that an extended instruction code appears on the data bus D. Specifically, the data bus monitoring circuit 16 determines whether the data on the data bus D is “3Eh (corresponding to an instruction code for loading immediate data into the register A at Z80)”, and It is provided with a comparator for judging whether the value of the data on the data bus D is “21h (corresponding to the instruction code for loading immediate data to the register HL at Z80)”. When the extension register mode is input by the monitoring enable signal WTC and the data on the data bus D becomes “3E”, the data bus monitoring circuit 16 targets the extension register selection signal generation circuit 18. Data discovery signal FND
1 is output. On the other hand, when the extension register mode is transmitted by the monitoring enable signal WTC and the data on the data bus D is "21h", the target data discovery signal F is sent to the extension register selection signal generation circuit 18.
Output ND2.

Further, the extension register selection signal generation circuit 1
Reference numeral 8 denotes a write register selection stored in the control word register 14a and the target data finding signal FN.
According to D1 or FND2, the extension register 12
In order to activate any one of the data bus buffers 42 provided in each of A to 12D, one of the extension register selection signals RE1 to RE4 is output.

For example, in the case of the control word register 14a of the first example shown in FIG. 5, the extension register selection signal generation circuit 18 uses the bits B0 and B1.
According to the above, any one of the extension register selection signals RE1 to RE4 is output. On the other hand, in the case of the second example shown in FIG. 6, the extension register selection signal RE according to the bits B0 and B1 when writing the data of the first byte.
1 to RE4, and outputs the extension register selection signals RE1 to RE4 according to the bits B2 and B3 in the case of writing the second byte data.

The outputs of the extension register selection signals RE1 to RE4 are made corresponding to the target data discovery signal FND1 or FND2. The target data discovery signal FND1 corresponds to an 8-bit data write request, and the target data discovery signal FND2 corresponds to a 16-bit data write. Therefore, when writing data to the 8-bit extension registers 12A and 12B, the data writing is performed when the target data discovery signal FND1 is input. On the other hand, when writing data to the 16-bit extension register 12C or 12D, this data writing is performed in synchronization with the input of the target data discovery signal FND2.

The extension register access control circuit 14 is controlled as described above when the register selection signal SR4 is input, and is provided on the data bus D side of the extension register access control circuit 14. The data bus buffer 42 is activated. Further, in the extension register access control circuit 14, when the bus release is transmitted from the CPU 1 by the bus release signal BA, the above processing is interrupted. This is because the data on the data bus D is generally irrelevant to the instruction code of the CPU when the bus release is transmitted, and the appearance of the extended instruction code is erroneously determined.

FIG. 7 is a diagram showing a first program example of writing data to the extension register in this embodiment.

The program example of FIG. 7 is intended for the first example of the control word register 14a shown in FIG. 5, and data is first written into the 8-bit extension register 12a, and then the 16-bit program is executed. Data is written to the extension register 12c.

First, in step 10, the data to be written to the control register 14a is written to the register A in the CPU as immediate data. Specifically, since only one byte of data is written to the extension register 12a, "08h" corresponding to this is written to the register A in the CPU1.

Then, at step 11, the data stored in the register A in the CPU 1 is written into the address of the control word register 14a indicated by "FFh" in the immediate data. Therefore, in step 11, "08h" is written in the control word register 14a.

After setting the data in the control word register 14a, setting the extension register mode and designating the extension address to which the data is written, the data is actually written to the extension register in step 12. . Specifically, the immediate data n
The instruction to write ₆ to the register A in the CPU 1 is executed.

The instruction code of the instruction is "3Eh",
The extended instruction code is defined as 8-bit data writing. Therefore, although the instruction in step 12 is originally an instruction executed by the CPU 1, the extended instruction code is indicated by the instruction code "3Eh", and the subsequent immediate data n ₆ is written to the extended register 12A. Be done. Data writing to the extension register 12A is mainly performed by the register extension circuit 10 to which the present invention is applied.

Then, in steps 13 to 15, data is written to the 16-bit extension register 12C.

First, in step 13, "0Eh" to be written in the control word register 14a corresponding to the writing of 2 bytes of data to the 16-bit extension register 12C is set in the register A in the CPU1.
Write to.

In the following step 14, the data stored in the register A in the CPU 1 is written into the address of the control word register 14a indicated by the immediate data "FFh". That is, in the step 14, the control word register 1
The data of "0022h" will be written to 4a. Thereby, for example, the extension register mode corresponding to the 16-bit data writing to the extension register 12C is set.

Then, in step 15, an instruction to write the immediate data n ₇ n ₈ to the register HL in the CPU 1 is executed. The instruction code for writing data to the register HL is "21h", which is defined in the extended instruction code as 16-bit data writing. Therefore, the step 15 is simply the CPU 1
Instead of being executed by the register extension circuit 10 to which the present invention is applied,
n ₇ n ₈ is written into the 16-bit extension register 12C.

Incidentally, FIG. 8 shows the Z80 shown in FIG.
9 shows actual program data of the program example of FIG. In this program example, the program data is stored in the memory addresses from “1000h” to “100Ch”.

In both cases, data is written to two extension registers, that is, the present embodiment shown in FIGS. 7 and 8 and the conventional example shown in FIGS. 9 and 10. As is clear from comparison with the above, according to the present embodiment, it is possible to reduce the number of program steps while realizing the same processing. For example, as is clear by comparing FIG. 7 and FIG. 9, the number of program steps can be reduced to 6 steps from 10 steps. Further, the program data can be reduced from 13 bytes to 20 bytes.

It should be noted that the setting of the control word register 14a and the address register of the conventional example, which is performed before the actual data writing to the extension register, requires 4 bytes both in this embodiment and in the conventional example. However, subsequent data writing to one 8-bit wide extension register can be performed with only 2 bytes in the present embodiment, compared with 4 bytes required in the conventional example. Further, data writing to one 16-bit wide extension register is possible with only 3 bytes in the present embodiment, compared with 8 bytes in the conventional example.

FIG. 9 is a diagram showing a second program example of writing data to the extension register in the present embodiment.

The program example of FIG. 9 is intended for the second example of the control word register 14a shown in FIG. 6, and has a total of two 8-bit extension registers 12a.
Data is continuously written to a.

First, in step 20, the data to be written to the control register 14a is written to the register A in the CPU as immediate data. Specifically, since only two pieces of 1-byte data are continuously written to the extension register 12a, the corresponding "24h" is written to the register A in the CPU1.

Then, at step 21, the data stored in the register A in the CPU 1 is written into the address of the control word register 14a indicated by the immediate data "FFH". Therefore,
In step 21, "24h" is written in the control word register 14a.

After setting the data in the control word register 14a, setting the extension register mode and designating the extension address to which the data is written, the data is actually written to the extension register in step 22. . Specifically, the immediate data n
The instruction to write _E and n _F to the register HL in the CPU 1 is executed.

The instruction code of the instruction is "21h",
It is defined as the extension instruction code as 16-bit data writing. Therefore, the instruction of step 22 is originally an instruction executed by the CPU 1, but the extended instruction code is indicated by the instruction code "21Eh", and the subsequent immediate data n _E and n _F have an 8-bit width. The data is sequentially output to the data bus D and sequentially written to the extension registers 12A and 12B. Data writing to the extension register 12A is mainly performed by the register extension circuit 10 to which the present invention is applied. When writing data to the extension register continuously for 2 bytes, according to the present embodiment, it is possible to further reduce the number of program steps and program data.

Incidentally, FIG. 10 shows the Z8 shown in FIG.
It shows the actual program data of the second program example of 0. In this program example, the program data is stored in the memory addresses from "1100h" to "1106h".

In all cases, data is written to two extension registers, that is, the present embodiment shown in FIGS. 9 and 10 and the conventional example shown in FIGS. 13 and 14. As is clear from comparison with the above, according to the present embodiment, it is possible to reduce the number of program steps while realizing the same processing. For example, as is clear from comparison between FIG. 9 and FIG. 13, the number of program steps can be reduced to 3 steps from 8 steps. Further, the program data can be reduced to 7 bytes from 16 bytes.

It should be noted that the present embodiment requires 4 bytes for the setting to the control word register 14a and the address register of the conventional example before the actual data writing to the extension register. On the other hand, in the conventional example, every time the 8-bit data is written twice, 4 bits are written.
Byte program is set, and convenience (4 × 2 =
8) I need bytes. Further, for the subsequent data writing to the two 8-bit wide extension registers, the conventional example performs the data writing twice twice independently, which is convenient (4 ×
2 = 8) bytes, but in this embodiment,
It is possible with only 3 bytes.

If an interrupt occurs during execution of the program examples shown in FIGS. 7 and 9, some malfunction may occur. For example, since the original instruction code is used as the extended instruction code in steps 12 and 15 of FIG.
When an interrupt occurs from the device or the like, a program or the like executed by the interrupt may malfunction. However, this can be easily dealt with by disabling interrupts. That is, prior to the program shown in FIG. 7, an interrupt prohibition instruction (Z80 mnemonic is "DI" and instruction code is "F3h") is executed.
After the execution of the program example shown in FIG. 7, the interrupt enable instruction (in the Z80, the mnemonic is "EI" and the instruction code is "FBh") is executed.

[0087]

As described above, according to the present invention, the number of program steps required for accessing a register can be reduced without changing the specifications of the side accessing the register, such as increasing the instruction set of the CPU. It is possible to obtain an excellent effect that it can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a block diagram of a register circuit of an embodiment to which the present invention is applied.

FIG. 3 is a diagram showing address decoding of the register circuit of the embodiment.

FIG. 4 is a block diagram showing a configuration of a register expansion circuit used in the embodiment.

FIG. 5 is a diagram showing a first example of a control word register used in the above embodiment.

FIG. 6 is a diagram showing a second example of the control word register.

FIG. 7 is a diagram showing a first program example for writing data to an extension register in the embodiment.

FIG. 8 is a diagram showing actual program data of the first program example of the embodiment.

FIG. 9 is a diagram showing a second program example for writing data to an extension register in the embodiment.

FIG. 10 is a diagram showing actual program data of the second program example of the embodiment.

FIG. 11 is a diagram showing a first program example for writing data to a conventional extension register.

FIG. 12 is a diagram showing actual program data of the first program example for writing data to a conventional extension register.

FIG. 13 is a diagram showing a second program example for writing data to a conventional extension register.

FIG. 14 is a diagram showing actual program data of the second program example for writing data to a conventional extension register.

[Explanation of symbols]

 10 ... Register expansion circuit 12A ... Expansion register A 12B ... Expansion register B 12C ... Expansion register C 12D ... Expansion register D 14 ... Expansion register access control circuit 14a ... Control word register 16 ... Data bus monitoring circuit 18 ... Expansion register selection signal generation Circuit 40A ... Register 1 40B ... Register 2 40C ... Register 3 42 ... Data bus buffer (unidirectional) 44 ... Data bus buffer (bidirectional) 46 ... Address decoder 50 ... Register circuit A ... Address bus D ... Data bus BA ... CPU Bus release signal from IOR ... I / O read signal IOW ... I / O write signal SR1-SR4 ... Register selection signal WTC ... Monitoring enable signal DE ... Data enable signal to extension register RE1-RE4 ... Extension register selection signal FND1 FND2 ... the target data discovery signal

Claims (3)

[Claims] 1. A register extension circuit used in a CPU system having a CPU and an address bus and a data bus connected to the CPU, the extension register being connected to the data bus, and a mode for accessing the extension register. As an extension register mode is set, an extension register access control circuit in which the mode setting is stored, a data bus monitoring mode corresponding to the extension register mode, and an extension instruction code appears on the data bus. A data bus monitoring circuit for monitoring, and an extension register selection signal generation circuit for selecting the extension register in order to write the data appearing after the extension instruction code when the extension instruction code is found in the data bus monitoring circuit. A register expansion circuit comprising: 2. The extension register according to claim 1, further comprising a plurality of extension registers, and an extension address register for storing an extension register address indicating any one of the plurality of extension registers. When the register selection signal generation circuit finds the extension instruction code in the data bus monitoring circuit, the extension instruction address stored in the extension address register is written to write the data that appears next to the extension instruction code. A register extension circuit for selecting the extension register shown. 3. The extension register access control circuit according to claim 2, wherein the extension register mode is set at the same time by setting and writing the number of registers to be accessed among the plurality of extension registers. A register extension circuit which is automatically performed and, after the mode setting, automatically releases the mode setting after the extension registers have been accessed the number of times corresponding to the number of registers.