JPH07129519A - Dual cpu system - Google Patents

Abstract

PURPOSE:To make a large capacity memory usable as the memory for temporary storage of data by constituting a pseudo dual port memory circuit by the address decoder of a CPU, a bus mediation controller, a bus buffer and the memory for temporary storage. CONSTITUTION:A bus arbitration controller 105 permits that a CPU 1 accesses a multiport memory 109 by returning a bus use permission signal BG 1 to an address decoder 103 and further opening a buffer 107 by making a G 1 signal active when the controller 105 judges that a CPU 2 does not access the multiport memory 109 when the controller receives a bus request signal BR 1. The controller 105 permits that the CPU 2 accesses the multiport memory 109 by returning a bus use permission signal BG 2 to an address decoder 106 and opening a buffer 108 by making a G 2 signal active when the controller 5 judges that the CPU 1 does not access the multiport memory 109 when the controller receives a bus request signal BR 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual CPU system, and more particularly to a dual CPU system capable of high speed data transfer.

[0002]

2. Description of the Related Art A conventional dual CPU system is provided with a CPU 1 indicated by 301 and a CPU 2 indicated by 310, as shown in FIG. The CPU 301 is connected to the local memory 1 represented by 302 via the CPU bus 1. On the other hand, the CPU 310 is connected to the local memory 2 represented by 312, the plurality of I / O devices 311, 314, 315, and the DMA controller 313 via the CPU bus 2. Also, CPU bus 1 and CP
The U-bus 2 is connected to the dual port memory 316 together so as to enable the transfer of data and commands between the CPUs, and the chip select terminal CS1 of the dual port memory 316 has an address from the CPU 1 represented by 303. An address from the CPU 2 is supplied to the chip select terminal CS2 via the decoder 1 and an address decoder 2 represented by 306.

As described above, in the conventional dual CPU system, the data and commands between the CPUs are transferred by using the dual port memory. From this figure, the local memory 1 on the CPU 1 side is transferred. The operation when transferring data to the I / O device on the CPU 2 side will be briefly described.

The CPU 1 reads out data necessary for transfer from the local memory 1, adds a command to the data and writes it in the dual port memory 316, and outputs an interrupt signal INT2 to the CPU 2. When the CPU 2 receives the interrupt, it reads the command from the dual port memory 316, judges the content of the command, and then the dual port memory 316
The data is read from and written to the target I / O device.

[0005]

In a single task system, such data processing is sufficient, but in a multitask system, I / O1 is transferred while transferring data.
It becomes necessary to transfer data to O2 as well. In this case, the amount of data increases and the capacity of the dual port memory 316 becomes insufficient (the current capacity of one dual port memory is several K).
It is necessary to temporarily transfer the data to the local memory 2 on the CPU 2 side and then transfer the data from the local memory 2 to the target I / O. This increases the load on the CPU 2 and makes it impossible to perform processing. Therefore, a DMA controller for data transfer is required.

However, in such a system, the data in the local memory 1 is first stored in the dual port memory 316.
To the local memory 2 and then to I
There is a problem that data transfer becomes very slow because the overhead is very large and the data is transferred to the / O device in three stages. Further CPU
On the bus on the second side, the CPU 2 and the DMA alternately take the bus for access, so that there is a problem that the time during which the CPU 2 can use the bus decreases and the time during which other I / O devices are accessed decreases.

[0007]

In order to solve the above problems, the present invention provides address decoders for the CPU 1 and CPU 2, a bus arbitration controller for arbitrating bus requests, and instructions from the bus arbitration controller. CP
A pseudo dual-port memory circuit was configured with a bus buffer that opens and closes a bus connected to U, and a memory for temporarily storing data, so that a large capacity memory can be used.

Further, instead of the dual port memory, a multi port memory (a memory having a parallel port and a serial port as an access port, one of which has a capacity of 256 Kbytes and has a large capacity) is used.
The parallel port side of the multi-port memory is CPU1 and C
Both the PU2 and the serial port are equipped with a DMA controller, and the DMA controller executes the data transfer from the multiport memory to the I / O device. Data can be transferred at high speed, and the time during which the CPU 2 can use the bus is increased.

[0009]

According to the above configuration, when a bus request is issued from the CPU1 or CPU2, the bus arbitration controller opens one of the bus buffers and enables access to the memory of the CPU1 or CPU2.

When a multi-port memory is used instead of the dual-port memory, data transfer to an I / O device connected to the serial port of the dual-port memory via the I / O bus is performed by the DMA controller. To be executed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A dual CPU system according to the present invention will be described below in detail with reference to the embodiments shown in the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

Reference numeral 101 denotes a CPU 1 having a local memory 1 102 via a CPU bus 1. 110 is CP
112 local memory 2 via CPU bus 2 in U2
And 111 I / O devices 3.

Reference numeral 103 denotes an address decoder 1 which determines that the CPU 1 is accessing the multiport memory and sends a bus request signal BR to a bus arbitration controller 105.
1 is output. 106 is an address decoder 2
The CPU 2 judges that the CPU 2 is accessing the multiport memory and outputs the bus request signal BR2 to the bus arbitration controller 105.

When the bus arbitration controller 105 receives the bus request signal BR1 and determines that the CPU 2 is not accessing the 9 multiport memory, it returns the bus use permission signal BG1 to the address decoder 1 of 3, and further G1 By activating the signal and opening the buffer of 7, the CPU 1 of 1 is allowed to access the multiport memory 9 and the CPU 1 is not accessing the multiport memory 9 when the bus request signal BR2 is received. If it is determined that the bus use permission signal BG
2 is returned to the address decoder 106, the G2 signal is made active, and the buffer 108 is opened.
The PU2 permits access to the multiport memory 109.

The input of the buffer 107 is the CPU bus 1
And its output is connected to the parallel port of the multiport memory 109, and as described above,
It is opened by activating one signal. On the other hand, the buffer 108 has its input connected to the CPU bus 2 and its output at the multiport memory 1
09 parallel port, as described above, G2
It is opened by activating the signal.

The multiport memory 109 is a memory having a parallel port and a serial port as access ports as described above, buffers 107 and 108 are connected to the parallel port, and I / O is connected to the serial port.
The bus is connected.

The interrupt request generation circuit 104 is used to generate an interrupt from each CPU to another CPU.

Reference numerals 111, 114 and 115 denote I's on the CPU 2 side.
I / O device, of which I / O device 111
Connect to the CPU bus 2 as described above, but
The O devices 114 and 115 are connected to the I / O bus connected to the serial port of the multiport memory.

The DMA controller 113 is for transferring data between the multiport memory 9 and the I / O devices 114 and 115.

Next, the operation of the dual CPU system according to this embodiment will be described with reference to the operation sequence diagram shown in FIG. As an example of data transfer, consider a case where data in the local memory 1 is transferred to the I / O devices 1 and 2. The CPU 1 prepares the data to be transferred to the I / O device 1 and writes the command and the data in the multiport memory. In this case, the address decoder 1 outputs the bus request signal BR1 to the bus arbitration controller 105, and the bus arbitration controller 105 confirms that the CPU 2 is not accessing the multiport memory 109 and returns the bus use permission signal BG1 and the buffer 107. Then, the G1 signal is output. This opens the buffer 107 and allows the CPU 1 to write data in the multiport memory.

Next, the CPU 1 accesses the interrupt request port to access the CPU 2 via the interrupt request generation circuit 104.
Generates an interrupt signal INT2. Upon receiving the interrupt, the CPU 2 understands the command written in the multiport memory 109, determines that the data is to the I / O device 1, sets the DMA channel 1 and starts the DMA transfer.

The DMA controller 113 uses the DMA channel 1 to transfer data from the multiport memory to the I / O device 1
Data transfer to.

On the other hand, since the CPU 1 further has data to be transferred to the I / O device 2, the data of the I / O device 2 is written in the multiport memory in the same procedure as above.

The CPU 2 similarly performs the DMA channel 2
To start data transfer to the I / O device 2.

The DMA controller 113 uses the DMA channel 2 to transfer data from the multiport memory to the I / O device 2
Data transfer to.

On the I / O bus, bus use arbitration is executed between two DMA channels in response to a request from each I / O device, and apparently data transfer is executed in parallel to the two I / O devices. High-speed transfer is possible.

[0028]

As described above, according to the present invention, data transfer is performed in two steps from the local memory 1 to the I / O device via the multiport memory, and therefore the overhead is small and high-speed transfer is possible. , And C of CPU2
Since the PU bus 2 and the I / O bus are separated and the DMA controller executes the transfer between the multiport memory and the I / O device, the CPU 2 is lightly loaded so that the processing of other I / O devices can be executed. become.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a dual CPU system according to the present invention.

FIG. 2 is an operation sequence diagram of the dual CPU system according to the present invention.

FIG. 3 is a circuit configuration diagram of a dual CPU system in a conventional example.

[Explanation of symbols]

 101 CPU1 102 Local Memory 1 103 Address Decoder 1 104 Interrupt Request Generation Circuit 105 Bus Arbitration Controller 106 Address Decoder 2 107, 108 Bus Buffer 109 Multiport Memory 110 CPU2 111 I / O Device 3 112 Local Memory 2 113 DMA Controller 114 I / O device 1 115 I / O device 2

Claims (2)

[Claims] 1. In a dual CPU system, a CP
A pseudo dual-port memory circuit is configured by an address decoder of U1 and CPU2, a bus arbitration controller that arbitrates bus requests, a bus buffer that opens and closes the bus according to an instruction from the bus arbitration controller, and a memory for temporarily storing data. Dual CPU characterized by
system. 2. A multi-port memory is used as the memory for temporarily storing data, a bus of the CPU 2 is separated from a bus of an I / O device (hereinafter referred to as an I / O bus), and the I / O is separated from the multi-port memory. A DMA (Direct Memory Access) controller for transferring data to the device is provided, and a CP from the local memory on the CPU 1 side is provided.
The data transfer to the I / O device on the U2 side can be executed at high speed, the bus of the CPU2 and the I / O bus are separated, and the CPU2 is operating even when the I / O device on the I / O bus and the CPU1 are transferring data. The dual C according to claim 1, wherein the dual C can execute other I / O processing.
PU system.