JPH0528090A - Memory controller - Google Patents

Abstract

PURPOSE:To reduce the load of a memory bus and to improve the efficiency of memory access by providing a local data memory accessed by each processor and a data bus connecting each processor and the local data memory independently of each other and dividing access areas by data. CONSTITUTION:A multiprocessor system is provided with two main storage devices, and only data shared among processors is accessed in one main storage device 2a, and the other local data memory 2b consists of a multiple port memory, and only local data for peculiar use of each processor is accessed in this memory 2b. When a program A is first executed in a CPU 1a, the CPU 1a outputs a bus request signal to a control signal bus 3b in the case of shared data. A bus control circuit 4 outputs a use permission signal of an address data bus 3a if any other CPU does not use it. The memory 2b is directly accessed in the case of local data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller in a multiprocessor system.

[0002]

2. Description of the Related Art The structure of the prior art will be described. 2 and 3
For example, "High-Performance Com
putter Architecture "(Harol
dS. Stone, 1987 Addison W
Issued by esley, pp. 299-303) is a block diagram of a conventional multiprocessor system. In FIG. 2, 1a, 1b, 1c, and 1d denote CPUs, and 2 denotes a main storage device. 3a is
An address data bus for transferring data and addresses between the CPUs 1a, 1b, 1c, 1d and the main memory 2, and 3b is a bus between the CPUs 1a, 1b, 1c, 1d and the bus control circuit 4. Is a control signal bus for transferring control signals for acquisition of Further, 3 is a memory bus composed of an address data bus 3a and a control signal bus 3b, 4
Is a bus control circuit that controls which CPU uses the memory bus 3. 3, the same reference numerals as those in FIG. 2 have the same functions as those shown in FIG. Also, 5a, 5
Reference numerals b, 5c, and 5d denote local memories dedicated to the CPUs 1a, 1b, 1c, and 1d to store data.

The operation of this conventional circuit configuration will be described below. Here, consider a case in which, for example, one program called Prog1 is executed in parallel by three CPUs on a multiprocessor system consisting of four processors in which a plurality of programs operate in time sharing. At this time, Prog is divided into three processing units (tasks), and the three divided tasks are assumed to be executed in parallel by three CPUs. Tasks obtained by dividing Prog1 into three are Prog1 (a) and Prog1
(B) and Prog1 (c). At this time, on this multiprocessor, in addition to Prog1, Prog2, P
log3 ,. ． ． Is assumed to be executed at the same time as Prog1 by time sharing. When this program is divided into multiple processing units (tasks), the data used in each task is (1) data used only within that task (local data), and (2) common to multiple tasks. There are two types of data (shared data) used.

In the conventional example as shown in FIG. 3, both (1) local data and (2) shared data are placed on the shared memory 2, and each CPU accesses all the data from the shared memory 2. To do. In the conventional example as shown in FIG. 4, (1) local data is stored in the local memories 5a, 5b, 5c, 5d of each CPU, and (2) shared data is stored in the shared memory 2. Then, each CPU accesses from the local memory connected to each CPU when accessing the local data, and all the CPUs access from the shared memory 2 when accessing the shared data. Here, as an example, Prog1
(A) is first executed on the CPU 1a, and the execution of the program is suspended once due to the time slice, or for some other reason, another program is executed on the CPU 1a, and the CPU of the Prog 1 (a) becomes free. It becomes a state of waiting for the
The operation of the conventional example shown in FIGS. 3 and 4 will be described by taking as an example the case where the execution of Prog1 (a) is restarted on U1b.

In the case of the conventional example of FIG. 2, Pr is set on the CPU 1a.
When execution of og1 (a) is started, Prog1 (a)
Data is shared memory both local data and shared data 2
Remembered above. At this time, when the CPU 1a accesses necessary data, the CPU 1a issues a bus request signal to the control signal bus 3b regardless of whether the data is local data or shared data. The bus control circuit 4 receives the signal, and another CPU receives the address data bus 3a.
Check if you are using. If no other CPU is using the address data bus 3a, the bus control circuit 4
A bus use permission signal is issued to U1a. CPU1a
When receiving the bus use permission signal, outputs the data address to the address data bus 3a and accesses the data in the main memory device 2. Other CPU is address data bus 3
When using a, the CPU 1a waits until the address data bus 3a becomes free, and when the memory bus 3a becomes free, outputs the data address to the address data 3a and accesses the data in the main memory device 2.

Next, Prog1 (a) enters the hibernation state,
Another program is executed by the CPU 1a, and Prog1
It is assumed that (a) is in a state of waiting for an empty CPU. After that, CPU1b is empty, Prog1 (a) is CPU1b
When the execution right is obtained and the execution is resumed on the CPU 1b, the memory access of the CPU 1b is performed in the same manner as before the execution is suspended because all the data of Prog1 (a) is in the shared memory. In the conventional example of FIG. 2, all data is stored in the shared memory 2, and all CPUs access all data from one shared memory.
The frequency of use of the address data bus increases. for that reason,
When the number of CPUs increases or a program that processes a large amount of data is simultaneously executed by a plurality of processors, the transfer speed of the address data bus cannot keep up with the execution speed of the CPU, and the CPU waits for the address data bus to become free. Longer and less efficient.

In the conventional example of FIG. 3, in order to improve such a situation, the local data uniquely used by the task is each C
The frequency of use of the address data bus is reduced by storing it in the local memory connected to the PU so that it can be accessed without using the address data bus and by placing only the data commonly used between tasks in the shared memory 2. It is a thing.

The operation of the conventional example shown in FIG. 3 will be described. C
When execution of Prog1 (a) is started on PU1a,
The data of Prog1 (a) is the local data of CPU1.
a is stored on a shared memory 5a provided adjacent to a,
The shared data is stored in the shared memory 2. At this time,
When the CPU 1a accesses necessary data, if the data is local data, the data is directly accessed from the local memory 5a, and if the data to be accessed is shared data, the CPU 1a issues a bus request signal to the control signal bus 3b. The bus control circuit 4 receives the signal and checks whether another CPU is using the address data bus 3a. If another CPU is not using the address data bus 3a, the bus control circuit 4 issues a bus use permission signal to the CPU 1a. When the CPU 1a receives the bus use permission signal, it issues the address of the data to the address data bus 3a and accesses the data in the main memory device 2.
When another CPU is using the address data bus 3a, the CPU 1a waits until the address data bus 3a becomes free, and when the address data bus 3a becomes free, outputs the address of the data to the address data bus 3a, Access the data.

Next, Prog1 (a) enters the rest state,
Another program is executed by the CPU 1a, and Prog1
It is assumed that (a) is in a state of waiting for an empty CPU. After that, CPU1b is empty, Prog1 (a) is CPU1b
When the execution right is obtained and the execution is resumed on the CPU 1b, the memory access of the CPU 1b is performed in the same manner as before the execution is suspended because the shared data is stored in the shared memory 2. However, when the local data is accessed, the local data of Prog1 (a) is stored in the local memory 5a connected to the CPU 1a that was being executed before the execution was paused, and therefore C
Prog1 (a) is CPU1 even if PU1b is empty
Continue to wait until a becomes available. When the CPU 1a becomes available, the execution is resumed on the CPU 1a and the local memory 5a
From the local memory 5a, or the CPU 1b restarts the execution, transfers the data from the local memory 5a to the local memory 5b, and then accesses the memory on the local memory 5b.

[0010]

Since the conventional memory access device in the multiprocessor system is configured as described above, in the case of the conventional example of FIG. 2, access to the main memory device 2 occurs so frequently. If not, there is a higher probability that the address data bus 3a is not used by another CPU. Therefore, it is not often necessary to wait for the permission to use the memory bus. However, when the number of CPUs is large or when a plurality of CPUs process a large amount of data at a high speed, the main memory device 2 is frequently accessed, so that the frequency of use of the address data bus 3a increases. .. Therefore, there is a problem in that the probability of waiting for obtaining permission to use the memory bus increases, and the performance decreases.

Further, in the case of the conventional example of FIG. 3, by placing local data in the local memory of the processor,
The frequency of use of the address data bus can be suppressed as compared with the conventional example of FIG. However, in a time-sharing system, when a task that has once been paused is re-executed, if it can be re-executed only by the processor that stores the local data that was used before the pause, another processor can operate. Even in the state, it is necessary to keep waiting until the original processor becomes free, and the load on the processor is biased, resulting in poor efficiency. Also, when a task that was once paused is re-executed, it can be re-executed from the local memory of the processor that was executing before sleep even if it can be executed by a processor other than the one that stores the local data that was used before sleep. There is a problem in that the efficiency becomes poor because it is necessary to copy the data to the local memory of the processor.

The present invention has been made to solve the above problems, and reduces the load on the memory bus when performing parallel processing on a multiprocessor system operating in a time sharing system to reduce the load on each processor. Eliminates load imbalance and data transfer between local memories,
An object is to obtain a device capable of efficient memory access.

[0013]

A memory control device according to the present invention includes a main memory device shared by processors, a data bus 1 connecting each processor and the main memory device, and a local memory accessed by each processor. A data memory and a plurality of separate data buses 2 for connecting each processor and a local data memory are provided. Shared data commonly used by the processors is stored in the main storage device, and data exclusively used by each processor is the local data. It is stored in a memory for local data, and the memory for local data can be accessed by each processor.

[0014]

In the memory control device according to the present invention, when each processor accesses the shared data, the main storage device provided for the shared data is accessed, and when each processor exclusively accesses the data, the local data memory is used. The access is controlled via another data bus 2.

[0015]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numerals 1a, 1b, 1c, and 1d denote CPUs, 2a and 2b are main storage devices, and 2b is a multiport memory. Shared data is stored in the main memory 2a and local data is stored in the multi-port memory 2b. 3a is a CPU 1a, 1b, 1c, 1
An address data bus for transferring data and addresses between d and the main storage device 2a. 3b is a CPU
It is a control signal bus for transferring a control signal for bus acquisition between 1a, 1b, 1c, 1d and the bus control circuit 4. Reference numeral 3c is an address data bus newly provided for transferring data and addresses between the CPUs 1a, 1b, 1c, 1d and the main storage device 2b.
A memory bus including address data buses 3a and 3c and a control signal bus 3b is shown. A bus control circuit 4 controls which CPU uses the address data bus 3a.

The multi-port memory has a plurality of memory ports and can be connected to a plurality of memory buses. Due to its structure, reading from the memory can be performed simultaneously from all the memory buses. As for writing to the memory, simultaneous writing to different addresses from each memory bus is possible. Of course, it is not possible to write to the same memory address at the same time, and it is necessary to select and write from one of the memory buses. In the present invention, the connection shown in FIG. 1 is used, and writing to each local memory is performed at different addresses, and reading is performed for each program. Therefore, different processors do not simultaneously read using different buses, and a certain program For, there is only access from one of the processors. In this way, the multi-port memory can refer to each address area under the protection of a plurality of processors.

Next, the operation will be described. The memory control device according to the present invention is provided with two main storage devices, and one main storage device 2a is made to access only shared data commonly used by processors, and the other main storage device 2b is accessed.
Is a multi-port memory, and controls each processor to access only the local data that it uses. As an operation example, a case similar to the description of the conventional example will be described. That is, the Prog1 (a) is first executed on the CPU1a, and the execution of the CPU is temporarily suspended due to the time sharing time or other reasons.
It will be in a waiting state. Then, another program is executed on the CPU 1a, and the other CPU 1b becomes free next time.
A case where the execution of Prog1 (a) is restarted on the CPU 1b will be described.

In this case, if the data is shared data,
The CPU 1a issues a bus request signal to the control signal bus 3b.
The bus control circuit 4 receives the signal and checks whether another CPU is using the address data bus 3a. If another CPU is not using the address data bus 3a, the bus control circuit 4 issues a bus use permission signal to the CPU 1a. When the CPU 1a receives the bus use permission signal, it issues a data address to the address data bus 3a and accesses the data in the main memory 2a. Other CP
If U is using the address data bus 3a, then C
The PU 1a waits until the address data bus 3a becomes empty. When the address data bus 3a becomes free, the address of the data is output to the address data bus 3a to access the data in the main memory 2a.

When the data to be accessed is local data, it differs from the case where the memory and the bus are shared data. Moreover, the main storage device 2 in which the local data is stored
Since b is composed of a multi-port memory, the multi-port memory 2b is accessed without checking the availability of the address data bus 3c. Next, Prog (a) enters the hibernation state, another program is executed in the CPU 1a, and P
It is assumed that log1 (a) is in a state of waiting for an empty CPU. After that, CPU1b is empty, Prog1 (a) is C
When the execution right on the PU 1b is obtained and the execution is restarted on the CPU 1b, the memory access of the CPU 1b is
Since the data in (a) is on the main storage device 2a and the multi-port memory 2b where both the local data and the shared data can be equally accessed by all the CPUs, it is the same as before the execution is suspended regardless of the operation of the CPU 1a. Done. That is, the frequency of use of the bus is suppressed, and there is no restriction on the relationship between the memory access of local data and the CPU, so that there is no waiting time in the processing time, and the operation speed becomes faster.

Example 2. In the above-described embodiment, an example is shown in which the number of CPUs is four and the number of divisions of the main storage device is two. However, even when the number of CPUs is five or more, the present invention has the same system configuration. Can have the functions presented by.

Example 3. Further, in the above-mentioned embodiment, the multi-port memory is used as the memory device for storing the local data. However, if the memory is replaced with a normal single-port memory, the efficiency is lowered to some extent, but the same function can be provided. .. In this case, since there is only one memory bus 2, the same operation as that for the memory bus 1 is required to establish the bus use right. This operation has already been described in the relation between the shared data and the memory bus 1 and will not be described here. When a single-port memory having the same configuration as a normal main memory is used as the local data memory, only the bus occupancy constraint works, and the processor constraint is not the same as in the multi-port memory.

Example 4. Further, although the number of main storage devices is two in the above embodiment, the number of main storage devices is three or more, some of which are used as main storage devices for placing a shared memory, and the rest are local memories. It can also be used as a storage device for storing.

[0023]

As described above, according to the present invention, in addition to the main storage device shared by the processors, the data bus 1 connecting the processors and the main storage device, the local data memory accessed by each processor is provided. Since another data bus 2 that connects each processor to the local data memory is provided and the area to be accessed by data is divided, efficient data access is possible and the processing time is shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory control device of a conventional multiprocessor system.

FIG. 3 is a configuration diagram of another memory control device of the conventional multiprocessor system.

[Explanation of symbols]

 1a, 1b, 1c, 1d CPU 2a Main storage device 2b Local data memory 3a Data bus 1 3b Data bus 2

Claims (1)

Claim: What is claimed is: 1. A main memory device shared by a plurality of processors, a common data bus 1 connecting the plurality of processors and the main memory device, and local data for each processor to access. A memory and a plurality of data buses 2 different from the data bus 1 connecting the processors to the local data memory are provided, and common data commonly used by a plurality of processors is shared via the data bus 1. The data used exclusively by each processor is the data bus 2
A memory control device comprising means for accessing the corresponding local data memory via the memory.