JPS6153747B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control method for a multiprocessor system, and particularly to a multiprocessor system that employs a buffer memory method and accesses a common main memory.
A multiprocessor system in which the area to be locked on the buffer memory is limited to blocks, thereby reducing access waiting time in cases where multiple access requests compete with each other for a common main memory. The present invention relates to a memory access control method.

As is well known, there is a buffer memory method as one of the processing methods for high-speed memory access, and the conceptual structure of the buffer memory method which uses a set associative method is generally as shown in FIG. In FIG. 1, 1 represents a main memory, 2 a directory, and 3 a buffer memory. For example, the main memory 1 is (M+
1)×(N+1) unit data blocks. Buffer memory 3 stores all unit data blocks 0 to [(M+1) in main memory 1.
(N+1)] is stored. In this case, the selected unit data block belongs to any array number within the storage area on the buffer memory 3 that has the same set number as the set number on the main memory 2 to which the unit data block belongs. Stored in address. As shown in the figure, the directory 2 has the same logical configuration as the buffer memory 3, and buffers the tag address information (corresponding to the tag number of the main memory 1) of the unit data blocks stored on the buffer memory 3. - Store at the same address as memory 3. Memory access is performed as follows. Based on the address information of the access destination, the tag address information in, for example, four unit storage areas belonging to the corresponding set number on the directory 2 is simultaneously read out, and the read tag address information is transferred to the tag address of the access destination address. Compare information. If any one of them is a comparison match, the information stored in the buffer memory 3 unit storage area corresponding to the directory 2 unit storage area where the match was found, that is, the unit data block, is read out and arithmetic processing is performed. On the other hand, if all comparisons do not match, it is determined that the desired data does not exist in the buffer memory 3, and the main memory 1
access and read the desired data. Then, arithmetic processing is performed using the read data, and the read data is transferred in units of blocks to unit storage areas belonging to the same set number on the buffer memory 3.

A multiprocessor system in which this type of buffer memory method is applied to a plurality of processor devices has a configuration as shown in FIG. 2, for example. In the figure, 1 is a common main memory, 2-0 to 2-S are directories, 3-0 to 3-S are buffer memories corresponding to directories 2-0 to 2-S, respectively, and 4 is a memory control memory. unit (hereinafter referred to as MCU), 5-0 to 5-S are respectively processors (hereinafter referred to as CPU), and 6-0 to 6-S are copy directories, respectively, with the same contents as directories 2-0 to 2-S. Each represents something that has.

This type of multiprocessor system generally uses a common main memory 1 for multiple CPUs 5-0 to 5.
- The following control is performed in consideration of data inconsistency due to sharing by S. Multiple CPUs 5 to the same address on common main memory 1
When access requests from 0 to 5-S conflict, for example, the one with the highest priority (for example, the one accessed first) based on a predetermined priority order
Only requests from CPU5-0 to 5-S are permitted. The authorized CPU 5-0 to 5-S reads the data at the access address from the common main memory 1 in blocks, and the read data is transferred to and stored in its own buffer memory 3-0 to 3-S. , used for data processing. During this time, other CPUs 5-
0 to 5-S are kept in a standby state and are not allowed memory access until at least the execution of the instruction is complete. In other words, authorized CPU5-0
or 5-S buffer memory 3-0 or 3
The entire contents of -S are made invisible to other CPUs 5-0 or 5-S, ie, locked. Therefore, even if a copy directory reference request from another CPU 5-0 to 5-S corresponds to data in the transfer block as described above, memory access is prohibited.

The present invention aims to solve the above points,
The purpose is to reduce the average access wait time of the entire system by locking only block areas that should be locked and allowing memory access requests from other CPUs to other storage areas. It is said that
Therefore, the memory access control method of the multiprocessor system of the present invention provides a plurality of processors each having a buffer memory and a directory, a copy directory corresponding to each processor, and access to a common main memory. In a multiprocessor system that refers to copy directories related to other processors and decides whether to permit or disallow the memory access based on the reference results, the main memory that should be area-locked corresponds to each copy directory. A lock register in which lock information corresponding to the address of the processor is set, and access request block information in memory access requests from its own processor and memory access requests from other processors based on the contents of the lock register. The present invention is characterized in that it includes a comparison circuit that compares the access request block information in the processor with the access request block information in the processor, and determines whether or not to accept a memory access request from another processor based on the comparison result by the comparison circuit. The present invention will be explained below with reference to FIG.

FIG. 3 shows the main configuration of an embodiment of the present invention, which corresponds one-to-one to each CPU 5-0 to 5-S. In the figure, 7 is a copy directory corresponding to each copy directory 6-0 to 6-S shown in Figure 2, 7-1
7-3 are unit copy directories belonging to the same array number, 8 is another address register in which instruction address information from other CPUs 5-0 to 5-S is set, and 9 is the own CPU 5-0 to 5-S. Own address register in which instruction address information from S is set, 10-0 to 10-
3 represents a comparison circuit, 11-0 and 11-1 each a comparison circuit, 12 a NAND gate with negative input, and 13 a lock register.

Other address registers 8 contain other CPUs 5-0.
Access address information when a memory access request is generated from 5-S is set. Own address register 9 contains the own CPU.
Access address information is set when a memory access request is generated from one of 5-0 to 5-S. Lock information corresponding to the access address information set in the own address register 9 is set in the lock register 13. Here, the lock information can be considered to be information indicating whether or not the access address information is locked. Comparison circuit 11-0 is connected to other addresses.
The tag address information in the register 8 and the tag address information in the own address register 9 are compared, while the other comparison circuit 11-1 compares the set address information in the other address register 8 and the own address register 9. Comparison processing is performed with the set address information in register 9. That is, the comparison circuit 11-0 and the other comparison circuit 11-1 cause the own CPU 5-0 to
or an access request block in a memory access request from one of the CPUs 5-S and the other CPU 5-
Matching/mismatching with the access request block in memory access requests from 0 to 5-S is detected. In this comparison process, if the content of the lock register 13 is, for example, logic "1", the above-mentioned comparison process is considered valid, and the self
One of CPU5-0 or 5-S and the other CPU5-
When 0 to 5-S both access the same block, the output of the NAND gate 12 with negative input becomes logic "0" due to each comparison match output from the comparison circuit 11-0 and the other comparison circuit 11-1. On the other hand, when accessing a different block, the output of the NAND gate 12 with negative input becomes logic "1". In addition, in the above comparison process, if the content of the lock register 13 is logic "0", the comparator circuit 11-0 and the other comparator circuits 11-1 can access the same block or different blocks. The comparison processing by is invalidated, and the output of the NAND gate 12 with negative input is set to logic "1". NAND gate 12 with negative input
The output is input to the other CPUs 5-0 to 5-S, and the other CPUs 5-0 to 5-S determine whether access is permitted or not based on the input signal.

In this way, the memory access request from the own CPU 5-0 or 5-S conflicts with the memory access request from the other CPU 5-0 or 5-S, and the own access request block that has been instructed to lock is The other CPUs 5-0 to 5-S are prohibited from accessing the memory only if the access request block is the same as the access request block, and in other cases, the memory access is permitted. Meanwhile own CPU
Memory access requests from 5-0 to 5-S are allowed to be made freely regardless of the contents of the lock information. Note that the copy directory, other address registers 9, and comparison circuits 11-0 to 11-
In the system consisting of 3 and 3, processing operations similar to normal copy directory reference processing are performed.

As explained above, the present invention uses normal copy directory reference processing in a multiprocessor system to determine whether an access request block in a memory access request from another CPU is a locked block or not. The memory access request is not permitted only when applicable. Therefore, the permission rate of memory access requests increases, and the average access waiting time of the entire system can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram conceptually representing a buffer memory method according to an embodiment of the present invention, FIG. 2 is a diagram conceptually showing the configuration of an embodiment of a multiprocessor system to which the present invention is applied, and FIG. 1 shows the configuration of main parts in an embodiment of the present invention. In the figure, 1 is a common main memory, 2-0 or 2-S
are directories respectively, 3-0 to 3-S are buffer memories respectively, 5-0 to 5-S are processors respectively, 6-0 to 6-S are copy directories respectively, 11-0 and 11-1 are respectively Comparator circuits, 13 represent lock registers, respectively.

Claims (1)

[Claims] 1 A plurality of processors each having a buffer memory and a directory, and a copy directory corresponding to each processor, are provided, and when accessing the common main memory, the copy directories related to other processors are referred to. In a multiprocessor system that decides whether to permit or deny the memory access based on the result, a lock function is used in which lock information corresponding to the address in the main memory to be area locked is set for each copy directory. A comparator circuit that compares access request block information in a memory access request from its own processor with access request block information in a memory access request from another processor based on the contents of the register and the lock register. 1. A memory access control method for a multiprocessor system, characterized in that the memory access control method for a multiprocessor system is configured to decide whether to permit or deny a memory access request from another processor based on the comparison result by the comparison circuit.