KR950013116B1 - Locking apparatus and its control method in ticom system - Google Patents

Abstract

a processor portion having a plurality of processors and sharing with a system bus; a system control module for the control of a system; an input/output board provided with an input/output processor; and a sharing memory board comprising first to fifth buffers for storing locking addresses, first to fifth AT(address tag) buffers/comparators for storing slot addresses of a request processor executing the locking and having the number of components corresponding to the number of the first to fifth buffers; a loader for detecting other conditions of each of the AT buffers/comparators to record the detected result in the first to fifth buffers or to execute a clear operation control, and a standard interface with the request processor.

Description

Locking device and locking control method of TICOM system

Fig. 1 (a) is a block diagram of a general tycom system, and (b) is a structure diagram of a locking buffer memory.

2 is a flowchart of a locking control method of a conventional Tycom system.

3 is a structural diagram of a buffer memory by the locking device of the Tycom system of the present invention.

4 is a flowchart of a control method for multi-locking in the present invention.

5 is a flowchart of a locking control method when applying a single processor / double buffer in the present invention.

6 is a flowchart of a method for controlling dynamic locking buffer selection in the present invention.

* Explanation of symbols for main parts of the drawings

5,6,7,8,9: Buffer 10,11,12,13,14: AT buffer / comparator

15: Loader 16: Interface

The present invention relates to a locking device and a locking control method of a TICOM system in which a multi-request can be performed by a locking algorithm in a main computer II for a computing computer network (Tycom: TICOM).

The basic configuration of Tycom shares a system bus (SYSTEM BUS), as shown in (a) of FIG. 1, a processor unit 1 composed of a plurality of processors, and a system control module 2 for system control. ), An input / output board (3) equipped with an input / output processor, and a shared memory board (4), and a tightly coupled (TIGHTLY COUPLED) structure in which a plurality of processors are mounted in one system and using a shared memory (4). The multiprocessor system is configured.

In particular, in the case of Tycom, the system has a high structure in a system having a large number of processors 1 by adopting a PENDED BUS which has an NON-MULTIPLEXED address and data lines and operates in synchronization with the main bus clock. Enable performance.

For example, when one processor of the processor unit 1 acquires a vested interest in the system bus and accesses the main memory, it drives the information related to the address on the bus. It gives the vested right to catch and operates as a PILE LINE overall.

In other words, a specific processor drives address-related information on one bus clock and releases a bus in order to obtain information of a memory area. In main memory, data is provided to a requesting processor through a data bus when data is valid.

In such a tightly coupled processor system, when a plurality of processors 1 want to use the shared memory 4, a certain CRITICAL SECTION exists so that a hardware may cause a specific processor to be caused by another processor. The need arises not to be infringed.

For example, the 68 *** family of processors is TAS (TEST AND SET), CAS, and CAS2 (COMPARE AND SWAP) INSTRUCTION.

TAS INSTRUCTION reads a certain bit in bytes and then writes it, which requires a locking device in the memory area because it must not be intruded by other processors until it reads and writes. Will be done.

CAS and CAS2 INSTRUCTION performs an interlock read (IR), which is distinguished from an INTERLOCK READ-normal lead, in the critical area and recognized by the memory area. WRITE-A type of light named by the Tycom system, distinguished from a normal light, and recognized by the memory area) may or may not occur.

In order to satisfy such a condition, a locking device is implemented in the memory area in hardware.

FIG. 1B shows the structure of a locking buffer memory (configured in the memory board 4) implementing the locking controller.

That is, the memory board 4 includes five 32-bit first through fifth buffers 4A-4E for storing a locking address, and the slot address (AT) of the request (processor) for which the locking has been performed. An AT buffer / comparator 4F for storing the data, a loader 4G for retrieving and controlling their status, and a standard interface 4H with the request processor.

Therefore, when the request (or processor) performs locking through the interface 4H, the address is stored in the corresponding buffers 4A-4E, and the slot address of the request (or processor) that performs the locking is stored in the AT buffer / comparator 4F. ), And the loader 4G retrieves the states of the buffers 4A-4E and the AT buffer / comparator 4F to perform locking control.

That is, the MC68 *** series of memory management units (MMUs) perform a READ-MODIFIED-WIRTE bus operation (locking-related INSTRUCTION) when visiting a page table, so the table's depth and size As a result, a continuous locking operation (CAS OR CAS2 INSTRUCTION) can be performed.

For example, when the MC68030 has a three-level structure, three to six locking operations can be performed according to the page table format. If the MC68030 has a higher level, more locking operations are performed.

Currently, the page table implemented in Tycom (3 levels, LONG PAGE DESCRIPTOR, SHORT DESCRIPTOR) is implemented to attempt 5 locking operations. Therefore, it does not occur when the bus operation is rejected under normal circumstances.

2 is a flowchart for explaining the above-described conventional locking control method.

First, it is necessary to decode the address-related information on the bus to determine whether it is a lock-related operation. If it is not a lock-related operation, it is determined whether or not it is currently locked. Determine.

If the critical area is locked, the AT buffer / comparator 4F compares the overlap with the critical area to generate a BUSY signal, and if not, performs a normal operation.

As a result of determining the locking related operation, if it is during the locking related operation, it is determined whether there is information stored in the buffers 4A-4E. If there is no information in the buffer, the address related information is actually recorded in the buffer 4A-4E. Lock the critical area.

However, if the information is already stored in the buffers 4A-4E, it is locked. Therefore, it is determined by searching AT information of the AT buffer / comparator 4F to determine whether the INSTRUCTION being executed is a read / write operation. In case of the operation, CAS and CAS2 are executed, and address related information is written to the upper buffer. In the case of a write operation, the corresponding buffer is cleared.

If BE * (BYTE ENABLE) is '0' during writing, the contents of all buffers are specifically cleared as DUMMY IW.

Through such operation, the locking control is performed in the tightly coupled multiprocessor. According to the conventional locking control method, there are the following problems.

First, since only one processor participates in locking-related operation at any one timing, the performance of the overall system is degraded. The maximum number of processors in the Tycom system is 23, so the remaining processors are waiting. As a result, the performance of the system is reduced.

That is, in the case of a system in which a plurality of processors are mounted and operated, such as Tycom, the conventional locking algorithm is greatly affected in terms of performance.

The collision frequency of such a processor depends on the execution speed of the processor and the frequency of locking operation in software. Therefore, if a conventional algorithm is adopted in a system equipped with a 68040 processor, there is a high possibility that a BUTTLE LOCK occurs in relation to the performance locking.

Second, in order to implement the locking, five buffers are required, and thus, the weight of the locking-related chips becomes large, and in the case of employing the MC68040 processor, the buffer is not used in the case of the current Tycom system. Does not cause INSTRUCTION).

Third, a separate device is required inside the processor board for generating the DUMMY IW.

In other words, additional logic is added to the processor board for DUMMY INTER LOCK WRITE. As a result, the hardware load of the system (number of chips) increases, and from the processor's point of view, the load due to the dummy interlock write. It is also difficult to avoid.

Therefore, the present invention enables a plurality of processors to participate in the locking operation to improve the performance of the system, and in the conventional MC68030 processor employing system, the maximum number of buffers is reduced to two, and efficient system operation is possible. It is an object of the present invention to provide a locking device and a locking control method of a TICOM system that can support CAS INSTRUCTION while participating in a locking operation. Hereinafter, the configuration of the present invention and its effects will be described with reference to the accompanying drawings. Is as follows.

First, FIG. 3 shows the configuration of the locking buffer memory according to the present invention, which is provided in the shared memory board 4 in FIG.

That is, share the system bus (SYSTEM BUS), and share with the processor unit (1) consisting of a plurality of processors, the system control module (2) for system control, the input and output board (3) equipped with an input and output processor, In constructing a multi-processor system having a tightly coupled (TIGHTLY COUPLED) structure using a memory board (4) and having a plurality of processors in one system and using a shared memory (4), It constitutes a locking buffer memory consisting of elements.

Five 32-bit first to fifth buffers 509 for storing a locking address, storing a slot address (AT; ADDRESS TAG) of a request (processor) for which locking is performed, and storing each of the buffers 5-9. Search for the first to fifth AT buffers / comparators 10-14 and other conditions of each AT buffer / comparator 10-14, and write them to the buffer 5-9 or clear them. It consists of a loader 15 in charge of the operation control and a standard interface 16 with the request processor.

The locking control method of the present invention performed by the apparatus configured as described above includes a mode determination step of determining an operation mode corresponding to a processor adopted by the system, and a result of the determination of the mode determination step. A multi-lock control step of performing a multi-locking routine in which the processor participates in the locking operation; a condition determination step of determining a single processor and a double buffer application condition when the processor of the MC68030 series is employed as a result of the mode determination step; A single lock control step of performing a single processor routine when the conditions for applying the single processor and the double buffer are satisfied in the condition determining step, and a dynamic processor routine for executing the single processor and the double buffer application conditions in the condition determining step. Dynamic lock control It is lost.

The effects of the present invention configured as described above will be described with reference to FIGS. 3 to 6.

4 is a flowchart showing a locking control algorithm for multi-locking in the locking control method of the TICOM system of the present invention, wherein the multi-locking control step is performed when it is determined that the multi-locking mode is performed in the mode determination step. This is a locking routine.

That is, if an event occurs, an AT buffer / comparator 10-14 suitable for the number of levels is set in order to compare an address or AT, and the loader 15 enters the system bus through the interface 16. Performs a locking related algorithm of the processor.

That is, it is determined whether or not the lock-related operation is determined, and if it is not the locking-related operation, it is determined whether the current lock is in the locked state.

If the current lock is not in the locked state, the operation is terminated. If the lock is locked, it is determined whether it is the critical area. If it is not the critical area, the operation is terminated.

As a result of the determination of the locking-related operation, if it is the locking-related operation, it is determined whether the buffer 5-9 is cleared, and if it is cleared, the address-related information is stored in the buffer 5-9 and the AT is stored in the AT buffer / comparator 10. -14) and exit.

However, if there is data in the buffer 5-9, it is determined whether it is a read operation. If it is a read operation, it is determined whether the buffer 5-9 is full. If it is FULL, a busy signal is generated. The relevant information and the AT are stored in the buffer 5-9 and the AT buffer / comparator 10-14, respectively, and then terminated.

If it is determined that the read operation is not a read operation, the AT is compared and the buffer is cleared in the buffers 5-9 according to the comparison result and then terminated.

This algorithm does not use more than one consecutive interlock lead (IR) because the processor does not use CAS-related INSTRUCTION, such as 68030, to retrieve the MMU table when the processor adopts 6840 processor.

Therefore, when the 68040 processor is adopted, the number of buffers is excessive in the existing algorithm, and when AT buffer / comparator is actually added, up to five processors can participate in locking related operations, enabling efficient system operation. Will be done.

5 is a diagram illustrating a locking control method of a TICOM system when a single processor and a double buffer are applied in the present invention, and the single lock performed when the single processor determination condition is satisfied in the mode determination step and the condition determination step. Single processor routine in the control phase.

That is, in the mode determining step, the MC68030 processor, and in the condition determining step, it is determined whether the locking related operation, the buffer clear, or the AT comparison result is matched, and the locking related operation, the buffer is not cleared, and the AT matched condition is determined. If satisfied, the process proceeds to a single processor routine. The routine determines whether the operation is locking related and compares the AT if it is not a locking related operation. In the case of the locking-related operation, the second step of determining whether the buffer is cleared and if it is cleared stores the address-related information and the AT in the corresponding buffer, sets the first flag and ends, and clears the buffer as a result of the determination of the second step. If not, compare AT and generate busy signal, then exit. A third step of determining whether the read operation is performed; a fourth step of determining whether the buffer is full when the read operation is completed; If it is determined that the buffer is not in the FULL state, the address-related information is stored and terminated. If the buffer is in the FULL state, the buffer in which the first flag is set is cleared, the address-related information is stored in the buffer, and the first flag is set in another buffer. The fifth step is to set and finish.

This is an algorithm that requires up to two locking buffers per processor, even in a conventional 68030 processor system.

For example, in case of CAS INSTRUCTION, interlock write (IW) does not necessarily occur after interlock read (IR), but if interlock read (IR) occurs continuously, the buffer is cleared, interlock read (IR) occurs, and all When finished, the buffer is cleared when NORMAL INSTRUCTION is active on the bus.

This prevents a dead look condition.

That is, as shown in FIG. 5, when it is determined that the operation is locking related, and not the locking related operation, the AT is matched by comparing the ATs of the AT buffer / comparator 10-14. If it is clear, if it is not the locking related operation, it is determined whether the buffer 5-9 is in the clear state, and if it is clear, the address related information is stored in the buffer 5-9 and the AT is stored in the AT buffer / comparator 10-14. After saving to the first flag (FIRST FLAG) is set.

However, if the buffer search result is not clear (when data is present), the AT is compared, and if it does not match, the busy signal is generated and terminated. If the match is found, it is determined whether the read operation is performed.

If it is not a read operation, the buffer 5-9 is cleared. If it is a read operation, the buffer 5-9 is determined to be full and if it is not full, the address related information is stored in the corresponding buffer and terminated. After clearing the first flag setting buffer, the address related information is stored in this cleared buffer, the first flag is set in another buffer, and then terminated.

That is, the locking control method of the TIC0M system of the present invention applied to a single processor and a double buffer application device includes the steps of clearing all the buffers when the interlock write (IW) occurs and the first when the third interlock read (IR) occurs consecutively. Clearing a buffer, clearing all buffers when a dummy interlock write (DUMMY IW) occurs, and clearing all buffers when the locked AT is in a normal operation state.

FIG. 6 is a diagram illustrating a control algorithm for selecting a dynamic locking buffer in a locking control method of a TICOM system according to the present invention. As shown in FIG. 6, a dynamic processor routine of a dynamic lock control step determines whether a locking related operation is performed. If the AT is matched and the corresponding buffer is cleared, the buffer is cleared and terminated. If the lock-related operation is performed, the first step of determining whether the buffer is cleared, and if the buffer is cleared, the address related information and the AT Is stored in the buffer, the first flag is set, and the second step is terminated. If the buffer is not cleared as a result of the determination of the second step, the AT is compared with the third step to determine whether the buffer is full. And if the buffer is in the FULL state as a result of the third step, generates a busy signal and ends. In the fourth step of determining the surface address overlap and the result of the fourth step, in the case of the address overlap, the busy signal is generated and terminated. If not, the address-related information and the AT are stored in the corresponding buffer and the first flag is generated. After setting the step 5 is completed.

That is, when the application (APPLICATION) is necessary because the case of FIGS. 4 and 5 are always present, the loader 15 is configured to select each mode by a dip switch or a register level, and the processors 68030/68040 are configured. If it is 68030, the algorithm for the multi-locking of FIG. 4 is performed. If the CAS INSTRUCTION is adopted and the multi-locking scheme is established, deadlock may occur in this scheme.

For example, after the first processor performs an interlock read (IR) to the first memory and at a next timing, the second processor performs an interlock read (IR) to the second memory, and then the first processor adds another memory to the second memory. Attempting to interlock read (IR) causes the second memory to be locked by the second processor, and in other cases deadlock (DEAD LOCK) even when the second processor attempts to interlock read (IR) to the first memory. ) Occurs.

In order to prevent such a case, an algorithm that does not allow access when all bits except the LSB (1 byte) of an address are matched is required. In such a case, a LONG DESCRIPTOR is generated when the processor performs a CAS INSTRUCTION. Can occur when used.

Therefore, in the control process of the present invention shown in FIG. 6, the concern of the deadlock of CAS INSTRUCTION is eliminated through the determination of the address overlap.

Referring to the dynamic locking buffer selection control process of the present invention as follows.

First, as described above, the processor set by the dip switch (or register) connected to the loader 15 is determined, and if the processor is 68040, the process of FIG. 4 is performed.

If the operation is not related to the locking, the AT is compared by the comparator 10-14, and when the AT is not matched, the AT is terminated.

However, in the case of non-locking operation, it is determined whether the buffer 5-9 is cleared, and if cleared, the address related information is stored in the buffer 5-9 and the AT is stored in the AT buffer / comparator 10-14. After the first flag is set and terminated, if the buffer is not cleared (data is present), AT is compared to determine whether a match is made.

If the AT is matched, the single processor and the double buffer applying algorithm of FIG. 5 are performed. If the AT is not matched, it is determined whether the buffer 5-9 is FULL.

If the buffer is FULL, a BUSY signal is generated and terminated. If it is not FULL, it is determined whether the address overlaps.

The address overlap is determined when only the lower bits (LSB 1 byte) of the address do not match and all the upper bits match.

If the address is not overlapped, the address-related information is stored in the buffer 5-9 and the AT is stored in the AT buffer / comparator 10-14. Then, the first flag is set and terminated. If the overlap occurs, the BUSY signal is generated and terminated. This eliminates the possibility of deadlock in CAS INSTRUCTION.

As described above, according to the multi-locking control method of the present invention, since a plurality of processors can participate in a locking operation, it is possible to prevent a system down in a system equipped with multiple processors, and to apply a single locking control method. Since the memory board configuration can be simplified by limiting the buffers of the memory board to two, and the logic configuration of the processor board for the existing dummy interlock write is excluded, it is economical and the algorithm according to the dynamic locking control method of the present invention There is an effect that can be properly operated according to the structure and performance requirements of the.

Claims (9)

A processor unit 1 comprising a system bus, comprising a plurality of processors, a system control module 2 for system control, an input / output board 3 having an input / output processor, and a shared memory board. In the multi-processor system of the TIGHTLY COUPLED structure which consists of (4) and is equipped with a plurality of processors in one system using the shared memory (4), the memory board (4), locking 32-bit first to fifth buffers 5-9 storing an address, and storing slot addresses (AT) ADDRESS TAGs of requests (processors) for which locking has been performed; Search for the first to fifth AT buffers / comparators 10-14 and other conditions of each AT buffer / comparator 10-14 configured according to the number of levels of the AT buffers / comparators 10-14, and write them to the buffer 5-9 or perform a clear operation. The loader (15) responsible for control, the request processor Tie comb (TICOM) a locking device of a system including a standard interface (16). The locking device according to claim 1, further comprising a dip switch for inputting selection information of a processor employed in the system to the loader (15). 2. The locking device according to claim 1, further comprising a register for inputting selection information of a processor employed in the system to the loader (15). A mode determination step of determining an operation mode corresponding to a processor adopted by the system, and a multi-locking routine for performing a multi-locking routine in which a plurality of processors participate in a locking operation when the MC68040 series of processors is used as a result determined in the mode determination step. In the control step and the result of the mode determination step, in the case of adopting the MC68030 processor, a condition determination step of determining a single processor and a double buffer application condition, and a condition of the single processor and double buffer applying condition are satisfied. Locking of the TICOM system comprising a single lock control step for performing a single processor routine and a dynamic lock control step for performing a dynamic processor routine when the condition for determining the single processor and the double buffer is not satisfied in the condition determination step. Control method. The method of claim 4, wherein the mode determining step determines whether the MC68040 processor or the MC68030 series processor is read by reading information provided to the loader (15) by a dip switch or a register. 5. The method of claim 4, wherein the multi-locking routine performed in the multi-lock control step determines whether the lock-related operation is performed, and if the lock is not a lock-related operation, the lock is determined by determining whether the lock is currently engaged or a critical area. A first step of generating and closing a busy signal in the critical area and ending the lock if not locked or in the critical area, and in the case of the current locking-related operation as a result of the determination of the first step, determining whether or not the buffer is cleared The second step of storing and terminating the address-related information and the AT in the corresponding buffer, respectively, and if the buffer is not cleared as a result of the determination of the second step, the read operation is determined to compare the AT if the read operation is not read and the corresponding buffer If the third step of clearing and ending the operation, and if the read result of the third step is a read operation, it is determined whether the buffer is full or not. End was generated if the signal, FULL or a method of controlling the locking tie comb (TICOM) system of the address information and the AT to the fourth step ends after saving its buffer. The method of claim 4, wherein the determining of the condition comprises determining whether the lock related operation is performed, whether the buffer is cleared or whether the AT comparison result is matched, and the locking related operation, when the buffer is not cleared and the AT matched condition is satisfied. How to control locking of TICOM systems to transition to routines. 5. The method of claim 4, wherein the single processor routine performed in the single lock control step comprises: a first step of determining whether or not the lock related operation is performed and comparing the AT to compare the AT if not the lock related operation; If it is determined that the locking-related operation is performed in the first step, the second step of determining whether the buffer is cleared and if it is cleared stores the address-related information and the AT in the corresponding buffer, sets the first flag, and then terminates. If the buffer is not cleared as a result of the determination, if the AT does not match and compares the AT, the busy signal is generated and terminated. A fourth step of determining whether the buffer is full or a read result of the fourth step If the status is not FULL, save the address-related information and exit. If the status is FULL, clear the buffer in which the first flag is set, save the address-related information in the buffer, and then set the first flag in another buffer. The locking control method of the TICOM system consisting of five steps. 5. The method of claim 4, wherein the dynamic processor routine performed in the dynamic lock control step determines whether the lock-related operation is performed. A first step of determining whether or not the buffer is clear; a second step of storing address related information and AT in the corresponding buffer, setting the first flag, and ending if the buffer is cleared as a result of the determination of the first step; If the buffer is not cleared as a result of the determination of the second step, the third step of determining whether the buffer is FULL if the AT is matched, and the busy signal is generated if the buffer is in the FULL state. The fourth step of determining the address overlap if not in the FULL state and the determination result of the fourth step. The method of controlling the locking of the TICOM system includes a fifth step of generating and ending a busy signal, and if not an address overlap, storing address-related information and AT in the corresponding buffer, and setting and ending the first flag. .