JPS62134751A - Information processor - Google Patents

Information processor

Info

Publication number
JPS62134751A
JPS62134751A JP27495185A JP27495185A JPS62134751A JP S62134751 A JPS62134751 A JP S62134751A JP 27495185 A JP27495185 A JP 27495185A JP 27495185 A JP27495185 A JP 27495185A JP S62134751 A JPS62134751 A JP S62134751A
Authority
JP
Japan
Prior art keywords
information
shared memory
memory device
computers
output device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27495185A
Other languages
Japanese (ja)
Inventor
Morimasa Kudou
工藤 謹正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP27495185A priority Critical patent/JPS62134751A/en
Publication of JPS62134751A publication Critical patent/JPS62134751A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To send and receive easily and also at a low cost the up-and-down on-line information to and from a control object, by constituting the titled processor of plural computers, and an information input/output device for sending and receiving the on-line information to and from the control object, and a shared memory device for sending and receiving directly the information which is held in common among the computers, to and from the information input/output device. CONSTITUTION:An information input/output device 3 writes up-on-line information from a control object, in the area concerned on a shared memory device 1 in order that information can be sent and received directly to and from a storage device. In such a case, the shared memory device 1 interlocks a fact that computers 2a-2n executes an access to the same area as the previous area, and protects the information concerned. Accordingly, when the up-on-line information is required, the computers 2a-2n can obtain easily the same up-on-line information by only reading out the area concerned on the shared memory device 1. Also, as for down-on-line information to the control object, by only writing the area concerned of the shared memory device 1 by each computer 2a-2n, the information input/output device 3 reads out the information on the shared memory device 1 and sends out the information to the control object.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は共有メモリー装置を備えた情報処理装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing device equipped with a shared memory device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

複数の計算機が制御対象との、1ニリ、トリオンライン
情報を授受する場合、従来は計算機のt記憶装置と外部
の情報入出力装置が直接情報交換していた。もCっで、
1個(nは計算機台数)の計算機が制御対象との1−リ
、トリオンラインl)’f+μの授受を行うには、【1
個の計算機と情報人出8ν置との間にn:1の分岐装置
を介したり、n個の情報人出装置を設ける必要があった
。そのため、システム構成が複雑になり、高価となって
いた。即ち、共有メモリー装置は各計算機で共有する情
報を配置しているが、直接情報入出力装置とインタフェ
ースしていない為、各計算機は情報の取込み、取出しの
負荷が定常的に必要であった。また、共有メモリー装置
及び分岐装置がシステム共通部である為、システム構成
が複雑となっている。
When a plurality of computers exchange one- or three-line information with a controlled object, conventionally, the computer's t-storage device and an external information input/output device directly exchange information. It's also C,
In order for one computer (n is the number of computers) to exchange 1-re, tri-line l)'f+μ with the controlled object, [1
It was necessary to use an n:1 branching device between each computer and the 8v information source, or to provide n information source devices. As a result, the system configuration has become complicated and expensive. That is, the shared memory device stores information that is shared by each computer, but because it does not directly interface with the information input/output device, each computer is constantly required to load and retrieve information. Furthermore, since the shared memory device and the branching device are common parts of the system, the system configuration is complicated.

〔発明の目的〕[Purpose of the invention]

本発明は情報入出力装置と上り、下りオンライン情報を
直接授受を可能と共有メモリー装置を装置を備え、複数
の計算機が簡便にがっ安価に制御対象との」ニリ、下り
オンライン情報の授受を可能とする情報処理装置を提供
する事を目的とする。
The present invention is equipped with an information input/output device and a shared memory device that can directly exchange upstream and downstream online information, allowing multiple computers to easily and inexpensively exchange downstream online information with the control target. The purpose is to provide an information processing device that enables

〔発明の概要〕[Summary of the invention]

本発明は共有メモリー装置に情報入出力装置を直接接続
し、これにより共有メモリー装置が計算機と情報入出力
装置とインタフェースする機能を持ち、共有メモリー装
置が情報入出力装置と制御対象との上り、下りオナライ
ン情報の授受を行い、さらに、オンライン情報の矛盾が
生じないようにする為共有メモリー装置が情報入出力装
置と情報の授受を行っている間、共有メモリー装置が計
算機との情報と同一番地の情報の授受を鎖錠し、共有メ
モリー装置情報を保護する情報処理装置である。
The present invention connects an information input/output device directly to a shared memory device, whereby the shared memory device has a function of interfacing with a computer and the information input/output device, and the shared memory device has the ability to interface between the information input/output device and the controlled object. While the shared memory device is exchanging information with the information input/output device, in order to exchange downstream online information and to avoid conflicts with online information, the shared memory device is located at the same address as the information with the computer. This is an information processing device that locks the exchange of information between devices and protects shared memory device information.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1図に示す。 An embodiment of the present invention is shown in FIG.

1は共有メモリー装置、3は情報入出力装置、28〜2
nは計算機を示す。共有メモリー装置1は各計算機28
〜2nに接続され複合系計算機システムを構成し、更に
情報入出力装置3とも接続する。
1 is a shared memory device, 3 is an information input/output device, 28-2
n indicates a computer. The shared memory device 1 is connected to each computer 28
2n to form a composite computer system, and further connected to the information input/output device 3.

先づ、上りオンライン情報の計算機への入力について説
明する。
First, inputting upstream online information into the computer will be explained.

情報入出力装置3は記憶装置と直接情報の授受を行う事
を可能とする為、制御対象からの上りオンライン情報を
共有メモリー装置1の上の該当する領域に書き込む。こ
の時、共有メモリー装置1は計算fi2a〜2nが先の
領域と同一領域をアクセスする事をインターロックし、
該当する情報を保護する。従って、計算機28〜2nは
情報入出力装置3がどの領域に対して情報を書込んだり
、呼出したりしているのかを膚:識せずに上りオンライ
ン情報が必要な時に共有メモリー装置1上の該当する領
域を読み出すだけで、各計算機は、同−上りオンライン
情報を容易に得る事が出来る。
The information input/output device 3 writes upstream online information from the controlled object to the corresponding area on the shared memory device 1 so that it can directly exchange information with the storage device. At this time, the shared memory device 1 interlocks the calculation fi2a to fi2n from accessing the same area as the previous area,
Protect applicable information. Therefore, the computers 28 to 2n do not know to which area the information input/output device 3 is writing or calling information, and when online information is needed, the computers 28 to 2n can access the shared memory device 1 By simply reading out the relevant area, each computer can easily obtain the same upstream online information.

次に、下りオンライン情報の外部への出力について説明
する。例えば、制御対象への下りオンライン情報は各計
算機2a〜2nが共有メモリー装置1の該当する領域に
書込むだけで、情報入出力装置3が共有メモリー装置1
上の情報を読み出し制御対象へ情報を送出する。
Next, outputting of downlink online information to the outside will be explained. For example, each computer 2a to 2n simply writes down online information to the controlled object in the corresponding area of the shared memory device 1, and the information input/output device 3
Read the above information and send the information to the controlled object.

以上説明した様にこの実施例によれば各計算機2a〜2
nが必要な時に共有メモリー装置1と上り、下りオンラ
イン情報の授受を行えば良い。従って、各計算機の上り
5.下りオンライン情報の取込み、取出しによるベース
負荷が低減できる。その他に。
As explained above, according to this embodiment, each of the computers 2a to 2
When n is necessary, uplink and downlink online information can be exchanged with the shared memory device 1. Therefore, each computer's upstream 5. The base load due to the import and retrieval of downstream online information can be reduced. Other.

各計算機は共有メモリー装置1と制御対象との上り、下
りオンライン情報の授受を行うだけで良い。
Each computer only needs to exchange upstream and downstream online information between the shared memory device 1 and the controlled object.

このため、従来のシステム構成に比し、各計算機28〜
2nは上り、下りオンライン情報の授受において共有メ
モリー装置1だけを対象にすれば良いので複雑な処理を
実施する必要がなく、システム構成が簡素化でき、かつ
安価に製作できる。
Therefore, compared to the conventional system configuration, each computer 28 to
2n needs only the shared memory device 1 to be used for sending and receiving upstream and downstream online information, so there is no need to perform complicated processing, and the system configuration can be simplified and manufactured at low cost.

尚5共有メモリー装置1はシステムの共通部である為、
機器を二重化構成として信頼性を向上させることも可能
である。
Note that 5. Since the shared memory device 1 is a common part of the system,
It is also possible to improve reliability by configuring the equipment in a redundant configuration.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明の共有メモリー装置を採用すれば各
計算機が制御対象との上り、下りオンライン情報を授受
する為に、従来のように分岐装置や切替装置を持ち、複
雑な構成とする必要がなくシステムが簡素化かつ安価に
できる。また、各計算機が扱う上り、下りオンライン情
報が共有メモリー装置上に一元管理される為、当該情報
を扱う計算機の台数が増加した場合、その効果は著しい
As described above, if the shared memory device of the present invention is adopted, each computer will need to have a branching device or a switching device and have a complicated configuration as in the past, in order to exchange upstream and downstream online information with the control target. This makes the system simpler and cheaper. Furthermore, since the uplink and downlink online information handled by each computer is centrally managed on a shared memory device, the effect is significant when the number of computers handling the information increases.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す情報処理装置の構成図
である。 1・・・共有メモリー装置 2a 、 2n・・・計算
機3・・・情報入出力装置  4・・・分岐装置5・・
・制御対象 代理人 弁理士 則 近 憲 佑 同  三俣弘文
FIG. 1 is a configuration diagram of an information processing apparatus showing an embodiment of the present invention. 1... Shared memory device 2a, 2n... Computer 3... Information input/output device 4... Branching device 5...
・Controlled agent Patent attorney Nori Chika Yudo Hirofumi Mitsumata

Claims (1)

【特許請求の範囲】[Claims] 複数の計算機と、制御対象とのオンライン情報を授受す
る情報入出力装置と、前記計算機の間で共有する情報を
前記情報入出力装置と直接授受することを可能とする共
有メモリー装置とからなる情報処理装置。
Information consisting of a plurality of computers, an information input/output device that exchanges online information with a controlled object, and a shared memory device that allows information shared between the computers to be directly exchanged with the information input/output device. Processing equipment.
JP27495185A 1985-12-09 1985-12-09 Information processor Pending JPS62134751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27495185A JPS62134751A (en) 1985-12-09 1985-12-09 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27495185A JPS62134751A (en) 1985-12-09 1985-12-09 Information processor

Publications (1)

Publication Number Publication Date
JPS62134751A true JPS62134751A (en) 1987-06-17

Family

ID=17548829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27495185A Pending JPS62134751A (en) 1985-12-09 1985-12-09 Information processor

Country Status (1)

Country Link
JP (1) JPS62134751A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07129519A (en) * 1993-11-04 1995-05-19 Sharp Corp Dual cpu system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07129519A (en) * 1993-11-04 1995-05-19 Sharp Corp Dual cpu system

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