JPS60124733A - Microprogram control circuit - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a memory by storing concentratingly fixed data of each instruction to other storage circuit and reading the fixed data from other storage circuit through the added address added to control data as required. CONSTITUTION:Control data CDA and an added address FDA are read from a storage circuit by an address A of an address circuit 1. The added address FDA reads fixed data FD from a storage circuit 5. The control data CDA and the fixed data FD of the storage circuits 2, 5 are latched to a register 3 as an instruction INS by a latch signal L. The instruction INS of the register 3 is inputted to an operation circuit 14 and executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprogram control circuit that controls reading of a memory storing a microprogram.

[Prior art]

The microprogram is composed of control data and fixed data added as necessary. This fixed data has a long number of bits but a small number of types. A conventional microprogram control circuit that stores such a microprogram is shown in FIG.

In FIG. 1, 1 is an address circuit that generates address A, and 2 is a storage circuit that stores a microprogram that is read out by address A of address circuit 1. In FIG. The memory configuration of the storage circuit 2 is such that a plurality of instructions INS are arranged as shown in FIG.

The memory structure of the storage circuit 2 may be as shown in FIG. 2 (bl). In this case, each instruction INS consists of control data CDI, CD2 and fixed data FD.

In the first diagram, a register 4 loaded with an instruction INS read out from the storage circuit 2 is an arithmetic circuit that executes arithmetic processing according to the instruction INS of the register 3.

To explain the operation, the address A of the address circuit 1 is input to the memory circuit 2, one instruction INS is read out, and this is loaded into the register 3. Since the instruction INS of the register 3 is input to the arithmetic circuit 4, the arithmetic circuit 4 executes arithmetic processing according to this instruction INS.

In the conventional microprogram control circuit, as shown in FIG. 2 (al.
As shown in Figure 2(b), since a control data field and a fixed data field are given to all instructions, the memory usage efficiency is poor. If you use this, you will not be able to control the same field as this,
Similarly, it had the disadvantage of being inefficient.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the fixed data of each instruction is stored centrally in another storage circuit, and when the fixed data is required, it is added to the control data. By reading fixed data from other memory circuits using the additional address specified,
An object of the present invention is to provide a microprogram control circuit that can improve memory utilization efficiency.

[Embodiments of the invention]

In FIG. 3, the same reference numerals as in FIG. 1 indicate the same or equivalent parts, and -5 is a storage circuit that stores fixed data FD of each instruction ID. FIG. 4(a) is a diagram showing the memory configuration of the storage circuit 2, and FIG. 4(b) is a diagram showing the memory configuration of the storage circuit 5.

Next, the operation will be explained. Control data CD and additional address FDA are read from memory circuit 2 from address AK of address circuit 1. Additional address FDA reads fixed data FD from memory circuit 5. Memory circuits 2 and 5
0 control data CD and fixed data FD are 1 in register 3.
It is latched as one instruction INS by the latch signal. Register 3 instruction IN
S is input to the arithmetic circuit 4 and executed.

Although the memory circuit 5 handles only fixed data, the same effect can be obtained even if the branch address of the microprogram is referred to using such an address.

〔Effect of the invention〕

As described above, according to the present invention, the storage capacity of the memory can be reduced without reducing the efficiency of the microprogram.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional microprogram control circuit, FIG. 2 is a data format diagram used by the microprogram control circuit of FIG. 1, and FIG. 3 is a microprogram control circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing the format of data used by the microprogram control circuit of FIG. 1... Address circuit, 2, 5... Memory circuit, 3...
・Register, 4... Arithmetic circuit. In the figures, the same reference numerals indicate the same or equivalent parts 0 Patent applicant Mitsubishi Electric Corporation Agent Patent attorney 1) Hiroaki Sawa, 1, 1 Agent Patent attorney Nobuo Ishibashi 1, 1□ j Figure 1 Figure 3 Figure 2 Figure 4 +al

Claims (1)

[Claims] a first memory circuit that stores control data and additional addresses of each instruction forming a microprogram; a second memory circuit that stores fixed data read out by the additional addresses of the first memory circuit; 2
A microprogram control circuit comprising an instruction register that holds microinstructions consisting of control data and fixed data read from a storage circuit, and an arithmetic circuit that executes arithmetic processing according to the microinstructions in the instruction register.