JPH04211854A - Computer device - Google Patents

Abstract

PURPOSE:To prevent the processing of a microcomputer from being interrupted even during a timing period in which a peripheral circuit accesses directly the memory of the microcomputer in the microcomputer. CONSTITUTION:A computer device is provided with a central processing unit 1, an instruction memory 7, a data memory 2, and the peripheral circuit 3, and an instruction bus 6 connected to said instruction memory 7 and a first data bus 4 are connected to the central processing unit 1, and the data memory 2 is connected to the first data bus 4 and a second data bus 5, and the second data bus 5 is connected to the peripheral circuit 3, and data transfer between the peripheral circuit 3 and the data memory 2 is executed through the second data bus 5 during a period in which the central processing unit 2 does not access the data memory 2 in the instruction cycle of the central processing unit 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a central processing unit (hereinafter referred to as CP).
The present invention relates to a computer device having a memory (denoted as U), a memory, and its peripheral devices, and particularly relates to a computer device in which data and memory of a CPU can be independently accessed from a peripheral device during execution of an instruction by a central processing unit.

0002

[Prior Art] In a conventional computer device that integrates a CPU, memory, and peripheral devices, one data
bus to CPU 21, data memory 22, peripheral device 23
Share with. The data bus 24 is used when the CPU 21 accesses the data memory 22, when the CPU 21 accesses the peripheral device 23, and when the peripheral device 23 accesses the data memory 22. CPU21
accesses the data memory 22 and the CPU 21
When accessing the peripheral device 23, it corresponds to an instruction from the CPU 21. However, the peripheral device 23
When accessing the data memory 2, there are cases in which the data in the data memory 22 is accessed in response to instructions from the CPU 21, and cases in which the peripheral device 23 requires the data in the data memory 22 independently of the instructions from the CPU 21 for its operation. The latter is called a direct memory access operation (hereinafter referred to as a DMA operation).

DMA operation is used when a large amount of data needs to be transferred from the data memory 22 to the peripheral device 23 in a short time than the amount of data transferred from the data memory 22 to the peripheral device 23 by one command from the CPU 21. used for.

[0004] Usually, the CPU 21 is an 8-bit CPU.
If it is U, one instruction will move data from data memory 22 to peripheral device 2.
The amount of data that can be transferred to No. 3 is about 8 bits. For example, if the peripheral device 23 requires 32 bits during the execution time of one instruction by the CPU 21, the data memory 22 is directly transferred to the peripheral device 23 without going through the data memory access operation of the CPU 21.
This is because it is better to access the peripheral device 23 four times during one instruction of the CPU 21 at its own timing.

When performing a DMA operation, the operation of the CPU 21 is stopped so that the data controlled by the CPU 21 and the data controlled by the peripheral device 23 do not interfere with each other on the data bus 24, and the data bus 24 is connected to the peripheral device. Released on the 23rd. The peripheral device 23 requests the CPU 21 for DMA operation 25
The CPU 21 puts the DMA operation into a state where it can execute the data bus, releases the data bus 24, sends a DMA enable signal 26 to the peripheral device 23, and stops the operation until a DMA operation cancel signal 27 is issued from the peripheral device 23.

[0006]

[Problems to be Solved by the Invention] In this way, in the DMA operation, the data bus 24 in FIG. decreases. Figure 3 shows the situation.

A in FIG. 3 shows the CPU when there is no DMA operation.
This is the operation timing. B in Figure 3 shows that the DMA operation is CP.
This is a case where every other instruction of U is executed. For example, CPU
If the instruction execution time is 2μ seconds and the time required for DMA operation is also 2μ seconds, then in Figure 3A, the CPU instruction execution time is 2μ seconds, but in Figure 3B, the CPU instruction execution time is It ends up being 4 microseconds.

Furthermore, in the above example, the DMA operation time is CP
Although the time taken to execute one instruction is the same as that of U, it may take even longer depending on the processing content of the peripheral device. In other words, since the data bus used for CPU data processing and the data bus used by peripheral devices are the same,
This is because the DMA operation period increases if data several times the bit width of the data bus is transferred to the peripheral device.

Furthermore, if the processing content of the peripheral device is asynchronous with the CPU operation, even if a DMA operation request is issued from the peripheral device, depending on the CPU operation status, the CPU
A DMA operation permission signal is not sent from the peripheral device, and the operation of the peripheral device stops during that time.

[0010] When DMA operations are used, there are cases in which both the processing speed of the CPU and the processing speed of peripheral devices become slow.

[0011] The faster the execution processing speed that a device external to the computer system requires of the computer system, the more disadvantageous it becomes. Furthermore, in order to increase the execution processing speed with such a configuration, it is necessary to increase the processing speed of the CPU itself. If the CPU is an integrated circuit, the size of the internal transistors must be increased, leading to an enlargement of the integrated circuit and further resulting in increased power consumption.

0012

A computer device of the present invention has a central processing unit, an instruction memory, a data memory, and a peripheral circuit, and the central processing unit has an instruction bus connected to the instruction memory, and a first A data bus is connected, and the data memory is connected to a first data bus and a second data bus.
a second data bus is connected to the peripheral circuit, and a second data bus is connected to the peripheral circuit, and data transfer between the peripheral circuit and the data memory transfers the data memory to the central processing unit during an instruction cycle of the central processing unit. It is characterized in that it is performed via the second data bus during periods when the data bus is not being accessed.

The period during the instruction cycle of the central processing unit when the data memory is not accessed by the central processing unit is a dedicated period during the instruction cycle.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The CPU 1 receives instructions from the instruction memory 7 via the instruction bus 8 and accesses the data memory 2 or the peripheral device 3 via the data bus 4 in accordance with the instructions. Data transfer between peripheral device 3 and data memory 2 takes place via a dedicated data bus 5. The data memory 2 has input/output devices for a data bus 4 and an input/output device for a dedicated data bus 5. Furthermore, the data bit widths on the dedicated data bus 5 and data bus 4 are different, and the data bit width on the dedicated data bus 5 is larger.

FIG. 5 shows the operating status of the CPU 1 during one instruction. One instruction of the CPU 1 is divided into four timings, and the data memory 2 can only be accessed once at each timing. During timing 51, CPU 1 does not access data memory 2, and at timings 52, 53,
At 54, CPU 1 accesses data memory 2.

For example, assume that the data bus 4 is 8 bits, the dedicated data bus 5 is 32 bits, and one instruction cycle of the CPU 1 is 2 μsec.

Now, while the CPU 1 is operating, the peripheral device 3 is
It operates asynchronously with PU1. It is assumed that the peripheral device 3 requires 32 bits of data every 2 microseconds due to its operation. Peripheral device 3 accesses data memory 2 via dedicated data bus 5 during timing 52 during the CPU 1 instruction cycle. Unlike the data bus 4, the dedicated data bus 5 has a bit width of 32 bits, so 32 bits of data can be transferred from the data memory 2 at one time, and at timing 51, it is always connected to peripheral devices while the CPU 1 is operating. 3 and the data memory 2, the data memory 2 only needs to be accessed once. In addition, peripheral device 3 may take the trouble to store data memory 2.
There is no need to obtain permission from the CPU 1 when transferring data from the CPU 1.

FIG. 4 shows a second embodiment of the invention. The difference from the previous embodiment is that the data memory 42 has only one data input/output device, and it is determined whether either the dedicated data bus 45 or the data bus 44 is connected to the input/output device of the data memory 42. Bus switching device 4
8. The data bit width of the input/output devices of data memory 42 is the same as the bit width of the dedicated data bus. The bus switching device 48 is controlled by a switching control signal 49, when the switching control signal 49 is high.
When the level goes high, the data input/output device of the data memory 42 is connected to the dedicated data bus 45, and when the level goes low, it is connected to the data bus 44. FIG. 5C shows the timing of the switching control signal 48.

The switching control signal 49 goes high at timing 51 and goes low at timings 52, 53, and 54, so the other operations are the same as in the previous embodiment.

FIG. 6 shows a third embodiment of the present invention. In this embodiment, the dedicated data bus 65 is connected to the data memory 62 by a bus switching device 68 during execution of an instruction that does not access the data memory 62, such as a branch instruction such as a jump instruction. The switching signal 69 is a data
It is output when the instruction does not access the memory 65. The rest is the same as the second embodiment.

Furthermore, in the present invention, when an instruction that does not access data memory, such as a branch instruction, data memory is directly accessed from a peripheral device, and during the instruction period that accesses data memory, the first embodiment is used. The peripheral device accesses the data memory using a dedicated period of . Therefore, the processing speed of the peripheral device can be further increased because the peripheral device can access the data memory during the dedicated period and the instruction period when the data memory is not accessed.

[0022]

Effects of the Invention As described above, by performing data transfer between the data memory and the peripheral device via the dedicated data bus instead of the data bus during the period when the CPU does not access the data memory during one instruction of the CPU, It is possible to transfer large amounts of data from data memory to peripheral devices without reducing the execution speed of the CPU or the processing speed of peripheral devices, which prevents the CPU from expanding and consuming large amounts of power. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of the prior art.

FIG. 3 is a timing diagram of the prior art.

FIG. 4 is a block diagram of a second embodiment of the invention.

FIG. 5 is a timing explanatory diagram of the embodiment of FIG. 1 and the second embodiment.

FIG. 6 is a block diagram of a third embodiment of the invention.

Claims (4)

[Claims] Claims: 1. A computer device having a central processing unit, an instruction memory, a data memory, and a peripheral circuit, wherein the central processing unit includes an instruction bus connected to the instruction memory and a first data・The data memory is connected to the first data bus and the second data bus.
a second data bus is connected to the peripheral circuit, and a second data bus is connected to the peripheral circuit, and data transfer between the peripheral circuit and the data memory transfers the data memory to the central processing unit during an instruction cycle of the central processing unit. A computer device that performs operations via a second data bus during periods when the computer is not accessing the data bus. 2. In the computer device according to claim 1, the period during which the central processing unit does not access the data memory during the instruction cycle of the central processing unit is a period exclusively provided during the instruction cycle. A computer device characterized by: 3. In the computer device according to claim 1, the period during which the central processing unit does not access the data memory during the instruction cycle of the central processing unit is the period during which the central processing unit does not access the data memory. A computer device characterized by: 4. In the computer device according to claim 1, the period during which the central processing unit does not access the data memory during an instruction cycle of the central processing unit is defined as the period during which the central processing unit does not access the data memory. and a dedicated period during an instruction cycle for accessing the data memory.