JPH0713920A - Dma transferring method - Google Patents

Abstract

PURPOSE:To reduce the load on a main processor, to improve the processing efficiency of an arithmetic processing unit, and to simplify a circuit constitution. CONSTITUTION:This system is equipped with a main processor 101A which executes the main functional processing of the arithmetic processing unit, sub- processor 101B which operates as a DMA controller, and dual port memory 111 provided between those processors 101A and 101B, in which the execution program of the sub-processor 101B is stored. Then, when a DMA transfer request is generated, the main processor 101A stores DMA transfer information such as data length and an address in the dual port memory 111, and the sub- processor 101B executes DMA transfer between the dual port memory 111 and an outside memory board 30 through a system bus 20 by using the execution program and the DMA transfer information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer method for transferring data (Direct Memory Access) between a memory connected to a microprocessor and an external memory via a system bus.

[0002]

2. Description of the Related Art In the following, a microprocessor is built in and connected via a system bus of a device to a main board for the purpose of executing the main functions of the arithmetic processing device, such as calculation, communication and input / output processing. A conventional DMA transfer technique with an external memory board will be described. FIG. 2 shows an arithmetic processing unit having a relatively simple structure to which the first conventional technique is applied. In the figure, 10 'is a main board, 20 is a system bus, and 30 is an external memory board. In 10 ', 101 is a CPU,
102 is a RAM, 103 is an interface unit, 104
Is a control circuit, and 105 is an internal bus.

To explain the operation, the CPU 101
The main processing of the main board 10 'is performed together with the control circuit 104 that performs calculation, communication, input / output processing, etc.
02 and the external memory board 30 are processed according to the DMA transfer. When performing DMA transfer of data from the RAM 102 to the external memory board 30, the CPU 101 first reads R
Data is read from the AM 102, and the data is read from the internal bus 105, the interface unit 103, and the system bus 2.
Write to the external memory board (internal memory) 30 via 0.

According to this method, in addition to the main function processing of the main board 10 'by one CPU 101, the DMA transfer with the external memory board 30 must be controlled. In addition, generally, the time required for external access via the system bus 20 is longer than the time required for memory access in the main board 10 ′.
One CPU 10 for DMA transfer processing including external access
Execution by 1 increases the load on the CPU 101 and reduces the original processing efficiency.

As a second conventional technique for solving the above problem, a DMA transfer method by the applicant of the present invention, which is described in Japanese Patent Laid-Open No. 3-216753, is known.
FIG. 3 shows an outline of this prior art. In the figure,
10 "is a main board, and this main board 10"
CPU 101, RAM 102, interface unit 1
03, control circuit 104, DMAC (DMA controller) control circuit 105, first DMAC 106A, second DMAC 106B, data transfer buffer 107, first
Internal bus 108A and second internal bus 108B. The configuration other than the main board 10 ″ is the same as that in FIG.

That is, in this example, the main board 10 ''
DMACs 106A and 106B are provided on the two internal buses 108A and 108B, respectively.
A data transfer buffer 107 is provided between A and 108B.

In this conventional technique, the first internal bus 108 is used.
The first DMAC 106A on A is transferred from the CPU 101 to D
A transfer activation request from the RAM 102 to the transfer buffer 107 is received via the MAC control circuit 105. As a result, the DMAC 106A transfers data from the RAM 102 to the transfer buffer 107 via the internal bus 108A. Then, the second DMA on the second internal bus 108B.
C106B is from the CPU 101 to the DMAC control circuit 10
A transfer activation request from the transfer buffer 107 to the external memory board 30 is received via the route 5.

The DMAC 106B has a transfer buffer 10
The data once stored in 7 is transferred via the internal bus 108B, the interface unit 103, and the system bus 20 and written in the external memory board 30. The main function processing of the main board 10 ″ is performed by the CPU 101.
I am going with 04.

[0009]

According to the second conventional technique, the CPU 101 is not restricted in its operation during the data transfer period from the transfer buffer 107 to the external memory board 30, and therefore the first conventional technique. CPU 101 compared to
The processing efficiency of is improved. However, in the second conventional technique, since the CPU 101 needs to control the two DMACs 106A and 106B via the DMAC control circuit 105, there is a problem that the circuit configuration becomes complicated and the circuit scale increases. Further, when data conversion such as byte swap is performed, it is necessary to execute processing by the CPU 101 or add a circuit to the CPU 101.
The load of No. 1 increases and the circuit configuration becomes more complicated, which is a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the load on the processor that performs the main function processing and to simplify the circuit configuration. To provide a transfer method.

[0011]

In order to achieve the above object, the present invention is provided between a main processor that executes main function processing of an arithmetic processing unit, a sub processor that operates as a DMA controller, and these processors. And a shared memory in which an execution program of the sub-processor is stored. When a DMA transfer request is generated, the main processor stores the DMA transfer information in the shared memory, and the sub-processor stores the execution program and the DM.
D between shared memory and external memory using A transfer information
MA transfer is executed.

[0012]

In the present invention, when the device is initialized, the DMA
The main processor stores the program of the sub-processor as a controller in the shared memory and releases the reset of the sub-processor. The main processor performs the main function processing such as the original operation of the device and communication, and D
When there is an MA transfer request, various information regarding the DMA transfer (data length, address, transfer direction such as read or write, etc.) is stored in the shared memory. After that, the sub processor causes the program in the shared memory to perform the DMA transfer between the shared memory and the external memory using the DMA transfer information.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an arithmetic processing unit to which this embodiment is applied. The same components as those in FIGS. 2 and 3 are designated by the same reference numerals. In this embodiment, in the main board 10, a main processor (main CPU) 101A is connected to a first internal bus 108A, and a sub processor (sub CPU) 101B that functions as a DMAC is connected to a second internal bus 108B. Along with
A dual port RAM (DPRAM) 111 as a shared memory is connected between the internal buses 108A and 108B.

A first control circuit 104A and a program ROM 110 are connected to the first internal bus 108A, and a second control circuit 104B is provided between the main processor 101A and the sub processor 101B. In addition,
Main processor 101A and second control circuit 104B
A reset circuit 109 is connected to.

In the above configuration, the main processor 10
The 1A and the first control circuit 104A perform main function processing such as arithmetic, communication, and input / output processing of the main board 10, and the sub processor 101B mainly executes DMA transfer between the dual port RAM 111 and the external memory board 30. Let The ROM 110 also includes the main processor 101.
In addition to the execution program of A, a program necessary for the sub processor 101B to execute the DMA function is stored.

Next, the operation of this embodiment will be described. First, at the time of initialization of the device, the reset signal output from the reset circuit 109 is input to the main processor 101A to reset it, and at the same time, the sub processor 10A is reset.
The reset signal continues to be input to 1B via the second control circuit 104B. Reset main processor 1
01A is a sub processor 1 stored in the ROM 110
The program 01B is loaded into the dual port RAM 111, and after the loading is completed, the reset of the sub processor 101B is released via the second control circuit 104B. As a result, the sub processor 101B causes the DMAC (DMA
It becomes possible to operate as a controller).

The main processor 101A executes the main function processing of the main board 10 together with the first control circuit 104A. When a DMA transfer request is issued, the data length and address to be transferred to the dual port RAM 111,
Stores DMA transfer information such as the direction (transfer direction such as read or write), and write data when write is designated (here, D including transfer data is also included.
MA transfer information). In other words, dual port RAM
111 also serves as a buffer for data transfer.

Sub-processor 101B as DMAC
Reads the DMA transfer information from the dual port RAM 111, and performs read or write with the external memory board 30 via the second internal bus 108B, the interface unit 103, and the system bus 20. Memory board 3
A DMA transfer with 0 is executed.

As described above, in this embodiment, the sub-processor 101B as the DMAC exclusively performs the DMA transfer using the program and the DMA transfer information in the dual port RAM 111, and the main processor 101A.
Performs reset control of the sub processor 101B, program loading to the dual port RAM 111, storage of DMA transfer information, etc., and main function processing may be executed. Therefore, the load on the main processor 101A is higher than that of the second conventional technique. There is no concern that the original processing efficiency of the arithmetic processing unit will be lowered by the DMA transfer.

[0020]

As described above, according to the present invention, by operating the sub-processor as a DMAC, external access by the main processor becomes unnecessary, the load on the main processor is reduced, and the processing efficiency of the apparatus is improved. It Further, since the sub-processor functioning as the DMAC can be made to perform data conversion such as byte swap, it is possible to further reduce the load on the main processor. Furthermore, by storing the execution program of the sub-processor in the shared memory, the sub-processor does not need to have its own memory and realizes efficient DMA transfer with a simpler and smaller circuit configuration than the second conventional technique. be able to.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an arithmetic processing unit to which an embodiment of the present invention is applied.

FIG. 2 is a schematic configuration diagram of an arithmetic processing device to which a first conventional technique is applied.

FIG. 3 is a schematic configuration diagram of an arithmetic processing unit to which a second conventional technique is applied.

[Explanation of symbols]

 10 main board 20 system bus 30 external memory board 101A main processor 101B sub processor 103 interface section 104A first control circuit 104B second control circuit 108A first internal bus 108B second internal bus 109 reset circuit 110 ROM 111 dual Port RAM (DP RAM)

Claims (1)

[Claims] 1. A main processor that executes main function processing of an arithmetic processing unit, a sub-processor that operates as a DMA controller, and a shared memory that is provided between these processors and that stores an execution program of the sub-processor. , When the DMA transfer request is generated, the main processor stores the DMA transfer information in the shared memory, and the sub processor causes the execution program and the DM to be executed.
D between shared memory and external memory using A transfer information
A DMA transfer method characterized by executing MA transfer.