JP2001159905A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a procedure for accelerating an access from a CPU module to an I/O module with respect to a programmable controller connecting the CPU module to the I/O module through an I/O bus. SOLUTION: The programmable controller is provided with the CPU module 10 comprising of a sequence instruction processing processor 12 for executing at least sequence instruction processing, an MPU 11 for controlling an access to the I/O bus 30 in accordance with an instruction from the processor 12 and a bus interface 19 for accessing the I/O bus 30 in accordance with an instruction from the MPU 11 and the I/O module 20 capable of accessing the CPU module 10 through the I/O bus 30. The bus interface 19 is provided with a DMAC 18 capable of accessing the I/O bus 30 by a direct instruction from the processor 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller, and more particularly, to a programmable controller (CPU) module for a programmable controller, and more particularly to a programmable controller CPU module for increasing the speed of a sequence instruction processor accompanied by access to an IO module.

[0002]

2. Description of the Related Art As shown in FIG. 2, a programmable controller according to the prior art is a CPU (Central Process) for performing operations such as a sequence program.
an IO unit 20 that controls an external interface, and an IO bus 30 that connects the CPU module 10 and the IO module 20 via a bus line.

[0003] The CPU module 10 includes an MPU (Micro Processes) for performing IO refresh and peripheral processing.
Sor Unit) 11, a sequence instruction processor 12 for performing sequence instruction processing, a memory 13 for storing sequence programs and data, and a buffer 14 for separating the MPU 11 and the sequence instruction processor 12 so that they can operate in parallel. , MPU11 is I
When accessing the O module 20, the MPU bus 15
And a bus interface circuit 16 for converting the data of the I / O bus into the IO bus 30. Of these, MPU1
1, bus interface circuit 16 and buffer 14 are M
The buffer 14, the sequence instruction processor 12, and the memory 13 are connected via a PU bus 15.

In such a configuration, when a read command, a write command, or a direct refresh command is processed in a sequence program, the following operation is performed.

First, the sequence instruction processor 12
Fetches various instructions from the memory 13 via the SPU bus 17, asserts the IRQ signal,
11 is interrupted. When an interrupt occurs, the MPU 11 sends the MPU bus 15, the buffer 14, the SPU bus 1
7 to access the memory 13, and the instruction code, I
O module 20 address, memory 13 address,
Reads information necessary for instruction processing such as the number of transfers. Furthermore,
The MPU 11 performs data transfer between the memory 13 and the IO module 20. When this data transfer is completed, the completion is notified to the sequence instruction processor 12, and a series of instruction processing is completed.

[0006]

However, the above-mentioned sequence instruction processor in the prior art is not compatible with the I / O processor.
When trying to access the O module, it is necessary to interrupt the MPU and have the MPU perform access to the IO module on behalf of the MPU. That is, in the sequence program, the processing time of the read command, the write command, and the direct refresh command has been long. This has also increased the processing load of the MPU.

Therefore, the sequence instruction processor has a problem that needs to be solved to speed up access to the IO module.

[0008]

In order to solve the above-mentioned problems, a programmable controller according to the present invention has the following configuration.

(1) A sequence instruction processor for performing at least sequence instruction processing, a microprocessor unit (MPU) for controlling access to the IO bus according to instructions from the sequence instruction processor, and an IO bus according to instructions from the MPU. A CPU module comprising a bus interface to be accessed; and an IO module capable of accessing the CPU module via the IO bus. The bus interface is provided by a direct instruction from the sequence instruction processing processor. A programmable controller comprising a direct memory access controller (DMAC) capable of accessing the IO bus. (2) The programmable controller according to (1), wherein the DMAC has a function of loading parameters such as an address of an I / O module to be accessed, a memory address, a transfer mode, and a transfer number from a predetermined memory. (3) The DMAC performs direct memory access (D
MA) The programmable controller according to (1) or (2), having a function of storing a transfer status in a predetermined memory. (4) The programmable controller according to (1), (2) or (3), wherein the DMAC includes a plurality of channels.

[0010]

Next, an embodiment of a programmable controller according to the present invention will be described with reference to the drawings. The same components as those in the prior art will be described with the same reference numerals.

As shown in FIG. 1, the programmable controller according to the present invention comprises a CPU module 10 for performing operations of a sequence program and the like, and an IO module 20 for interfacing with the outside. The module 20 is connected via an IO bus 30.

The CPU module 10 includes an MPU 11 for performing IO refresh and peripheral processing, a sequence instruction processor 12 for performing sequence instruction processing, and a memory 13 for storing sequence programs and data.
A buffer 14 for separating the bus so that the MPU 11 and the sequence instruction processor 12 can operate in parallel; and a bus interface circuit 16 for converting the MPU bus 15 to the IO bus 30 when the MPU 11 accesses the IO module 20. And a DMAC (Direct Memory Access Controller; Direct Memory) capable of accessing the memory 13 and the IO module 20
Access Control 18). Of these, the bus interface circuit 16 and the DMAC 18 use the bus interface LSI (19).
Is configured. The sequence instruction processor 12, the memory 13, and the buffer 14 can be connected via the SPU bus 17.

When the processing of a read instruction, a write instruction, or a direct refresh instruction occurs in the sequence program having such a configuration, the sequence instruction processor 12 fetches these instructions from the memory 13 via the SPU bus 17. , DRQ signal is asserted, and DMA (Direct Memory) is sent to the DMAC 18.
y Access) request. When the MPU 11 releases the right to occupy the bus, the MPU 11 asserts a BACK signal,
This is notified to the DMAC 18. DMAC 18
It has a function of automatically loading parameters required for DMA transfer, and when it acquires the right to occupy the MPU bus 15, it accesses the memory 13 via the MPU bus 15, the buffer 14, and the SPU bus 17 to execute instruction codes, IO Information necessary for DMA transfer, such as the address of the module 20, the address of the memory 13, the transfer mode, and the number of transfers is read.
Next, the DMAC 18 stores the memory 13 and the IO module 2
Data transfer during 0 is performed, and when the data transfer is completed,
This is notified to the sequence instruction processor 12, and the status of the DMA transfer is stored in the memory 13. In this way, the sequence instruction processing processor 12 uses the DMAC to access the IO bus 30.
Since the drive of the bus interface circuit 16 can be controlled directly via the MPU 11, the MPU 11
Therefore, it is not necessary to drive and control the IO bus 30 via the internal bus, and the IO module 20 can be accessed quickly by that amount.

Further, an interrupt to the MPU 11 is performed to
If the DMAC 18 is provided with a plurality of channels in order to drive and control the bus interface circuit 16 via the MAC 18, access to the IO module 20 can be promptly performed by interrupt processing or the like.

[0015]

As described above, the sequence instruction processing processor in the programmable controller according to the present invention uses the DMAC to execute the MPU.
This makes it possible to access the IO module without going through the interface, so that the access can be performed at high speed.

Further, in a sequence program, processing of a read instruction, a write instruction, and a direct refresh instruction can be performed at a high speed, and there is an effect that a processing load of an MPU can be reduced.

Further, by providing the DMAC with a plurality of channels, it is possible to promptly cope with a request for access to the IO module due to interrupt processing during sequence command processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a programmable controller according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a programmable controller according to the related art.

[Explanation of symbols]

 Reference Signs List 10 CPU module 11 MPU 12 Sequence instruction processor 13 Memory 14 Buffer 15 MPU bus 16 Bus interface circuit 17 SPU bus 18 DMAC 19 Bus interface LSI 20 IO module 30 IO bus

Claims (4)

[Claims] 1. A sequence instruction processor for performing at least sequence instruction processing, a microprocessor unit (MPU) for controlling access to an IO bus in accordance with an instruction from the sequence instruction processor, and an MPU
A CPU module comprising a bus interface for accessing the IO bus in accordance with the instruction of the above, and an IO module capable of accessing the CPU module via the IO bus. The bus interface comprises the sequence instruction processing processor Memory controller (DM) that can access the IO bus by a direct instruction from
AC). 2. The programmable controller according to claim 1, wherein said DMAC has a function of loading parameters such as an address of an IO module to be accessed, a memory address, a transfer mode, and a transfer number from a predetermined memory. controller. 3. The programmable controller according to claim 1, wherein said DMAC has a function of storing a status of direct memory access (DMA) transfer in a predetermined memory. 4. The programmable controller according to claim 1, wherein said DMAC has a plurality of channels.