JP2003076550A - Data processor, semiconductor circuit and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor for simplifying access procedures from a control circuit to an external memory. SOLUTION: A DSP (digital signal processor) 20 of an LSI (large scale integrated circuit) 13 executes a boot program and downloads an execution program 10 by using a function of DMA- CNT (direct memory access controller) 21 in the process. Then the DSP 20 downloads and uses data 11 from the external memory 4 by using the function of the DMA- CNT 21 during execution of the execution program 10. The DSP 20 is controlled by a host CPU 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, a semiconductor circuit and a data processing system capable of simplifying access to programs and data.

[0002]

2. Description of the Related Art A CPU (Cen
tral Processing Unit) and DSP (Digital Signal Proc)
A control circuit (arithmetic circuit) such as an essor) downloads the execution program stored in a rewritable external memory such as SRAM or flash memory to the program memory in the control circuit during execution of the boot program. Further, the CPU or DSP described above inputs / outputs data to / from an external memory other than the external memory in which the execution program is stored during execution of the execution program.

[0003]

However, in the above-described conventional system, since the execution programs and data are stored in different external memories, the width of the data bus between the external memory and the control circuit and the number of connection terminals are different. However, there is a problem that the access procedure to the external memory in the control circuit becomes complicated.

The present invention has been made in view of the above-mentioned problems of the prior art, and can reduce the width of the data bus between the external memory and the control circuit and reduce the number of connection terminals, the semiconductor circuit and the data. The purpose is to provide a processing system. Further, the present invention provides a data processing device capable of simplifying an access procedure from a control circuit to an external memory,
An object is to provide a semiconductor circuit and a data processing system.

[0005]

In order to solve the above-mentioned problems of the prior art and achieve the above-mentioned object, a data processing apparatus according to the first invention comprises an external memory for storing an execution program and data. And a semiconductor circuit that executes the execution program, the semiconductor circuit including a program memory that stores a boot program, a data memory, and a transfer of the execution program from the external memory to the program memory. A memory control circuit for controlling and controlling data transfer between the external memory and the data memory, and boot processing based on the boot program read from the program memory, and in the boot processing, the external processing is performed. Instructing the memory control circuit to transfer the execution program from the memory to the program memory. And performs processing based on the execution program read out from the memory for the program,
And a control circuit for instructing the memory control circuit to transfer data between the external memory and the data memory during the process.

The operation of the data processor of the first invention is as follows. First, the control circuit reads the boot program from the program memory and performs boot processing based on the boot program. And the control circuit
In the boot process, the memory control circuit is instructed to transfer the execution program from the external memory to the program memory. Then, under the control of the memory control circuit, the execution program is transferred from the external memory to the program memory. And the control circuit
Processing is performed based on the execution program read from the program memory. The control circuit instructs the memory control circuit to transfer data between the external memory and the data memory during the process. Under the control of the memory control circuit, data transfer is performed between the external memory and the data memory.

In the data processor of the first invention, preferably, the control circuit stores program size data indicating the size of the execution program transferred from the external memory to the program memory. Received from an external controller, stores the program size data in a register, the memory control circuit, based on the program size data stored in the register,
The execution program is transferred from the external memory to the program memory.

In the data processor of the first invention, preferably, the control circuit transfers the execution program from the external memory to the program memory while the boot program is being executed. Instruct the control circuit.

Further, in the data processing apparatus of the first invention, preferably, the control circuit executes the execution program transferred from the external memory to the program memory from a control apparatus external to the data processing apparatus. The execution start vector address is received, the execution start vector address is stored in a register, and the memory control circuit stores the execution program in the program memory from the external memory based on the execution start vector address stored in the register. To transfer.

In the data processor of the first invention, preferably, the control circuit sets a program counter at an execution start vector address stored in the register to execute the execution program.

Further, in the data processor of the first invention, preferably, the control circuit outputs a data transfer request to the memory control circuit during execution of the execution program,
The memory control circuit transfers data between the external memory and the data memory based on the data transfer request.

The semiconductor circuit of the second invention controls the transfer of an execution program from a program memory for storing a boot program, a data memory, and an external memory to the external memory. A memory control circuit for controlling data transfer to and from the data memory, and boot processing based on the boot program read from the program memory, and in the boot processing, the external memory to the program memory. Instructing the memory control circuit to transfer the execution program, performing processing based on the execution program read from the program memory, and in the process of the processing, between the external memory and the data memory. Control circuit for instructing the memory control circuit to transfer the data

A data processing system according to a third aspect of the present invention has an external memory for storing an execution program and data, a semiconductor circuit for executing the execution program, and a control device for controlling the semiconductor circuit. The semiconductor circuit controls a program memory that stores a boot program, a data memory, and a transfer of the execution program from the external memory to the program memory,
A memory control circuit that controls data transfer between the external memory and the data memory, and boot processing is performed based on the boot program read from the program memory. Instructing the memory control circuit to transfer the execution program to the program memory, processing is performed based on the execution program read from the program memory, and in the process of the processing, the external memory and the data And a control circuit for instructing the memory control circuit to transfer data to and from the memory.

[0014]

DETAILED DESCRIPTION OF THE INVENTION A data processing system according to an embodiment of the present invention will be described below. FIG. 1 is an overall configuration diagram of a data processing system 1 of this embodiment. Figure 1
As shown in, the data processing system 1 has, for example, a host CPU 2, an LSI 3, and an external memory 4. As shown in FIG. 1, the host CPU 2 and the LSI (Large Scale)
The integrated circuit 3 is connected via a signal line 30 and a data bus 31. The LSI 3 and the external memory 4 are connected via a signal line 32, a data bus 33 and an address bus 34. Here, the host CPU 2 corresponds to the control device of the present invention, the LSI 3 corresponds to the semiconductor circuit of the present invention, and the external memory 4 corresponds to the external memory of the present invention.

Hereinafter, each component of the data processing system 1 will be described. [Host CPU 2] The host CPU 2 indicates, for example, program size data and execution start vector data of the execution program 10 that the LSI 3 reads from the external memory 4 to the data memory 44 via the data bus 33 via the signal line 30. The control signal is output to the LSI 3.

[LSI3] As shown in FIG.
Is a DSP 20 and a DMA_CNT (Direct Memory A
ccess CoNTroller) 21. Where DMA_C
NT21 corresponds to the memory control circuit of the present invention. Note that the LSI 3 may have a built-in video processing circuit, audio processing circuit, or the like in addition to the functions shown in FIG.

As shown in FIG. 2, the DSP 20 has, for example, a processor 41, a register group 42, a program memory 43, and a data memory 44. here,
The processor 41 corresponds to the control circuit of the present invention, the program memory 43 corresponds to the program memory of the present invention, and the data memory 44 corresponds to the data memory of the present invention.

The processor 41 operates based on a control signal input from the host CPU 2 via the signal line 30. Further, the processor 41 has a program memory 43.
The program memory 43 stored in advance is executed to perform boot processing. In addition, the processor 41 uses the data bus 33 to transfer data from the external memory 4 to the data memory 44.
The execution program 10 that has been read (downloaded) is executed to perform processing. In addition, the processor 41
A request such as a data transfer request is output to the DMA_CNT 21.

The register group 42 stores data such as program size data and execution start vector data of the execution program 10 read from the external memory 4 to the data memory 44 via the data bus 33, which is indicated by a control signal from the host CPU 2. Memorize

As shown in FIG. 2, the program memory 43 stores a boot program 50 in advance. Further, the program memory 43 stores the execution program 10 transferred from the external memory 4 as illustrated in FIG. 3 while the processor 41 is executing the boot program 50.

The data memory 44 is, for example, the external memory 4 while the processor 41 is executing the execution program 10.
The data 11 transferred from is stored.

[External Memory 4] As shown in FIG. 1, the external memory 4 has a program storage area 4a and a data storage area 4b. The execution program 10 is stored in the program storage area 4a. The data 11 is stored in the data storage area 4b. When the data processing system 1 is started up (when the power is turned on), the execution program 10 and the main processor 11 are read from a memory such as a flash memory (not shown) into the program storage area 4a and the data storage area 4b.

An operation example of the data processing system 1 shown in FIG. 1 will be described below. 4 and 5 are diagrams for explaining an operation example of the data processing system 1 shown in FIG. Step ST1: The host CPU 2 shown in FIG. 1 stores the program size data and the execution start vector data of the execution program 10 which the LSI 3 reads from the external memory 4 into the data memory 44 via the data bus 33 via the signal line 30. The control signal shown is output to the LSI 3. Program size data and execution start vector data are
It is stored in the register group 42 shown in FIG.

Step ST2: Host CPU shown in FIG.
2 outputs a control signal indicating a boot start instruction to the LSI 3 via the signal line 30.

Step ST3: D of the LSI 3 shown in FIG.
When the control signal indicating the boot start instruction is input from the host CPU 2 in step ST2, the SP 20 reads the boot program 50 from the program memory 43 by the processor 41 shown in FIG. 2 and starts the boot process based on the boot program 50. .

Step ST4: Processor 4 shown in FIG.
1 is the boot process started in step ST3,
The program size data and the execution start vector data are read from the register group 42, and a transfer request for the execution program is output to the DMA_CNT 21 together with the read program size data and the execution start vector data.

Step ST5: DMA_CN shown in FIG.
From the address in the program memory area 4a of the external memory 4 designated using the address bus 34, T21 is based on the designated program size data and execution start vector data based on the transfer request input in step ST4. The execution program 10 is read and written in the processor 41 shown in FIG.

Step ST6: Processor 4 shown in FIG.
1 reads the execution program 10 written in the program memory 43 in step ST5, sets the program counter according to the execution start vector data, and starts the processing based on the execution program 10.

Step ST7: Processor 4 shown in FIG.
1 indicates a case where data is read from the data storage area 4b of the external memory 4 or written in the data storage area 4b in the process of the process started in step ST6, that is, data is exchanged with the data storage area 4b. When performing the transfer, the data transfer request is output to the DMA_CNT 21.

Step ST8: DMA_CN shown in FIG.
At T21, based on the transfer request input at step ST7, the data stored in the data memory 44 or the register group 42 is read out and stored in the program storage area 4a of the external memory 4 designated using the address bus 34. Write to address. Further, the DMA_CNT 21 reads the data read from the address in the program storage area 4a of the external memory 4 designated using the address bus 34 on the basis of the transfer request input in step ST7, and outputs the data memory 44 or the register group 42. Write in.

As described above, according to the data processing system 1, as shown in FIG.
Moreover, since the execution program 10 and the data 11 are stored, the number of external memories can be reduced as compared with the conventional one. Further, according to the data processing system 1, since the number of external memories can be reduced, the number of data buses, address buses, control lines and connection terminals can be reduced. According to the data processing system 1, the LSI 3 accesses the execution program 10 and the data 11 by firmware (processing method).
Can be unified and the processing can be simplified. Further, according to the data processing system 1, the DMA_CNT 21 shown in FIG.
Only the access to the external memory 4 needs to be controlled, and the processing can be simplified.

[0032]

As described above, according to the present invention,
It is possible to provide a data processing device, a semiconductor circuit, and a data processing system that can reduce the width of a data bus between an external memory and a control circuit and reduce the number of connection terminals. Further, according to the present invention, it is possible to provide a data processing device, a semiconductor circuit, and a data processing system that can simplify the procedure for accessing the external memory from the control circuit.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a data processing system according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of the DSP shown in FIG.

FIG. 3 is a functional block diagram of the DSP shown in FIG. 1 after transferring an execution program from an external memory to the DSP.

FIG. 4 is a diagram for explaining an operation example of the data processing system shown in FIG. 1.

FIG. 5 is a diagram for explaining an operation example of the data processing system shown in FIG. 1.

[Explanation of symbols]

1 ... Data processing system, 2 ... Host CPU, 3 ... LS
I, 4 ... External memory, 4a ... Program storage area, 4
b ... data storage area, 10 ... execution program, 11 ...
Data, 20 ... DSP, 21 ... DMA_CNT, 30 ...
Signal line, 31 ... Data bus, 32 ... Signal line, 33 ... Data bus, 34 ... Address bus, 41 ... Processor, 42
... register group, 43 ... program memory, 44 ... data memory, 50 ... boot program

Claims (14)

[Claims] 1. An external memory that stores an execution program and data; and a semiconductor circuit that executes the execution program, wherein the semiconductor circuit includes a program memory that stores a boot program, a data memory, and A memory control circuit that controls the transfer of the execution program from the external memory to the program memory, and controls the data transfer between the external memory and the data memory; and the boot read from the program memory. A boot process is performed based on a program, and in the boot process, the memory control circuit is instructed to transfer the execution program from the external memory to the program memory, and the execution program read from the program memory is executed. Process based on the The data processing device and a control circuit for instructing data transfer between the memory and the data memory to the memory control circuit. 2. The control circuit receives program size data indicating a size of the execution program transferred from the external memory to the program memory from a control device external to the data processing device, and receives the program size data. The data processing device according to claim 1, wherein the data is stored in a register, and the memory control circuit transfers the execution program from the external memory to the program memory based on the program size data stored in the register. 3. The data processing according to claim 1, wherein the control circuit instructs the memory control circuit to transfer the execution program from the external memory to the program memory during execution of the boot program. apparatus. 4. The control circuit receives an execution start vector address of the execution program transferred from the external memory to the program memory from a control device external to the data processing device, and outputs the execution start vector address. The data processing device according to claim 1, wherein the data is stored in a register, and the memory control circuit transfers the execution program from the external memory to the program memory based on an execution start vector address stored in the register. 5. The data processing device according to claim 4, wherein the control circuit sets a program counter at an execution start vector address stored in the register to execute the execution program. 6. The control circuit outputs a data transfer request to the memory control circuit during execution of the execution program, and the memory control circuit outputs the data to the external memory and the data based on the data transfer request. The data processing device according to claim 1, wherein data is transferred to and from the memory for use. 7. A program memory for storing a boot program, a data memory, a transfer of an execution program from an external memory to the program memory, and data between the external memory and the data memory. A memory control circuit that controls transfer; and a boot process based on the boot program read from the program memory, wherein in the boot process, the execution program is transferred from the external memory to the program memory. Instructing the memory control circuit to perform processing based on the execution program read from the program memory, and in the process of the processing, transfer data between the external memory and the data memory to the memory control circuit. A semiconductor circuit having a control circuit for instructing. 8. The control circuit receives program size data indicating a size of the execution program transferred from the external memory to the program memory from a control device external to the data processing device, and receives the program size data. The semiconductor circuit according to claim 7, wherein the memory control circuit stores the execution program in the register, and the memory control circuit transfers the execution program from the external memory to the program memory based on the program size data stored in the register. 9. The semiconductor circuit according to claim 7, wherein the control circuit instructs the memory control circuit to transfer the execution program from the external memory to the program memory during execution of the boot program. . 10. The control circuit receives an execution start vector address of the execution program transferred from the external memory to the program memory from a control device external to the data processing device, and receives the execution start vector address. The semiconductor circuit according to claim 7, wherein the semiconductor control circuit stores the execution program in a register, and the memory control circuit transfers the execution program from the external memory to the program memory based on an execution start vector address stored in the register. 11. The semiconductor circuit according to claim 10, wherein the control circuit sets a program counter at an execution start vector address stored in the register to execute the execution program. 12. The control circuit outputs a data transfer request to the memory control circuit during execution of the execution program, and the memory control circuit outputs the data to the external memory and the data based on the data transfer request. 8. The semiconductor circuit according to claim 7, which performs data transfer with a memory for use. 13. An external memory for storing an execution program and data, a semiconductor circuit for executing the execution program, and a controller for controlling the semiconductor circuit, wherein the semiconductor circuit stores a boot program. A program memory, a data memory, and a memory control circuit that controls transfer of the execution program from the external memory to the program memory and controls data transfer between the external memory and the data memory. Instructing the memory control circuit to perform a boot process based on the boot program read from the program memory, and transferring the execution program from the external memory to the program memory in the boot process, Based on the execution program read from the program memory And a control circuit for instructing the memory control circuit to transfer data between the external memory and the data memory in the course of the processing. 14. The control device outputs program size data indicating the size of the execution program transferred from the external memory to the program memory to the semiconductor circuit, and the control circuit registers the program size data in a register. 14. The data processing system according to claim 13, wherein the memory control circuit transfers the execution program from the external memory to the program memory based on the program size data stored in the register.