JP5002238B2 - Digital signal processor system and starting method of digital signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DSP starting system and a DSP starting method which are capable of performing signal processing regardless of the size of a part of a program for initializing. <P>SOLUTION: A DSP successively loads a plurality of programs to an internal memory of the DSP and starts them, and settings which a preceding performed program has performed are held in an external storage device of a DSP card in such form that they can be used in a succeeding program to be performed. A CPU controls the sequence and timings of programs to be performed. When a plurality of DSPs exists on one DSP card, one of them controls program load timings and start timings of the other DSPs. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a DSP system and a starting method of a digital signal processor (hereinafter referred to as DSP) device.

  The DSP is a kind of processor specialized in signal processing. A DSP device using this DSP is configured by combining a DSP, a storage device, various peripheral devices, and the like. Since the DSP operates by software, the function of the signal processing apparatus that has been conventionally configured by using hardware can be realized by software.

  However, since DSP has limited available memory resources, it uses basic software such as an OS like a CPU (Central Processing Unit) or executes complicated processing such as PCI device setting processing. I can't.

  For this reason, DSP performs fixed signal processing such as digital filter processing and FFT (fast Fourier transform) processing, and processing is performed so that the CPU performs processing such as control of peripheral devices and data transfer using the PCI / VME bus. Various devices were configured by sharing.

  FIG. 6 is a diagram showing a method of using a conventional DSP. The DSP card 52 includes at least one DSP, a DSP external memory, a DSP flash ROM storing a program, a bus bridge, and the like. Each DSP reads a program to be executed at startup from the DSP flash ROM and starts processing.

  The DSP card 52 is connected to a host computer via a PCI bus or the like. The host computer includes a CPU 51, an external memory, a CPU flash ROM for storing a program, various peripheral devices, a PCI bus, a VME bus, and the like. The CPU reads a program to be executed at startup from the CPU flash ROM and starts processing. As described above, in the conventional DSP usage method, the DSP only serves as an auxiliary processor of the CPU 51 specialized for computation.

  However, now that semiconductor technology has advanced and the memory capacity that can be used by the DSP has increased, it has become possible for the DSP to execute more complex processing that was previously performed by the CPU. For this reason, there has been a demand for controlling the peripheral devices and the PCI / VME bus that have been conventionally performed with the CPU depending on the purpose.

  However, since the program memory area of the DSP is smaller than that of the CPU, the size of a program that can be executed at one time is still limited. Therefore, it becomes necessary to examine a method for mounting a program on a DSP.

  Here, the first consideration is whether or not the activation method supported by the DSP can be used. The DSP supports multiple startup methods. Specifically, it is possible to select a reading source of a program used for starting the DSP. Therefore, it is possible to mount a plurality of programs on the DSP.

  However, this selection must be made mechanically by a boot mode setting DIP switch provided outside the DSP as shown in FIG. Specifically, in order to change the setting of the DIP switch, it is necessary to remove the DSP card incorporated in the device again and switch the DIP switch manually.

  For this reason, for example, a method for storing a signal processing program in the DSP flash ROM and starting the update program for the DSP flash ROM from a host or the like cannot be used.

  The next studied method is to read a program for updating a program stored in the flash ROM of the expansion card from the external storage device such as a floppy disk when the host computer is started up, and thereby read the contents of the flash ROM of the expansion card. It is to be updated (see Patent Document 1).

  However, in this method, since it is necessary to restart the DSP in order to execute the newly updated program, there is a problem that the settings after the program before the update cannot be used by the program after the update. .

  The next considered method is that the sub processor starts the main processor with the first program, and after the main processor starts, the main processor loads the second program into the second program storage area of the sub processor, Next, the sub processor is restarted to cause the sub processor to execute the second program (see Patent Document 2).

  However, even in this method, since the DSP is restarted, there is a problem that the setting performed when the sub processor is started for the first time cannot be used when the second program is executed.

  Therefore, a conventional program configuration executed by the DSP is examined. As shown in FIG. 8, in the conventional program configuration, when the reset of the DSP is released, the program is loaded from the DSP flash ROM in step S701, and then the program is executed as shown in steps S702 to S705.

  What should be noted here is that step S702 for performing initial setting and steps S703 to S705 for performing signal processing operations are stored in the flash ROM as a series of programs.

  These series of programs are all loaded from the DSP flash ROM into the DSP internal memory. On the other hand, the size of the internal memory of the DSP is limited. For this reason, the size of the entire program is limited to a size that can be stored in the internal memory of the DSP. Therefore, there has been a problem that the portion of the program that performs signal processing is limited by the size of the portion of the program that performs initial setting that is used only once at the time of startup.

Regarding this problem, the applicant has previously filed one of the solutions. (Japanese Patent Application No. 2005-292501. Hereinafter referred to as a prior application.) In this application, a DSP boot method for a DSP device having a plurality of DSPs, wherein a first program is loaded into an internal memory of the DSP and the DSP is There is disclosed a boot method characterized in that after starting, the second program is loaded by overwriting the first program in the internal memory of the DSP.
Japanese Patent Laid-Open No. 10-91452 JP 2006-99704 A

  However, the technique of the prior application has a problem that only one activation program can be executed.

  The present invention has been made in view of the above problems, and a DSP activation method and DSP activation capable of executing signal processing regardless of the size and number of program parts to be initialized. It aims to provide a method.

In order to achieve this object, an embodiment of the present invention described in claim 1 includes a digital signal processor having an internal memory, a flash ROM storing an initial startup program for performing the first startup, and a volatile memory. At least one DSP card having a DSP external storage device, which is an external storage device having; a CPU, at least one secondary activation program for performing second and subsequent activations, and an operation program for performing signal processing. A digital signal processor activation method of a DSP device comprising: a CPU card having a CPU external storage device that is an external storage device, wherein the digital signal processor stores an initial activation program from a flash ROM when the power is turned on. At the top address of the An initial startup step for the first startup; a secondary startup program transfer step for the CPU to transfer a secondary startup program from the CPU external storage device to the DSP external storage device; and a CPU for secondary startup to the digital signal processor A secondary start program start command issuing step for issuing a start command for starting the program; and when the digital signal processor receives the secondary start program start command, the secondary start program is stored in the internal memory from the DSP external storage device. At least one secondary startup routine having a secondary startup program execution step for reading at the start address and executing the secondary startup program; and the CPU transfers the operation program from the CPU external storage device to the DSP external storage device Operation program transfer step; An operation program start command issuing step for issuing a start command for starting the operation program to the signal processor; and when the digital signal processor receives the operation program start command, the operation program is read from the DSP external storage device to the top address of the internal memory; An execution step of executing an operation program is provided. A starting method of a digital signal processor is provided.

  According to the present invention, the DSP overwrites a plurality of programs on the internal memory, repeatedly reads and executes, and the external memory of the DSP card holds the settings made by these programs so that the subsequent programs can be used. It becomes possible to execute signal processing regardless of the size and number of programs to be initialized.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing the concept of this embodiment in a simplified manner. As described above, the size of the DSP internal memory is limited. In this embodiment, a plurality of programs are sequentially loaded into the internal memory of the DSP.

  In step S101, the DSP activation program is loaded from the flash ROM, and in step S102, the first initial setting is performed.

  When initial setting after the second time is necessary, a routine from step S103 to step S106 is provided. In this routine, the second and subsequent initial setting programs are loaded from the external storage device, and the initial setting is repeated. Here, the second and subsequent programs are loaded by overwriting the program loaded in advance from the beginning of the DSP internal memory, and the initial settings made in advance are stored in the DSP external storage device, followed by The operation program such as the initial setting and signal processing performed in this way can be used. Specifically, the setting is stored in, for example, a shared area of the external storage device of the DSP.

  Finally, in step S107, the operation program is loaded by overwriting the program loaded in advance from the top of the DSP internal memory, and execution of the processing from step S108 to step S110 is started.

  As described above, this embodiment is characterized by repeatedly loading and starting a plurality of programs into the internal memory of the DSP. As a result, when the first initial setting program 150, the second and subsequent initial setting programs 160, and the operation program 170 are combined, the size of the internal memory of the DSP is exceeded.

  FIG. 2 is a schematic diagram showing the hardware configuration of this embodiment. The DSP device that performs signal processing includes at least one DSP card 30, 31, a CPU card 32, an IO card 33, and a data bus 21 that connects them.

  The DSP card 30 includes at least one DSP 10, 11, a DSP external storage device 13 that is an external storage device having a volatile memory, a flash ROM 14 that stores an initial startup program for starting the DSP for the first time, and a bus. A bus protocol conversion function 12 for converting the above protocol, a bus bridge 16 such as VME or PCI, a high-speed peripheral device 17, and a low-speed peripheral device 15. Each DSP 10, 11 has an internal memory and a direct memory access controller (hereinafter referred to as DMAC) for transferring a program to the internal memory. The above elements constituting the DSP card 30 can be appropriately deleted or added.

  When a plurality of DSPs are provided, one DSP controls the start timing of other DSPs. This is to prevent a plurality of DSPs from accessing the memory at the same time. With this configuration, it is not necessary to provide hardware for performing exclusive control on the memory. Here, a DSP that controls the start timing of another DSP is called a master DSP, and a DSP whose start timing is controlled by the master DSP is called a slave DSP.

  The CPU card 32 includes a CPU 23 and a CPU external storage device 22 which is an external storage device for storing at least one secondary activation program for performing the second and subsequent activations of the DSP and an operation program for performing signal processing.

  It is preferable to use a large capacity memory such as a page memory for the DSP external storage device 13 and the CPU external storage device 22. The IO card 33 has communication means for performing communication between the DSP device and an external device.

  Next, the operation in the present embodiment will be described based on the flowcharts shown in FIGS. The initial setting of each DSP at the first power-on is as shown by the arrow 101. Each DSP reads the initial startup program stored in the flash ROM 14 at the start address of the internal memory of each DSP and executes it. To do. This process is called an initial activation step. The CPU 23 controls the starting process and the operation program loading and execution for the second and subsequent times.

  FIG. 3 is a flowchart of processing performed by the CPU 23. When the power is turned on, the CPU 23 waits for an activation start instruction in step S201. If there is no start instruction, the waiting operation is continued. If there is a start instruction, the process proceeds to step S202.

  Next, the CPU 23 repeats steps S202 to S213 until the number j of programs executed by the DSP stored in the CPU external storage device 22 is reached. These programs may be stored in an available storage device other than the CPU external storage device.

  In step S <b> 203, the CPU 23 reads the j-th program from the CPU external storage device 22.

  Next, the CPU 23 repeats steps S204 to S206 up to the number i of DSP cards. In step S205, the CPU 23 transfers the read j-th program to the DSP external storage device 13 of each DSP card, as indicated by an arrow 102 in FIG. Thus, the CPU 23 controls the order of programs transferred from the CPU external storage device 22 to the DSP external storage device 13. In step S206, the master / DSP adds 1 to i and returns to step S204.

  If the program to be transferred is a program for starting the second and subsequent DSPs, the program is called a secondary startup program, and the step of transferring to the DSP external storage device 13 is called a secondary startup program transfer step. . If the transferred program is a program for operating a DSP such as signal processing, the program is called an operation program, and the step of transferring to the DSP external storage device 13 is called an operation program transfer step.

  When the j-th program is transferred to the DSP external storage device, each DSP does not access the DSP external storage device. For this reason, exclusive control of the DSP external storage device is unnecessary. Further, since the bus protocol conversion function 12 is provided, the CPU 23 does not need to match the data format to be transferred to the types of buses 18, 19, and 20 in the DSP card.

  Next, the CPU 23 repeats steps S207 to S209 up to the number i of DSP cards. In step S208, the CPU 23 issues an activation command to the master / DSP of the i-th DSP card, as indicated by the arrow 103 in FIG. In step S209, the master / DSP adds 1 to i and returns to step S207.

  If the program to be activated is a secondary activation program, this step is called a CPU secondary activation program activation command issue step. If the program to be activated is an operation program, this step is referred to as a CPU operation program activation command issue step. Call it.

  As will be described later, when the master / DSP receives this activation command, the master / DSP performs a given operation to perform a process of activating each DSP. When the DSP activation process is completed, each DSP writes the activation completion status in the DSP external storage device 13.

  Next, the CPU 23 repeats steps S210 to S212 up to the number i of DSP cards. In step S211, the CPU 23 determines whether a start completion status is written in the DSP external storage device of each DSP card. If not written, the determination operation is repeated. If the activation completion status is written for all the DSP cards, the process proceeds to step S213.

  When execution of all the programs to be executed is completed, in step S214, the CPU 23 performs CPU card activation processing.

  If it is not necessary to execute the secondary startup program, the secondary startup program transfer step and the CPU secondary startup program startup command issue step are not performed.

  FIG. 4 is a flowchart of processing performed by the master / DSP. When the power is turned on, the master / DSP reads the initial startup program from the flash ROM 14 to the top address of the internal memory of the master / DSP in step S301, performs the first startup by this initial startup program, and performs the initial setting.

  Next, the master / DSP waits for an activation command from the CPU 23 in step S302. At this time, the master / DSP does not access the data bus 20 and the DSP external storage device 13. If the start command is not received, the waiting operation is continued. If an activation command is received, the process proceeds to step S303.

  Next, the master DSP repeats steps S303 to S306 up to the number k of slaves and DSPs. In step S304, the master / DSP determines whether the slave / DSPk is a restart target. If it is not a restart target, 1 is added to k in step S306, and the process returns to step S303. If it is a restart target, the process proceeds to step S305.

  In step S305, the master / DSP issues an activation command to the slave / DSPk as indicated by the arrow 104 in FIG. 2, and the process proceeds to step S306. At this time, since each slave DSP does not access the data bus 20 and the DSP external storage device 13, it is not necessary to perform exclusive control. In step S306, the master / DSP adds 1 to k and returns to step S303.

  Next, in step S307, the master / DSP designates the start address of the internal memory of the master / DSP as a direct memory access (hereinafter referred to as DMA) transfer completion vector.

  Next, in step S308, the master / DSP activates the built-in DMAC. Here, the master DSP is stopped by the built-in DMAC. As shown by an arrow 105 in FIG. 2, the built-in DMAC transfers a program from the DSP external storage device 13 to the internal memory of the master / DSP according to the setting. As a result, the previously loaded program is overwritten.

  In step S309, the master DSP receives the DMA transfer completion interrupt and executes the newly loaded program from the top. When the executed program is an initial startup program or a secondary startup program, the master / DSP stores settings made by these programs in the DSP external storage device 13 in a form that can be used by subsequent programs. Specifically, the master / DSP stores these settings in, for example, a shared area of the DSP external storage device 13.

  As described above, when the program is loaded into the internal memory of the master / DSP, the execution of the program in the master / DSP is stopped by simply overwriting the newly loaded program in the internal memory using the built-in DMAC. To avoid.

  Here, when the master / DSP receives the secondary startup program startup command, the master / DSP issues a startup command to cause each slave / DSP to start the secondary startup program. The operation of reading the next startup program into the start address of the internal memory of the master / DSP and executing the secondary startup program is called a DSP secondary startup program startup command issuing step.

  If it is not necessary to execute the secondary startup program, the DSP secondary startup program startup command issuing step is not performed.

  Also, when the master / DSP receives the operation program start command, the master / DSP issues a start command for starting each slave / DSP to start the operation program, and the operation program is transferred from the DSP external storage device 13 to the inside of the master / DSP. The operation of reading the start address of the memory and executing the operation program is called a DSP operation program start command issuing step.

  FIG. 5 is a flowchart of processing performed by the slave / DSP. When the power is turned on, the slave DSP reads the initial startup program from the flash ROM 14 to the top address of the internal memory of the slave DSP in step S401, performs the first startup by this initial startup program, and performs initial settings.

  Next, the slave DSP waits for an activation command from the master DSP in step S402. At this time, the slave DSP does not access the data bus 20 and the DSP external storage device 13. If the start command is not received, the waiting operation is continued. If an activation command is received, the process proceeds to step S403.

  Next, in step S403, the slave / DSP designates the start address of the internal memory of the slave / DSP in the DMA transfer completion vector.

  Next, in step S404, the slave DSP activates the built-in DMAC. Here, the slave DSP is stopped by the built-in DMAC. As shown by an arrow 106 in FIG. 2, the built-in DMAC transfers a program from the DSP external storage device 13 to the internal memory of the slave / DSP according to the setting. As a result, the previously loaded program is overwritten.

  In step S405, the slave DSP receives the DMA transfer completion interrupt and executes the newly loaded program from the top. If the executed program is an initial startup program or a secondary startup program, the slave DSP stores the settings made by these programs in the DSP external storage device 13 in a form that can be used by subsequent programs. Specifically, the slave DSP stores these settings in, for example, a shared area of the DSP external storage device 13.

  As described above, when the program is loaded into the internal memory of the slave / DSP, the execution of the program in the slave / DSP is stopped by simply overwriting the newly loaded program in the internal memory using the built-in DMAC. To avoid.

  Here, when each slave / DSP receives a secondary start program start command, the secondary start program is read from the DSP external storage device 13 into the start address of each internal memory of each slave / DSP. The operation of executing the startup program is called a slave / DSP secondary startup step.

  If it is not necessary to execute the secondary startup program, the slave / DSP secondary startup step is not performed.

  When each slave / DSP receives an operation program start command, the operation program is read from the DSP external storage device 13 to the top address of each internal memory of each slave / DSP and the operation to execute the operation program is executed by the slave / DSP. This is called a step.

  Here, when there is one DSP in the DSP card, the CPU 23 transfers the secondary startup program from the CPU external storage device 22 to the DSP external storage device 13, and the CPU 23 performs secondary startup to the DSP. A secondary start program start command issuing step for issuing a start command for starting the start program, and when the DSP receives the secondary start program start command, the secondary start program from the DSP external storage device 13 is stored in the DSP. The secondary startup program execution step for reading into the start address of the memory and executing the secondary startup program is collectively referred to as a secondary startup routine.

  When there is one DSP in the DSP card, the DSP is treated as a master / DSP, and processing for the slave / DSP is not performed.

  If the DSP card has a master / DSP and a slave / DSP, the master / DSP causes each slave / DSP to start the secondary startup program when the master / DSP receives the secondary startup program startup command. Issue a startup command, read a secondary startup program from the DSP external storage device 13 to the top address of the master / DSP internal memory, execute a secondary startup program, a DSP secondary startup program startup command issue step, and a slave When the DSP receives a secondary start program start command, the secondary start program is read from the DSP external storage device 13 to the start address of each slave / DSP internal memory and the secondary start program is executed. The slave / DSP secondary startup step is collectively referred to as a multiple DSP secondary startup routine.

  When the secondary activation program is not required, the secondary activation routine or the multiple DSP secondary activation routine is not performed. When only one secondary startup program is required, the secondary startup routine or secondary startup program is executed once. When multiple secondary startup programs are required, the secondary startup routine or secondary startup program is executed. Is performed as many times as necessary.

  As described above, in the DSP system and the DSP activation method of the present embodiment, a program in which a plurality of programs are sequentially loaded and activated in the DSP's internal memory and the DSP external storage device 13 is executed in advance. Since the setting executed by the program is stored in a form that can be used by the program to be executed subsequently, a plurality of programs exceeding the size of the internal memory of the DSP can be executed together.

  In addition to this, in addition to the execution of the arithmetic processing program which is the main purpose of the DSP, setting processing of a plurality of peripheral devices becomes possible.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is the flowchart which expressed the idea of this embodiment simplified. It is a schematic diagram showing a hardware configuration. It is a flowchart of the process which CPU performs. It is a flowchart of the process which a master and DSP perform. It is a flowchart of the process which a slave DSP performs. It is the figure which showed the utilization method of the conventional DSP. It is a figure explaining the boot mode setting DIP switch of DSP. It is a flowchart explaining the conventional program structure.

Explanation of symbols

10, 11: DSP,
12: Bus protocol conversion function,
13: DSP external storage device,
14: Flash ROM,
15: Low-speed peripheral device,
16: VME-PCI bus bridge,
17: High-speed peripheral device,
18, 19, 20, 21: data bus,
22: CPU external storage device,
23: CPU,
30, 31: DSP card,
32: CPU card,
33: IO card.

Claims (2)

A digital signal processor having an internal memory;
A flash ROM for storing an initial startup program for performing the first startup;
A DSP external storage device which is an external storage device having a volatile memory;
At least one DSP card having:
CPU,
A CPU card having at least one secondary activation program for performing the second and subsequent activations and a CPU external storage device that is an external storage device for storing an operation program for performing signal processing;
A digital signal processor activation method for a DSP device comprising:
An initial startup step in which the digital signal processor reads the initial startup program from the flash ROM into the top address of the internal memory when the power is turned on, and performs a first startup by the initial startup program;
A secondary startup program transfer step in which the CPU transfers the secondary startup program from the CPU external storage device to the DSP external storage device;
A secondary start program start command issuing step in which the CPU issues a start command for starting the secondary start program in the digital signal processor;
When the digital signal processor receives the secondary start program start command, the secondary start program is read from the DSP external storage device into the top address of the internal memory, and the secondary start program is executed. At least one secondary activation routine comprising: a next activation program execution step;
An operation program transfer step in which the CPU transfers the operation program from the CPU external storage device to the DSP external storage device;
An operation program start command issuing step in which the CPU issues a start command for starting the operation program to the digital signal processor;
An execution step of reading the operation program from the DSP external storage device into the top address of the internal memory and executing the operation program when the digital signal processor receives the operation program start command;
A method for starting a digital signal processor, comprising: One master digital signal processor having internal memory and controlling the start-up timing of other digital signal processors;
At least one slave digital signal processor having an internal memory and whose start timing is controlled by the master digital signal processor;
A flash ROM for storing an initial startup program for performing the first startup;
A DSP external storage device which is an external storage device having a volatile memory;
At least one DSP card having:
CPU,
A CPU card having at least one secondary activation program for performing the second and subsequent activations and a CPU external storage device that is an external storage device for storing an operation program for performing signal processing;
A digital signal processor activation method for a DSP device comprising:
An initial startup step in which the digital signal processor reads the initial startup program from the flash ROM into the top address of the internal memory when the power is turned on, and performs a first startup by the initial startup program;
A secondary startup program transfer step in which the CPU transfers the secondary startup program from the CPU external storage device to the DSP external storage device;
A CPU secondary startup program start command issuing step in which the CPU issues a start command for starting the secondary start program to the master digital signal processor;
When the master digital signal processor receives the secondary start program start command, the master digital signal processor issues a start command for causing each slave digital signal processor to start the secondary start program; A step of issuing a DSP secondary start program start command for reading the secondary start program from the DSP external storage device into the start address of the internal memory of the master digital signal processor and executing the secondary start program;
When the slave digital signal processor receives the secondary start program start command, the secondary start program is sent from the DSP external storage device to the start address of each internal memory of each slave digital signal processor. A slave / DSP secondary startup step of reading and executing the secondary startup program;
At least one multiple DSP secondary startup routine having:
An operation program transfer step in which the CPU transfers the operation program from the CPU external storage device to the DSP external storage device;
A CPU operation program start command issuing step in which the CPU issues a start command for starting the operation program to the master digital signal processor;
When the master digital signal processor receives the operation program start command, the master digital signal processor issues a start command for starting the operation program to each slave digital signal processor, from the DSP external storage device A DSP operation program start command issuance step for reading the operation program into the start address of the internal memory of the master digital signal processor and executing the operation program;
When the slave digital signal processor receives the operation program start command, the operation program is read from the DSP external storage device into the start address of each internal memory of each slave digital signal processor, and the operation program is read. A slave DSP execution step to be executed;
A method for starting a digital signal processor, comprising:

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