JP2002073341A - Dsp program download system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DSP program download method which can be made faster by reducing time required in downloading a program to plural DSPs. SOLUTION: When power is applied, the CPU 1 writes the DSP program stored in advance in the memory 2 to the dual port memory 3 for a program storage after its initialization process. When the power is applied, the DSPs 5-7 become the program transfer standby status and output a DMA transfer request to the DMA controller (DMAC) 4. CPU 1 writes the DSP program to dual port memory 3 for the program storage and sets the DMA start address, the number of DMA transfer bytes and the DMA transfer permission to DMAC 4. DMAC 4 executes the DMA operation to DSPs 5-7 based on a set address and the number of bytes to be transferred and outputs the DMA transfer completion signal to CPU 1 after the DMA operation is completed. When the program transfer is completed, DSPs 5-7 output the download completion notice interrupting to CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a DSP program download system, and more particularly to a DSP (Digita) used as a voice coding / decoding circuit of a transmission control device.
l SignalProcessor) peripheral circuits.

[0002]

2. Description of the Related Art A DSP is a one-chip microprocessor dedicated to digital signal processing, and can perform repetition of product-sum operations, which are particularly common in digital signal processing, at least one digit faster than general-purpose microprocessors. It is used as a speech encoding / decoding circuit of a transmission control device.

As a method of downloading a program to the DSP, there is a method described in Japanese Patent Application Laid-Open No. 213968/1990, and the above-mentioned publication describes a method of downloading a program to a single DSP.

In the method disclosed in the above publication, when a plurality of DSPs exist, it takes a very long time to download a program. In this case, the time required to download the program to all DSPs is n D
If there is an SP, one download unit time × n times is required. Also, while the program is being downloaded to the DSP, only the processing can be performed.
Cannot interface to P.

Japanese Patent Application Laid-Open No. 8-249272 discloses that one program download is performed for a plurality of DSPs.
A method is described in which a program is converted into block data and downloaded sequentially, instead of performing each one separately, and the object is to reduce the total time required for downloading the program.

In the above method, the program download itself is performed by a CPU (Central Processing Unit).
While downloading data to the DSP, only that processing can be performed, and no interface can be taken with another DSP.

Further, Japanese Patent Application Laid-Open No. 11-120002 discloses an example in which a DSP program memory is provided one-to-one with respect to a DSP. In the technology described in this publication, a program to be downloaded to each DSP is held in the form of a master ROM, and downloaded to a program memory of each DSP in synchronization with an address generated cyclically by an address generation unit. The method is adopted.

[0008] The method described in the above-mentioned publication describes a method of sequentially downloading one by one and a method of sequentially downloading with a slight time lag. The program is simultaneously downloaded to each DSP. I can't.

[0009]

The above-mentioned conventional DSP
According to the method of downloading a program, when a CPU directly downloads a DSP program, a plurality of program downloads cannot be performed simultaneously. In addition, when the program is executed by the CPU or when the program is divided into blocks,
Only one DSP can be controlled.

Further, there is a method of downloading a plurality of programs at the same time, but it is impossible to download the programs to a plurality of DSPs at exactly the same timing. Therefore, in the case where a plurality of DSPs exist in the conventional download method, the program cannot be downloaded to all the DSPs at the same time.

When a CPU directly downloads a program to a DSP, the CPU itself is performing the download process, so that no interface can be taken with another DSP at that time. Even if the interface could be taken, it would interrupt the program download process, and would be delayed by the time it takes to complete the program download.

Therefore, when a program is downloaded to one DSP, a software interface such as a command / status cannot be taken from the CPU to the other DSPs.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to reduce the time required to download a program to a plurality of DSPs, thereby increasing the speed.
It is to provide a program download system.

Another object of the present invention is to provide a DS which can interface with another DSP even while a program is being downloaded to a certain DSP.
A P program download system is provided.

[0015]

A DSP program download system according to the present invention is a DSP program download system for downloading a program to each of a plurality of digital signal processors used as a voice encoding / decoding circuit. A program download memory for storing a program to be downloaded to each of the digital signal processors;
Control means for controlling direct memory access from each of the plurality of digital signal processors to the program download memory.

Another DSP program download system according to the present invention has, in addition to the above-described configuration, a DSP program transfer bus for transmitting a program to each of the plurality of digital signal processors, and a DSP program transfer bus connected to the DSP program transfer bus. And a control bus for connecting each of the plurality of digital signal processors to a central processing unit; and means for separating the DSP program transfer bus from the control bus.

That is, according to the DSP program download method of the present invention, an audio codec program to be used as an audio encoding / decoding circuit is stored in a DSP (Digital
DMAC (Direct memory A) for downloading to a Signal Processor
access controller) and a memory for storing a DSP program.

When a shared memory is used as communication means between the CPU (Central Processing Unit) and the DSP, one DSP
In order to enable communication between the CPU and the DSP for other DSPs even when downloading to
A program transfer bus and a DSP local bus are connected to the SP.

Further, in the DSP program download method of the present invention, a bus separation buffer for separating the control bus and the program transfer bus of the CPU during the program download, and a control bus of the CPU and the DSP local bus during the DSP operation. A bus arbiter for performing bus arbitration on the DSP local bus.

The CPU transfers all programs to be downloaded to the DSP to the DSP program storage memory in advance, and the DMAC synchronizes DMA transfer request signals from all the DSPs so that the DMA transfer request signals from the program storage memory can be transferred to the DSP from the DSP storage memory. Program download is realized.

By using the DMAC, it is possible to complete the program download for a plurality of DSPs at the same time. Therefore, there is an effect that the time required for the program transfer becomes the same regardless of whether one or twenty DSPs are used.

Further, since the bus separation buffer is provided between the CPU control bus and the program transfer bus, the operation of the CPU is not affected even when the DMAC is operating.
When the CPU accesses the shared memory or each DSP accesses, the CPU outputs a bus request signal to the bus arbiter. On the other hand, the bus arbiter assigns priorities and outputs a bus permission signal to any one of the other parties. By this operation, the right to use the DSP local bus is determined.

Since the CPU can operate even while the DMAC is downloading the program, the CPU can access the shared memory and can take an interface.

As described above, by realizing the program download process itself by hardware, the CPU
Can be reduced, and the time that can be spent on transmission processing can be extended. In other words, in the present invention, although the circuit configuration is simple and the circuit configuration inside the bus arbitration block is somewhat complicated, it is possible to reduce the cost as a whole and form a simple circuit configuration.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a DSP program download system according to one embodiment of the present invention. In FIG. 1, a DSP program download system according to an embodiment of the present invention includes a CPU 1
, A memory 2, a program storage dual port memory 3, and a DMAC (Direct memory Ac).
ESS Controller 4) and DSP (Dig)
ital Signal Processor) (# 1
To # 3) 5 to 7 and dual-port memories 8 to 10 for CPUIF (interface).

The CPU 1 controls the transfer of programs to the DSPs 5 to 7. The memory 2 has a program for the CPU 1 and D
Programs to be downloaded to SPs 5 to 7 are stored first.

Dual port memory 3 for storing programs
Stores a program to be downloaded to DSPs 5-7. The DMAC 4 transfers the program from the dual port memory 3 for storing programs to the DSPs 5 to 7.

The DSPs 5 to 7 are used as a speech coding / decoding circuit (not shown) of a transmission control device for transferring a program and repeating a product-sum operation in digital signal processing. CPUIF dual port memory 8-10 is C
It is arranged between PU1 and DSPs 5-7.

The CPU 1, the memory 2, the dual port memory 3 for storing programs, the DMAC 4,
The dual port memories for F 8 to 10 are connected by a common control bus 101. Dual port memory 3 for storing programs, DMAC 4, DSPs 5 to 7
Are connected by a program transfer bus 102.

The DSP 5 and the CPU IF dual port memory 8 are connected by a DSP local bus 103,
P6 and dual port memory 9 for CPUIF are DSP
Connected by local bus 104, DSP7 and CPUIF
Dual port memory 10 is DSP local bus 1
05.

The DMAC 4 is connected to the control bus 10 from the CPU 1.
1 and the program transfer bus 102. DMAC 4 is the address / data / control bus 101
Although connected to all the control buses, the address / control bus is connected to the program transfer bus 102.

Each of the DSPs 5 to 7 sends a DMC signal to the DMAC 4.
A DMA transfer request signal is output, and DMAC 4
An MA transfer permission signal is output. The DMAC 4 outputs a DMA transfer end signal for notifying the CPU 1 that the DMA transfer has ended.

FIG. 2 is a sequence chart showing the processing operation of the DSP program download system according to one embodiment of the present invention, and FIG. 3 is a DM chart according to one embodiment of the present invention.
6 is a timing chart showing an A operation. FIG. 4 is a timing chart showing a state when a program is downloaded to all DSPs according to an embodiment of the present invention. FIG. 5 is a timing chart showing a state when a program is downloaded to some DSPs according to an embodiment of the present invention. 6 is a sequence chart showing the operation of FIG.
6 is a timing chart showing a state when a program is downloaded to an SP.

The operation of the DSP program download system according to one embodiment of the present invention will be described with reference to FIGS. First, the operation when the power is turned on will be described with reference to FIG.

After the power is turned on, the CPU 1 writes the DSP program stored in the memory 2 in advance into the dual port memory 3 for storing the program after the initialization processing. Also,
When the power is turned on, the DSPs 5 to 7 enter a program transfer waiting state and output a DMA transfer request to the DMAC 4.

After the CPU 1 writes the DSP program into the dual port memory 3 for storing the program, the CPU 1
4, the DMA start address, the number of DMA transfer bytes,
DMA transfer permission is set.

The DMAC 4 performs a DMA operation on the DSPs 5 to 7 according to the set address and the number of transfer bytes. The DMAC 4 outputs a DMA transfer end signal to the CPU 1 when the DMA operation for the DSPs 5 to 7 ends.

Upon completion of the program transfer, the DSPs 5 to 7 write a program download completion message to the CPU IF dual port memories 8 to 10, and
Output a download completion notification interrupt.

Next, referring to FIG.
The detailed timing when transferring the program to 5 to 7 will be described. When all the DMA transfer request signals of the DSPs 5 to 7 become low level, the address is output from the DMAC 4.

Dual port memory 3 for storing programs
Inputs this address and outputs data corresponding to this address. After outputting the address, the DMAC 4 sets the DMA transfer permission signal to a low level at a timing when data is output.

The DSPs 5 to 7 confirm that the DMA transfer permission signal has become low level, take in the data, and
The A transfer request signal is set to a high level. DMAC4 is DM
When the A transfer request signal goes high, the DMA permission signal goes high. The DSPs 5 to 7 output a low level to the DMA transfer request signal until the data to be received ends, and repeat the above cycle.

FIG. 4 shows the state of each of the DSPs 5 to 7 after the power is turned on, and FIG. 5 shows the operation during normal operation. In FIG. 5, there is a program write, but this write is performed only when there is a change to the written one when the power is turned on, and is not performed when there is no change.

When performing program transfer during operation, the CPU
1 notifies the DSPs 5 to 7 of a program transfer request via the CPUIF dual port memories 8 to 10. The DSPs 5 to 7 receiving the notification perform a process of accepting the program transfer, and after the preparation is completed, notify the CPU 1 of the program transfer permission to the CPU 1 via the CPU IF dual port memories 8 to 10. I do. At the same time, the DSPs 5 to 7 output a DMA transfer request signal to the DMAC 4.

After receiving the program transfer permission notice, the CPU 1 issues a DMA start address and DM
A transfer byte count and DMA transfer permission are set. At this time, the DMAC 4 performs a DMA operation according to the set address and the number of transfer bytes.
That is, DMA transfer is performed only to the DSP that has output the DMA transfer permission. The operation after the DMA transfer is the same as the above-described sequence when the power is turned on.

The other difference from power-on is that the DSP
It is possible to issue a request for encoding / decoding to a DSP that has not transferred a program during the program transfer (see FIGS. 5 and 6).

FIG. 7 is a block diagram showing the configuration of a DSP program download system according to another embodiment of the present invention, and FIG. 8 is a timing chart showing the operation of the DSP program download system according to another embodiment of the present invention. . In FIG. 7, a DSP program download system according to another embodiment of the present invention includes a CPU 1,
Memory 2, program storage memory 11, DMAC
4, DSP5, 6, CPUIF (interface)
Memories 12 and 13 and bus separation buffers 14 to 16
And bus arbiters 17 and 18.

Referring to FIG. 7, the basic structure of a DSP program download system according to another embodiment of the present invention is the same as that of the above-described embodiment of the present invention. In this regard, we are further devising this point.

The difference between the other embodiment of the present invention and the embodiment of the present invention is that the dual port memory 3 for storing programs and the dual port memories 8 to 10 for CPUIF And CPUIF memories 12 and 13.

Thus, the CPU 1 can access the memory 2 except during the DMA transfer. CPU1 is D
When DMA transfer permission is set for MAC4, D
The MAC 4 closes the bus separation buffer 14 and outputs the CP
The control bus 101 of U1 and the program transfer bus 102 are separated. In other words, this allows the program to be downloaded without stopping the CPU 1 even during the DMA operation.

The CPU 1 has the CPU IF memories 12 and 13
Is accessed once, a bus request is output to the bus arbiters 17 and 18 and the system waits until the wait request is released. Therefore, the timing of the bus arbitration operation using the bus arbiters 17 and 18 is as shown in FIG.
It becomes as shown in.

FIG. 9 is a block diagram showing the configuration of a DSP program download system according to another embodiment of the present invention, and FIG. 10 is a timing chart showing the operation of the DSP program download system according to another embodiment of the present invention. . In FIG. 9, a DSP program download system according to another embodiment of the present invention has a CPU 1
, Memory 2, program storage memory 11, DM
AC4, DSPs (# 1 to # 3) 5 to 7, CPUIF
(Interface) memory 12, bus separation buffers 14 and 15, and bus arbiter 17.

In FIG. 9, the basic configuration of a DSP program download system according to another embodiment of the present invention is the same as that of the above-described other embodiment of the present invention. The difference between another embodiment of the present invention and another embodiment of the present invention is that C
The point is that one PUIF memory 12 is not prepared for each of DSPs 5 to 7, but one is prepared for n DSPs. The CPU IF memory 12 is used in common by the n DSPs and the CPU 1.

Thus, the DSP local bus 103
The bus arbiter 17 that performs the bus arbitration is one, and the bus arbitration of a plurality of devices is performed. The timing of the bus arbitration operation using the bus arbiter 17 at this time is shown in FIG.
0. Therefore, in another embodiment of the present invention, in addition to the above-described effects, an effect of reducing the apparatus cost can be obtained.

As described above, the DMA is performed on one channel, all the DMA request signals are processed, and the DMA transfer is performed at the same time.
Downloading for 30 DSPs can be completed simultaneously.

Further, DSPs 5 to 7 which are separately connected to a bus for performing a program transfer and a local bus are used.
There is a case where a plurality of DSPs 5 to 7 are controlled by one CPU 1 by arranging a memory for interface and a memory for program transfer between PU 1 and DSPs 5 to 7 and using DMA for program download. D
While downloading a program to an SP, an interface can be established with another DSP.

[0056]

As described above, according to the DSP program download method of the present invention, in the DSP program download system for downloading a program to each of a plurality of digital signal processors used as a voice encoding / decoding circuit, By controlling direct memory access from each of the plurality of digital signal processors to a program download memory storing a program to be downloaded to each of the plurality of digital signal processors,
For P, there is an effect that the time required for downloading the program can be reduced and the speed can be increased.

According to another DSP program download method of the present invention, a DSP program transfer bus for transmitting a program to each of a plurality of digital signal processors and a plurality of digital signals connected to the DSP program transfer bus are provided. By providing a means for separating each processor from the control bus connecting the central processing unit, it is possible to interface with another DSP even while downloading a program to one DSP. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DSP program download system according to one embodiment of the present invention.

FIG. 2 is a sequence chart showing a processing operation of a DSP program download system according to one embodiment of the present invention.

FIG. 3 is a timing chart showing a DMA operation according to an embodiment of the present invention.

FIG. 4 is a timing chart showing a state when a program is downloaded to all DSPs according to an embodiment of the present invention.

FIG. 5 is a sequence chart showing an operation when a program is downloaded to some DSPs according to an embodiment of the present invention.

FIG. 6 is a timing chart showing a state when a program is downloaded to some DSPs according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a DSP program download system according to another embodiment of the present invention.

FIG. 8 is a timing chart showing an operation of a DSP program download system according to another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a DSP program download system according to another embodiment of the present invention.

FIG. 10 is a timing chart showing an operation of a DSP program download system according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Memory 3 Dual port memory for program storage 4 DMAC 5-7 DSP 8-10 Dual port memory for CPUIF 11 Memory for program storage 12, 13 CPUIF memory 14-16 Bus separation buffer 17, 18 Bus arbiter

Claims (4)

[Claims] 1. A DSP program download system for downloading a program to each of a plurality of digital signal processors used as an audio encoding / decoding circuit, wherein the program stores a program to be downloaded to each of the plurality of digital signal processors. A DSP program download system comprising: a download memory; and control means for controlling direct memory access from each of the plurality of digital signal processors to the program download memory. 2. A DSP program transfer bus for transmitting a program to each of the plurality of digital signal processors, and a bus connected to the DSP program transfer bus and connecting each of the plurality of digital signal processors to a central processing unit. 2. The DSP program download system according to claim 1, further comprising: a control bus; and means for separating the DSP program transfer bus from the control bus. 3. The DSP program download system according to claim 1, further comprising an interface memory for connecting each of said plurality of digital signal processors to said control bus in common. 4. The apparatus according to claim 1, wherein said control means processes a plurality of direct memory access requests on one direct memory access channel.
The DSP program download system according to any one of claims 1 to 3.