JP2011059787A - Digital signal processor system and starting method for digital signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital signal processor system capable of performing operation by one kind of an execution file even if a part of parameters differs at each of a plurality of DSP cards regardless of identical processing contents in a DSP execution file. <P>SOLUTION: The digital signal processor system includes: a CPU card 6 having a CPU 4 and a first external storage device 5 storing a data file including a plurality of commands starting each execution file and execution programs for a plurality of DSPs; and the DSP cards 2 each having a second external storage device 15 storing a data file, a ROM 17 storing an initialization program, and the plurality of DSPs 11. When a first DSP 11 of the DSP card 2 is ROM-booted and notified of a starting instruction, the first DSP 11 sequentially issues starting instructions to the respective second-Nth DSPs, and the respective second-Nth DSPs 11 read the execution programs into the head address of an internal memory 9, acquire commands created by the CPU card 6, and thereafter execute necessary processing. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a digital signal processor system and a digital signal processor startup method.

  FIG. 7 is a diagram illustrating a configuration example of the signal processing device. The signal processing device 49 includes a commercially available DSP card 50 equipped with a flash ROM, and an expansion slot 51 in which the DSP card 50 is inserted and a personal computer 52 having a mother board (not shown). The DSP card 50 includes N DSPs 53, a DSP flash ROM 55 connected to these DSPs 53 via a data bus 54, an external memory 56 for storing the calculation results of each DSP 53, and an interface process with the personal computer 52. PCI (Peripheral Component Interconnect) -DSP bridge 57. The flash ROM 55 stores each program describing calculation instructions for N DSPs 53. From the flash ROM 55, each DSP 53 reads a program executed by itself at the time of activation.

  The motherboard of the personal computer 52 is connected to the PCI bus 58 connected to the PCI-DSP bridge 57, the PCI-host bridge 59 connected to the PCI bus 58, and the PCI-host bridge 59 via the data bus 60. And an external memory 63 connected to the PCI-host bridge 59 via a data bus 62 is provided. Further, the PCI-host bridge 59 includes a flash ROM 65 for the CPU 61 via a data bus 64, a peripheral device 66 such as a display controller, and an HDD (hard disk drive) 67 in which drivers and applications provided by the DSP manufacturer are stored. It is connected. A PCI-VME bridge 68 connected to the VME bus 69 is connected to the PCI bus 58.

  Communication between the personal computer 52 and the DSP 53 is performed by the CPU 61 executing the driver and application of the HDD 67. Communication between the DSPs 53 on the DSP card 50 is performed by using a unique communication function of each DSP 53 itself.

  Since the DSP has various functions specialized for signal processing, many signal processing functions that have been conventionally configured by hardware have been softwareized. Usually, DSP has few memory resources that can be used as compared with a CPU, and therefore basic software such as a CPU (hereinafter referred to as an OS) cannot be used. For this reason, the DSP does not have a command line argument function provided by the OS. Therefore, in the case of a PC, an arbitrary process in a program can be executed by one program and a command line argument function, but a DSP without a command line argument function needs to divide the program according to the process. In addition, when the DSP uses ROM boot, it is necessary to change the program by updating the ROM. Therefore, as shown in FIG. 7, the signal processing performed by the DSP is assigned fixed signal processing such as digital filter processing or FFT processing, and the CPU executes control of peripheral devices and data transfer using the PCI / VME bus. Etc., and had a complementary relationship with each other.

  Regarding a program execution technique by a processor, conventionally, a startup control method is known in which a sub processor can execute an arbitrary program after a main processor is started (see Patent Document 1). The activation control method described in Patent Literature 1 is a method in a personal computer, a server computer, or an embedded system for various electronic devices, and the activation target is a general-purpose CPU. Regarding a method for starting up a computer system, a method of starting up a computer system is known in which an expansion board equipped with a circuit for extending the function of the computer system can be connected (see Patent Document 2). The start-up method described in Patent Document 2 enables the expansion board to be used when starting the computer system regardless of the CPU format of the computer system and the ROM format specification of the expansion board. The technologies described in Patent Documents 1 and 2 are not small in memory capacity like the internal memory of a DSP. In both cases, since the startup target is a general-purpose CPU, the usable memory capacity is larger than the internal memory capacity of the DSP, and the OS can be used within the range allowed by the required performance.

JP 2006-99704 A Japanese Patent Laid-Open No. 10-91452

  Conventionally, since the memory capacity that can be used by the DSP is small, a simple DSP is assigned a fixed process, and the target process is executed in units of a DSP card in which a plurality of DSPs are collected. Therefore, since the program stored in the flash ROM on the DSP card is fixed unless a problem occurs, it need not be updated. In other words, from the viewpoint of the CPU, the DSP is an auxiliary processor specialized for computation. Further, since the processing scale is small, the signal processing apparatus has about 1 to 10 commercially available DSP cards and the number of execution programs is small, so that the flash ROM can be easily updated.

  However, at present, due to advances in semiconductor technology, the memory capacity that can be used by the DSP has increased, and more complex processing can be executed. Furthermore, due to the increase in processing scale, there are cases where 10 to several hundreds of commercially available DSP cards are used in one signal processing device.

  On the other hand, although the DSP program has the same processing contents, some of the parameters such as the number of channels for data input and the allocation address of the shared memory are different. For this reason, since the number of execution programs is large, configuration management and flash ROM update are burdened.

  Therefore, in view of the above circumstances, the present invention adds a command line argument function to the DSP boot function to unify similar execution programs and improve the efficiency of manufacturing and maintenance operations. And a method for starting up a digital signal processor.

  In order to solve such a problem, according to one aspect of the present invention, a first data file that stores a plurality of execution programs for digital signal processing and a plurality of commands that respectively start the execution programs is stored. A CPU card having an external storage device, a CPU card for transferring the data file and notifying an activation command, an interface unit connected to the CPU card by a bus, and the data file received via the interface unit (2) an external storage device, a ROM for storing an initialization program, and a DSP card having a plurality of DSPs each having an internal memory, taking the execution program into the internal memory and generating and executing a given DSP program. And any DSP on this DSP card is blocked from the ROM. After the activation command is notified from the CPU, the activation command is issued to other DSPs in turn, and the other DSP sends the command included in the data file of the second external storage device. The digital signal processor system is characterized in that the execution program is read into the start address of the internal memory and the execution program is executed from the start address.

  Further, according to another aspect of the present invention, a first external storage device that stores a plurality of execution programs for digital signal processing and a data file that includes a plurality of commands for starting each of these execution programs, and A step of providing a CPU card having a CPU for transferring the data file and notifying the start command, an interface unit connected to the CPU card by a bus, and a second external unit for storing the data file received via the interface unit Providing a DSP card having a plurality of DSPs for storing a storage device, a ROM for storing an initialization program, each having an internal memory, generating the given DSP program in the internal memory and executing the given DSP program; Each DSP of the DSP card boots from the ROM. When the initialization program waits for an activation command, and when the initialization program of any DSP receives the activation command, the other DSP receives the command included in the data file of the second external storage device. The execution method of the digital signal processor is provided, comprising the step of sequentially reading the execution program into the start address of the internal memory based on the above and executing the execution program from the start address.

  According to the present invention, even if the shared memory base address and the number of input / output channels are different in spite of the same processing, it is possible to unify execution files, and the manufacture and maintenance thereof are facilitated.

1 is a configuration diagram of a signal processing system including a digital signal processor system according to an embodiment of the present invention. (A) is a figure which shows the file structure of the data file for boot, (b) is a figure which shows an example of character string data. It is a flowchart for demonstrating the boot method of a slave DSP. It is a flowchart for demonstrating the boot method of a master DSP. It is a 1st flowchart for demonstrating the boot control procedure with respect to the DSP card by host CPU. It is a 2nd flowchart for demonstrating the boot control procedure with respect to a DSP card by host CPU. It is a figure which shows the structural example of the conventional signal processing apparatus.

  Hereinafter, a digital signal processor system and a digital signal processor start-up method according to embodiments of the present invention will be described with reference to FIGS. In the drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.

  A digital signal processor system according to an embodiment of the present invention is a signal processing system, each of which includes a plurality of DSP cards provided with a plurality of DSPs, a CPU card provided with a CPU, and an I / O card. Is mounted on the backplane. In this signal processing system, each DSP card of each DSP card performs signal processing operations assigned to these DSPs on the input data input to any DSP card, thereby obtaining signal processing operation results. Output is performed from any other DSP card.

  The signal processing system is composed of a box-shaped chassis, a backplane provided on the back side of the chassis with a VME bus wired on the inner surface of the chassis, and arranged on the backplane at equal intervals on the surface. A plurality of connectors, a CPU card inserted into the leftmost connector of these connectors, and a plurality of connectors inserted into connectors other than the connector into which the CPU card is inserted It consists of a single DSP card.

  A space surrounded by the inner surface of the chassis ceiling plate, the inner surface of the bottom plate, each connector port, and the opening end surface on the front side of the chassis forms a slot, and a CPU card and a DSP card are inserted into each slot. By mounting the CPU card and each DSP card in the respective slots, the CPU card and the plurality of DSP cards are accommodated and connected to the VME bus.

  In addition, the digital signal processor startup method according to the present embodiment uses a single type of boot data file having the same data structure among a plurality of DSP cards, and the CPU uses a plurality of data on these DSP cards. This is a method for restarting the DSP. This boot data file includes an IPL (Initial Program Loader) which is a startup program, a plurality of DSP individual execution programs, and an argument which will be described later.

  The CPU sends a boot data file to each DSP card, one of the DSPs on the DSP card side calls another DSP, and after the other DSP completes booting, the processing is continued based on this argument. The transfer destination of the boot data file transferred by the CPU is one DSP card or a plurality of, for example, 20 DSP cards.

  FIG. 1 is a configuration diagram of a signal processing system. The signal processing system 1 includes N DSP cards 2 each executing a DSP program, a VME bus 3 to which the DSP cards 2 are connected, a host CPU 4 and an external storage device 5 ( CPU card 6 having a first external storage device). The signal processing system 1 is connected to an input / output IO card 8 that communicates with a control device 7 outside the system.

  The DSP card 2 is equipped with a flash memory, and reads an execution file for signal processing operation from the flash memory, and performs signal processing operations such as digital filter processing and FFT processing. The DSP card 2 is connected to N (N is 5 for example) DSPs 11 each having an internal memory 9 and a DMA controller 10, a first data bus 12 connected to each DMA controller 10, and the data bus 12. A bus protocol conversion function unit 13 (interface unit), an external storage device 15 (second external storage device) connected to the bus protocol conversion function unit 13 via a second data bus 14, and a bus protocol conversion function A flash ROM 17 (ROM) connected to the unit 13 via a third data bus 16 and a low-speed peripheral device 18 connected to the data bus 16 are provided. The DSP card 2 further includes a high-speed peripheral device 20 connected to the bus protocol conversion function unit 13 via the fourth data bus 19 and a VME-PCI bridge 21 connected to the data bus 19.

  The internal memory 9 of each DSP 11 has a small capacity storage area. The internal memory 9 inside these processors stores programs and data. The DSP 11 fetches the execution file into the internal memory 9 and executes it. The DMA controller 10 performs DMA transfer of data stored in the internal memory 9. DSP_1 to DSP_N represent N DSPs 11.

  The bus protocol conversion function unit 13 functions as a bus bridge between the data buses 12, 14, 16, and 19 having different bus widths and data transfer units and converting the data according to the protocol of these buses and then transferring the data. .

  The bus protocol conversion function unit 13 is provided with a plurality of registers (not shown). One of the registers holds card identification information. The card identification information is read and collected by the host CPU 4 via the VME bus 3. The host CPU 4 can identify the DSP card 2 based on the card identification information obtained from each DSP card 2.

  The external storage device 15 is a volatile storage device that stores software files from the host CPU 4. In the signal processing system 1, the external storage device 15 passes a boot program as a startup memory to each DSP 11. A large-capacity memory such as a page memory is used for the external storage device 15.

  The flash ROM 17 holds an initialization program for each DSP 11. Each program is transferred to each internal memory 9 by each DMA controller 10 when the DSP card 2 is powered on. In the present embodiment, the signal processing program is transferred from the CPU card 6 to the DSP card 2 and then distributed to the other DSPs 11 by the first DSP 11. Each DSP 11 performs arithmetic processing of the assigned DSP software according to the calculation instruction of the distributed program.

  The low-speed peripheral device 18 is a message output device. For example, the low-speed peripheral device 18 receives a parallel message output from each DSP 11 and outputs serial data of each message. The data bus 19 is a PCI bus. The high-speed peripheral device 20 performs data transfer at a high transfer rate. The VME-PCI bridge 21 performs interface processing between the VME bus 3 and the data bus 19.

  Since the DSP card 2 is composed of the same type of DSP 11 and a plurality of DSPICs, there are one or a plurality N of boot target DSPs 11. The configuration of the N DSP cards 2 is the same. These DSP cards 2 share the same VME backplane.

  The external storage device 5 of the CPU card 6 stores 5 × N execution files for the five DSPs 11 of the N DSP cards 2 and a program executed by the host CPU 4. As the external storage device 5, a memory having a large storage capacity is used. The application program stored in the external storage device 5 is a single type of DSP card 2 in which five execution files for the DSP 11 are collected together with an argument indicating the relative address position of these execution files. A boot data file is created, and the created boot data file is stored in the external storage device 5. This application program creates a boot data file in which execution files and arguments for five DSPs 11 on these DSP cards are collected for all the N DSP cards 2, and is stored in all the N DSP cards 2. To send.

  The application program also has functions of collecting various types of information on the N DSP cards 2 and notifying activation commands to the DSP cards 2. This application program collects card identification information of N DSP cards 2 and can output an activation command to all the DSP cards 2 mounted on the backplane.

  FIG. 2A is a diagram showing a file structure of a boot data file, and shows an example of a file transferred to any one DSP card 2. The boot data file 22 includes an area 23 for storing an execution file (execution program for digital signal processing) for each DSP 11, an IPL 24 common to all the DSPs 11, and an area 25 for storing command line arguments for each DSP 11. It is divided into and. Each command line argument functions as one of the commands for starting the execution program.

  Each execution file is stored in each sub area of the area 23. These execution files are codes for signal processing operations that are interpreted and executed by each DSP 11. The IPL 24 is a boot control program composed of a fixed number of bytes. The IPL 24 uses a program provided by a DSP manufacturer. Character string data is stored in each sub-region of the region 25. The character string represents a command given from the host CPU 4 to the DSP 11.

  FIG. 2B is a diagram illustrating an example of character string data, and character string data in the sub area for the 0th DSP 11 (DSP_0) in the area 25 is shown. In the figure, when the startup character string of the VME boot is, for example, “test −n 50 −b”, the address where each character in the startup character string is stored and the relative address of each character are shown. ing. “Test” is an execution file name (program name of an execution program). “-N 50 -b” is information specifying that a certain subroutine process is repeated 50 times, for example. One space is described from the executable file name. The activation character string includes the relative address of each execution file with respect to the leading address 0x00000000 in the boot data file 22. Each DSP 11 generates a DSP program from the execution file based on these execution file names and command line arguments.

  The host CPU 4 can process character data in units of 8 bits. Since the host CPU 4 can handle 1-byte character data one character at a time, the character data for 4 characters is stored in one arithmetic register having a 32-bit width and operated. Since the DSP 11 processes the data in units of 32 bits, the character data for the same four characters is stored in four arithmetic registers having a 32-bit width to perform the operation. In terms of specifications, the DSP 11 uses 8 bits on the LSB side of the 32-bit arithmetic register.

  In this embodiment, the host CPU 4 converts character string data into a format that can be directly read by the DSP 11 in advance. As shown in FIG. 2A, the host CPU 4 combines the converted character string data, the argument indicating the relative address position of each character string data, and the execution file for the DSP 11 into one boot data file. 22 is created. When the DSP card 2 receives the boot data file 22 from the host CPU 4 as an activation command, the DSP card 2 extracts arguments from the boot data file 22 and sequentially extracts and executes the character data existing at the relative address positions indicated by the arguments. I am doing so. As many DSPs 11 as the number of DSPs 11 can be given different arguments.

  In the source code of the program that can be executed by the DSP 11, unlike the host CPU 4, the bit width of the character variable is 32 bits. For this reason, the host CPU 4 converts the format of the command line argument from 8 bits to 32 bits, and stores the relative address data stored in the arvg area as a 32-bit word address combined with the DSP 11.

  argc and * argv [] are the same as the arguments used in the main function main () in the C language source code. argc is an integer type variable that stores the number of parameters input from the command line. * Argv [] is a character type pointer array for storing parameters input from the command line. An example of inputting an argument to the console will be described. When the execution file name is test, the number of parameters included in “test −n 50 −b” is “test”, “−n”, “50”, Since there are four “−b”, the value “4” is stored in argc. The address of the character string “test” is stored in the 0th (= argv [0]) of the array argv []. The first (= argv [1]) stores the address of the character string “−n”. The address of the character string “50” is stored in the second (= argv [2]). The address of the character string “−b” is stored in the third (= argv [3]).

  In the signal processing system 1 according to the present embodiment, * argv [0] indicates the address of the first character “t” in the character string “test”. The address of the character “t” is represented by a relative address starting from argc. Relative addresses are specified in words. The command line argument data set by the user is extended from the 8-bit width to the 32-bit width in the host CPU 4, and the command line argument data having the 32-bit width is interpreted by the DSP 11. By implementing a function for interpreting this description on the DSP card 2 side, the signal processing system 1 is made to realize a parameter passing function in the same manner as in the case where a file name and an argument are input to the console. .

  Also, in the digital signal processor startup method according to this embodiment, each DSP 11 performs ROM boot on the DSP card 2 side, the initialization program waits for a startup command, and the initialization program of the first DSP 11 issues a startup command. Upon receipt, each of the other second to Nth DSPs 11 sequentially reads the execution file into the top address of the internal memory 9 and executes this execution program from this top address.

  An operation flowchart for restarting the first DSP 11 (DSP_1) to the Nth DSP 11 (DSP_N) in the DSP card 2 of the signal processing system 1 according to the present embodiment having the above-described configuration is shown in FIGS. To explain. In the signal processing system 1, the first DSP 11 functions as a master DSP, and the second DSP 11 to the N-th DSP 11 function as slave DSPs. For example, when the DSP 11 itself reads the logical values of a plurality of IC pins provided in five DSP ICs, each DSP 11 operates as a master or a slave. FIG. 3 shows a boot method from the second DSP 11 (DSP_2) to the N-th DSP 11.

(1) Each Boot Method of Second DSP 11 to Nth DSP 11 FIG. 3 is a flowchart for explaining a boot method of the second DSP 11. In step A1, power is turned on to the second DSP 11. In step A 2, as shown in FIG. 1 (1), the DSP 11 loads an initial setting program from the flash ROM 17 into the internal memory 9.

  In step A3, the second DSP 11 waits for an activation command issued by the first DSP 11. At this time, the second DSP 11 performs neither access to the data bus 12 nor access to the external storage device 15. While the second DSP 11 does not receive the start command, the NO route is taken and the DSP 11 continues to wait.

  When the second DSP 11 receives the start command from the first DSP 11 in step A3, the YES route is passed. In step A4, the second DSP 11 sends the external storage device 15 to the external storage device 15 as shown in FIG. The stored program is read into the internal memory 9. The second DSP 11 jumps to the read first address and executes the program.

  The second DSP 11 makes preparations before reading the program. That is, the transfer completion interrupt vector of the DMA controller 10 is set at the head address of the internal memory 9 in order to transfer its own execution to the program read by the second DSP 11. Also, the second DSP 11 temporarily stops its own operation. When this preparation is completed, the second DSP 11 activates the DMA controller 10 and puts itself into a stopped state. The DMA controller 10 transfers the program to the internal memory 9 according to the setting. When the transfer is completed, the DMA controller 10 sets the transfer completion interrupt vector at the head address of the internal memory 9. In response to the DMA transfer completion interrupt, the second DSP 11 restarts the program.

  In step A5, when the second DSP 11 executes a new program, it acquires argument data from the address of the command line argument area provided in the storage area of the external storage device 15, and performs processing according to the contents of the argument data. Execute.

  The boot method of the third DSP 11 to the N-th DSP 11 is the same as the boot method of the second DSP 11.

  As described above, the startup method in each of the second to N-th DSPs 11 is such that the ROM booted program reads the program to be executed subsequently into the head address of the internal memory 9 for storing the program, and then starts from the head address. The next program is read and executed. The program storage area inside these processors is effectively used.

(2) Boot Method of the First DSP 11 (DSP_1) FIG. 4 is a diagram for explaining the boot method of the first DSP 11. In step B1 of FIG. 4A, power is turned on to the first DSP 11 as the master. In step B2, the DSP 11 reads the program from the flash ROM 17 and starts it as shown in FIG. After the activation, in step B3, an activation command issued by the CPU card 6 is waited. At this time, the DSP 11 does not access either the data bus 12 or the external storage device 15. In step B3, while the first DSP 11 does not receive the start command, the NO route is taken and the standby is continued.

  On the other hand, due to the bus protocol conversion function of the bus protocol conversion function unit 13, the CPU card 6 is a data bus to which the CPU card 6 itself belongs without being conscious of the external storage device 15 of the DSP card 2 and the bus in the DSP card 2. A program and command line argument data are transferred using a certain VME bus 3. When the transfer of the program and command line argument data is completed, the CPU card 6 outputs a start command to the first DSP 11 as shown in FIG.

  In step B3, when the first DSP 11 receives the start command, the YES route is passed, and the process proceeds to step B4, where N execution files 23, one IPL 24 (program part), N command line arguments, Are copied to N predetermined storage areas of the external storage device 15. The first DSP 11 stores the address value of the storage area to which the execution file 23 and the command line argument are copied for each of the N DSPs 11.

  In step B5, the first DSP 11 adds the address value after transfer to the external storage device 15 to the relative address of argv [0] to argv [N] indicated by the command line argument data. The first DSP 11 adds N address values to the N relative addresses, thereby calculating and setting N absolute addresses that can be accessed by the N DSPs 11 respectively.

  Thereafter, in step B6 of FIG. 4B, the first DSP 11 sets the repetition variable i (i <N) to the DSP number N, and in step B7, the first DSP 11 reboots the i-th DSP 11. It is determined whether or not it is the DSP 11 to be processed. If the i-th DSP 11 is the DSP 11 to be rebooted, the first DSP 11 issues a start command to the i-th DSP 11 through the YES route in step B8. The DSP 11 that is not the reboot target passes through the NO route in step B7 and proceeds to step B9.

  In step B8, as shown in FIG. 1 (4), the first DSP 11 outputs a start command to the other DSP 11 in the DSP card 2. At this time, since each of the second to Nth DSPs 11 is not accessing either the data bus 12 or the external storage device 15, the exclusive control of the data bus 12 is performed when the first DSP 11 outputs an activation command. There is no need to consider.

  Each of the second to N-th DSPs 11 receives the activation command from the first DSP 11 and then reads the program stored in the external storage device 15 into each internal memory 9 as shown in FIG. Each of the second to Nth DSPs 11 takes in each executable file as a program. Each of the second to Nth DSPs 11 jumps to each read start address and executes the program. Each of the second to Nth DSPs 11 acquires argument data from the address of the command line argument area 25 provided in the storage area of the external storage device 15, and executes processing according to the contents.

  Finally, in step B10, as shown in FIG. 1 (5), the first DSP 11 reads the program stored in the external storage device 15 into its own internal memory 9, jumps to the read first address, and executes the program. Execute.

  The reading of the program by the first DSP 11 uses the DMA controller 10 built in the DSP 11 and temporarily stops the DSP 11 itself. Further, the first DSP 11 sets the transfer completion interrupt vector of the DMA controller 10 at the head address of the internal memory 9 in order to cause the read program to execute itself. When this preparation is completed, the first DSP 11 activates the DMA controller 10 and puts the DSP 11 itself into a stopped state. The DMA controller 10 transfers the program to the internal memory 9 according to the setting. In response to the DMA transfer completion interrupt, the first DSP 11 restarts the program.

  In step B <b> 11, the first DSP 11 acquires argument data from the address of the area 25 in the external storage device 15 and executes processing according to the contents, as with the other DSPs 11.

  As described above, the start-up method in the first DSP 11 is such that the ROM booted program reads the program to be subsequently executed into the top address of the internal memory 9, and then reads and executes the next program from the top address. Do. The program storage area inside the processor is effectively used.

(3) Activation Method of DSP Card 2 by CPU Card 6 A control method for the CPU card 6 to activate the DSP card 2 will be described with reference to FIGS. 5 and 6 are flowcharts for explaining a boot control procedure for the DSP card 2 by the host CPU 4.

  The process is started in FIG. Since the host CPU 4 also needs to execute necessary processing such as setting of its own hardware, the host CPU 4 starts up from the ROM 6a of the CPU card 6 and performs necessary processing.

  In step C1, the host CPU 4 determines whether to start booting. As an example, booting is started by outputting a boot command at a timing determined in a sequence designed in advance. Alternatively, the boot is started when the application program issues a boot command based on a human operation. If the timing condition is not satisfied, the host CPU 4 continues to wait (NO route of step C1). When the host CPU 4 determines that the timing condition is satisfied, the host CPU 4 starts to boot the DSP card 2 through the YES route.

  In the following steps C3 to C6, the CPU card 6 converts character string data indicating command line arguments, which is stored in the external storage device 5 in advance, into a format that can be directly read by all the DSPs 11. The format conversion software is stored in the external storage device 5 of the CPU card 6 in advance. In step C2, the host CPU 4 sets the repetition variable j (j <N) to 20 for example.

  Next, in step C <b> 3, the host CPU 4 reads program data j from the data area of the external storage device 5. In step C4, the host CPU 4 reads command line argument data j from the data area. In step C5, the host CPU 4 converts the character string data into command line arguments in a data format that can be received by each DSP 11. Thereafter, in step C6, as shown in FIG. 2, the host CPU 4 creates a boot data file 22 in which the converted character string data and the DSP 11 execution file program are combined into one. In step C7, the repetition variable i is set to the number of cards of the DSP card 2. In step C8, as shown in FIG. 1B, the host CPU 4 transfers the boot data file 22 as program data j to the external storage device 15 in the DSP card 2 via the VME bus 3. In step C9, the repetition variable i is incremented.

  The boot data file 22 is written in the external storage device 15 via the high-speed peripheral device 20 in the DSP card 2.

  Further, due to the bus protocol conversion function of the bus protocol conversion function unit 13, the CPU card 6 is unaware of the external storage device 15 of the DSP card 2 and the bus in the DSP card 2, and the bus protocol conversion function unit 13 itself belongs to it. The program can be transferred using the data bus 19 or the data bus 16.

  Subsequently, when the transfer of the boot data file 22 is completed, the host CPU 4 sets the repetition variable i as the number of DSP cards 2 in step C10 of FIG. 6A, and in step C11, FIG. As shown in (3), an activation command is output to the first DSP 11. In step C12, the host CPU 4 performs the increment process, and then returns to step C10 to notify the start command to all the DSP cards 2.

  In the processing from step C13 to step C15 below, the host CPU 4 acquires from the DSP cards 2 answers that the DSP cards 2 output when booting is completed. The host CPU 4 sets the number of DSP cards 2 to the variable i (step C13), and determines whether or not the i-th DSP card 2 has been booted (step C14). If the boot is unsuccessful, the NO route is passed, and if the boot is successful, the YES route is taken (step C15).

  The application program of the host CPU 4 issues a command so that the completion of the program transfer from the host CPU 4 to the DSP card 2 and the reboot start command from the host CPU 4 to the DSP card 2 are continuous in time. When the five DSPs 11 are rebooted, the host CPU 4 has completed the access to the data bus 2, so that the reboot is performed without any problem. These processes can be repeated according to the number of programs used for booting. The iterative process corresponding to step C2 in FIG. 5A ends in step C16 in FIG. 6B.

  Finally, in step C17 of FIG. 6B, the host CPU 4 starts itself and executes processing.

  To summarize the above, the host CPU 4 obtains the number of cards of each DSP card 2 mounted in the chassis in advance from the card identification information, and creates a boot data file created with one execution file and one command line argument. Transfer to each slot. The five DSPs 11 on each DSP card 2 load the initialization program before receiving the activation command, complete the initialization process, and wait for the activation command from the host CPU 4 to be notified. When the master DSP 11 receives the start notification command, the master DSP 11 reads the boot data file 22 of the external storage device 15 and generates storage addresses for five execution files based on the arguments, and all the DSPs 11. Is converted to executable file data in a format that can be interpreted. The master DSP 11 rearranges the five executable file data and issues a start command to the slave DSP 11. As a result, all the DSPs 11 are activated.

  Similarly, for all the DSP cards 2 installed in the chassis of the signal processing system 1, the host CPU 4 transfers the boot data file 22 and issues a start start command. Thereby, all the DSP cards 2 are activated. After confirming that all the DSP cards 2 are activated, the host CPU 4 starts card processing necessary for the CPU card 6 itself. In this way, the signal processing system 1 starts up and the mode of the signal processing system 1 becomes the operation mode. In this state, the signal processing system 1 performs signal processing operations such as digital filter processing and FFT processing.

  For example, the signal processing system 1 used as an industrial device may have a DSP configuration in which several tens of chassis are connected to each other and hundreds of DSP cards 2 are connected. After creating a calculation program and a startup program for the DSP 11 mounted on each DSP card 2, when these programs are securely mounted on all the DSPs 11, all the DSP cards can be obtained by using only one type of software. The work efficiency of the test and confirmation work of 2 can be greatly improved. It is possible to realize a mechanism in which arguments for each DSP 11 are described in advance in one type of software, this software is collectively supplied from the CPU 4 to all the DSP cards 2 and the processing is branched on these DSP cards 2. .

  According to the signal processing system 1 according to the present embodiment, since the software is integrated, the enable / disable enable process of the input channel is described individually in the software by the card number of the DSP card 2. You can also. As a result, the manufacturing cost can be reduced by the DSP activation system.

  As described above, according to the digital signal processor system and the digital signal processor start-up method according to the present embodiment, each host DSP 4 sharing the same VME backplane as the DSP card 2 can execute each of the target DSP cards 2. It becomes possible to give DSP 11 command line arguments and execution files to the DSP 11.

  For this reason, by using one type of execution program and different command line arguments, various processes such as complicated peripheral device setting processing and creation of a large amount of initial value data used for calculation can be selectively executed. become. In addition, since the number of execution program types is minimized, manufacturing and maintenance management can be saved.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. The character string data in the above embodiment can be variously changed.

  In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.

  DESCRIPTION OF SYMBOLS 1 ... Signal processing system (digital signal processor system), 2 ... DSP card, 3 ... VME bus, 4 ... Host CPU (CPU), 5 ... External storage device (1st external storage device), 6 ... CPU card, 6a ... ROM, 7 ... control device, 8 ... IO card, 9 ... internal memory, 10 ... DMA controller, 11 ... DSP, 12, 14, 16, 19 ... data bus, 13 ... bus protocol conversion function unit (interface unit), 15 ... external storage device (second external storage device), 17 ... flash ROM (ROM), 18 ... low-speed peripheral device, 20 ... high-speed peripheral device, 21 ... VME-PCI bridge, 22 ... boot data file, 23, 25 ... Area, 24 ... IPL.

Claims (4)

A first external storage device that stores a plurality of execution programs for digital signal processing and a data file that includes a plurality of commands for starting each of these execution programs, and a CPU for transferring the data file and notifying a start command A CPU card having
An interface unit bus-connected to the CPU card, a second external storage device that stores the data file received via the interface unit, a ROM that stores an initialization program, and an internal memory, respectively, A DSP card having a plurality of DSPs for taking an execution program and generating and executing a given DSP program;
When any DSP of this DSP card boots from the ROM and is notified of the start command from the CPU, it issues a start command to other DSPs in turn, and the other DSP A digital signal processor system, wherein the execution program is read into a head address of the internal memory based on the command included in the data file of a storage device, and the execution program is executed from the head address. The command of the data file includes a program name of the execution program and a command line argument given to the execution program,
2. The digital signal processor system according to claim 1, wherein the other DSP generates the DSP program from the execution program based on the program name and command line arguments. A first external storage device for storing a plurality of execution programs for digital signal processing and a data file including a plurality of commands for starting each of these execution programs, and a CPU for transferring the data file and notifying a start command Providing a CPU card having:
An interface unit bus-connected to the CPU card, a second external storage device that stores the data file received via the interface unit, a ROM that stores an initialization program, and an internal memory, respectively, Providing a DSP card having a plurality of DSPs for capturing an execution program and generating and executing a given DSP program;
Each DSP of the DSP card boots from the ROM and the initialization program waits for an activation command;
When the initialization program of any DSP receives an activation command, the other DSPs sequentially transfer the execution program to the start address of the internal memory based on the command included in the data file of the second external storage device. A method for starting up a digital signal processor, comprising: reading and executing the execution program from the head address. The command of the data file stored in the first external storage device in the step of providing the CPU card includes a program name of the execution program and a command line argument given to the execution program,
4. The digital signal processor according to claim 3, wherein in the step of executing the execution program, the other DSP generates the DSP program from the execution program based on the program name and command line arguments. Startup method.

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