JPH09146901A - Program transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a failure in program transfer to one DSP(digital signal processor) from affecting the transfer of a program to another DSP and transfer the program through a single process when plural DSPs require the same program. SOLUTION: A CPU 2 reads a program for a DSP 5 out of a ROM 3 and makes the DSP 5 execute it. The CPU 2 reads a program to be transferred this time among programs for DSPs 71-7n out of a ROM 3 and transfers this program and transfer destinations of the program to the DSP 5. The DSP 5 outputs the program to a serial data bus 9 in synchronism with load pulses. The DSPs specified as the transfer destinations among the DSPs 71-7n input the program from the serial data bus 9 at the same time in synchronism with the load pulses. Those are repeated to transfer programs to all the DSPs 71-7n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program transfer system, and more particularly to a program transfer system in an apparatus having a plurality of processors.

[0002]

2. Description of the Related Art A transmitter / receiver in a base station of a mobile communication system has a large amount of processing due to the development of information society in recent years and receives signals from a plurality of antennas in parallel. It has a digital signal processor (hereinafter referred to as DSP) and operates by operating them in parallel. These DSPs
Since the program is executed on a volatile memory such as a RAM inside the DSP, it does not have a program for controlling itself in advance. Therefore, a program for controlling these DSPs is externally acquired when the power supply of this device is turned on. There is a need. For this reason, various program transfer methods have been conventionally proposed.

FIG. 4 is a block diagram showing a conventional program transfer system.

In the system shown in the figure, the ROM 42 for storing a plurality of programs for controlling the plurality of DSPs and the RO
The CPU 41 that reads the program from the M42 and outputs the program and the transfer destination of the program, the DSP (DSP441 to DSP44n) of the first layer that is the transfer destination of the program and performs high-speed arithmetic processing, the CPU 41 and the First layer dual port RAM (hereinafter referred to as DPRAM) (DPRAM 431) provided between the first layer DSP and for transferring data such as programs.
To DPRAM 43n) and a DSP (DSP4) of the second layer which is a transfer destination of the program and performs high-speed arithmetic processing.
71 to DSP 47n), and a second layer DPRAM (DPRAM 461 to DPRAM 46n) provided between the first layer DSP and the second layer DSP for transferring data such as programs.

In this conventional program transfer system, the CPU 41 transfers from the ROM 42, which stores programs used by all DSPs in the transmitter / receiver 49, to one of the first layer DSPs. Read the program and run this program on the first layer DPR
Transfer to the DPRAM corresponding to the DSP of AM. This operation is performed for all DSPs in the first layer DSP, and all DPRs in the first layer DPRAM are performed.
Transfer the program to be transferred to the AM.

Next, a reset release signal is output to the reset control line 45 to release the reset of all the DSPs in the first layer to activate these DSPs. The activated DSPs of the first layer read the programs from the respective DPRAMs of the corresponding first layer and execute these programs.

Next, the CPU 41 controls the D of the second layer.
A program to be transferred to one of the SPs is read from the ROM 42, and this program is associated with the one DSP of the first layer DPRAM.
Transfer to AM. The DSP of the first layer corresponding to the one DSP reads the transferred program from the DPRAM of the first layer, transfers the program to the DPRAM of the second layer corresponding to the one DSP, and outputs a reset release signal. It outputs to the reset control line (corresponding reset control line of the reset control line 481 to the reset control line 48n) corresponding to the one DSP to release the reset of the one DSP and activate the DSP. The one DS
P is a corresponding DPRA of the second layer DPRAM.
The program is read from M and this program is executed. Perform these operations on all D's of the second layer DSP.
The operation is performed on the SP, and the programs corresponding to these DSPs are executed to start the operation of the transmission / reception device 49.

[0008]

In the above-mentioned conventional program transfer method, the CPU 41 causes the DSP of the first layer to operate.
For transferring a program to each DSP of the second layer DSP via each DSP of the first layer DSP that has been activated, When the transfer of the program fails, the DSP in the second layer DSP following the failed DSP
Program is not transferred to. Also, when a plurality of DSPs of the first layer DSP and the second layer DSP require the same program, the CPU 41 causes the respective DSPs of the plurality of DSPs to have the same program.
Since it is necessary to individually transfer the same program to the SP, there is a problem that efficiency is poor and it takes time to transfer the program.

The object of the present invention is to eliminate such a conventional defect, so that even if the transfer of a program to one DSP fails, the program can be transferred to another DSP, and a plurality of DSPs can be transferred. It is an object of the present invention to provide an efficient program transfer method capable of transferring a program in a single process when the same program is required, and which does not require a long program transfer time.

[0010]

A program transfer method of the present invention is a program transfer method for transferring a program used by the processor in an apparatus having a plurality of processors to these processors, wherein the plurality of programs to be transferred are And a first processor for reading one program of the plurality of programs from the storage means and outputting the read program and the transfer destination of the program, and the first processor By receiving a predetermined program of the plurality of programs and executing it, a program other than the predetermined program and a transfer destination of this program are received from the first processor, and this reception is performed. To the processor indicated by the destination of the transferred program A second processor for outputting a program, is configured to include a plurality of processors to start normal operation, a by the second receiving the program output from the processor the program.

Further, in the program transfer method of the present invention, when one of the plurality of programs stored in the storage means is used by some of the plurality of processors, The one program is simultaneously output from the second processor to the some processors, and the some processors simultaneously receive the one program output from the second processor.

Further, the second processor of the program transfer system of the present invention and the plurality of processors are connected by a serial data bus.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the program transfer system of the present invention.

In the present embodiment shown in FIG. 1, in a program transfer system in which a program used by the processor in a transmitter / receiver 1 having a plurality of processors is transferred to these processors, the plurality of programs to be transferred are previously stored. For example, a storage means 3 such as a ROM for storing (hereinafter referred to as RO
M3), the first program 2 for reading the program from the ROM 3 and outputting the read program and the transfer destination of the program, and the high-speed arithmetic processing by receiving the program. A second processor 5 (hereinafter referred to as DSP5) such as a digital signal processor for executing the above, and the ROM
3 and the DSP 5 are provided between the dual port RAM 4 for transferring data such as programs (hereinafter referred to as DPRA).
M4), and a plurality of processors (hereinafter DSP 71 to DS) that receive the program and execute high-speed arithmetic processing and the like, respectively.
P7n), a transfer control unit 6 provided between the DSP 5 and the DSP 71 to DSP 7n for displaying the transfer destination of the program and controlling transfer of the program, and the DSP 5 and the DSP 71 to DSP 7n. And a serial data bus 9 that is connected and transfers the program.

Next, the operation of the program transfer method of the present invention will be described in detail with reference to FIGS.

FIG. 2 is a flow chart showing an example of the operation of this embodiment.

FIG. 3 is a diagram showing the operation of the serial data bus 9, showing the timing of the output of data from the DSP 5 and the input of data to the DSP of the DSP 71 to DSP 7n that has been reset. Also, the DSP 161 of AT & T Co. is used as the DSP.
An example using 0 is shown. The bus 9 is provided with two signal lines for a load pulse, which is a signal for synchronizing the start of data transfer, and an operation clock, which is a synchronizing signal for outputting or inputting data bit by bit, and DataOutput. And one data line for DataInput. The operation clock is output from the transfer control unit 6 from the time when the power of the transmission / reception device 1 is turned on. Similarly, the load pulse is output from the transfer control unit 6 in response to a load pulse generation instruction from the DSP 5. When the transfer controller 6 receives a load pulse generation instruction from the DSP 5 and outputs the load pulse to the serial data bus 9, the DSP 5 starts an output operation in synchronization with the load pulse, and outputs the operation clock of the operation clock. Data is output to the data line bit by bit for each cycle. On the other hand, the DSP
The DSP that has been reset from 71 to DSP 7n
Executes an internally stored program, starts an input operation in synchronization with the load pulse output to the serial data bus 9, and outputs the data line by one bit for each cycle of the operation clock. Enter the data from. By performing the above-mentioned operations, the program to be transferred is from DSP5 to DSP71 to DSP7.
It is simultaneously transferred to a plurality of DSPs whose reset has been released. Although FIG. 3 shows an example in which 16-bit data is transferred, 8 bits, 32 bits, 64 bits, etc. may be used and it is not necessary to be particular about the number of bits. In addition, D
Although an example in which the DSP 1610 manufactured by AT & T Co. is used as the SP is shown, other than this DSP may be used.

In FIG. 2, when the transmitter / receiver 1 is turned on, the CPU 2 performs an initialization process such as a read / write inspection and a clear of the DPRAM 4 for transferring data such as the program (S).
1), the program for the DSP 5 is read from the ROM 3 and transferred to the DPRAM 4 (S2), and a reset release signal is output to the reset control line 8 to output the DSP 5
The reset of is canceled (S3). The DSP 5 released from the reset by the reset release signal executes the program stored in advance,
The program on the DPRAM 4 transferred in (S2) is read (S4), the program is executed, normal control is started, and the control is started.
To the DPRAM to notify the control start
4 (S5). The CPU 2 uses the DPRA
The state of "control start" is read from M4 and the DSP5
(S6), the program to be transferred this time among the programs for DSP71 to DSP7n stored in advance in the ROM3 is read from the ROM3, and this program and the transfer destination of this program are stored in the DPRAM4. Transfer (S7). The DSP 5 reads the transferred program and the transfer destination of the program from the DPRAM 4, and transfers the transfer destination of the program to the transfer control unit 6 (S8). The transfer control unit 6
Receives the transfer destinations of the program, displays the transfer destinations, outputs a reset release signal to the reset control line 10 to the DSPs indicated by these transfer destinations, and releases the reset of the DSP (S9).

Next, the DSP 5 transfers an instruction to generate the load pulse to the transfer control unit 6 in order to transfer the program acquired in step 8 (S8) to the DSP whose reset has been released. Yes (S10).
The transfer controller 6 receives the load pulse generation instruction and outputs the load pulse to the serial data bus 9 (S11). The DSP 5 outputs the program to the serial data bus 9 at the timing shown in FIG. 3 in synchronization with the load pulse output to the serial data bus 9 (S12).

Further, the DSP whose reset has been released in step 9 (S9) executes the program stored therein beforehand, and is synchronized with the load pulse output to the serial data bus 9 as shown in FIG. The program is input from the serial data bus 9 at the indicated timing (S
13) After the input of this program is completed, this program is executed to start normal control (S14).

On the other hand, the DSP 5 transfers the program to the DSP whose reset has been released, and then executes the C
In order to report the end of transfer of the program to PU2, the state of "program transfer end" is set in the DPRAM.
4 (S15).

From the DPRAM4, the CPU 2 "
It is confirmed that the transfer is completed by reading the state of "program transfer completed" (S16), and the DSP 71 to DSP
It is checked whether or not the program transfer to all 7n DSPs has been completed (S17), and if there is a DSP for which the program transfer has not been completed, the above step 7 (S
Go to 7) and continue control. If the transfer of the program has been completed for all DSPs, the program transfer operation is completed.

[0024]

As described above, according to the program transfer method of the present invention, each DSP of the DSP 71 to DSP 7n is connected to the DSP by the serial data bus 9.
Since it is directly connected to 5, DSP71 to DS
When one DSP of P7n fails to receive the program, it does not affect the transfer of the program to another DSP, and further, when a plurality of DSPs of the DSP 71 to DSP 7n require the same program. Outputs the program from the DSP 5 to the serial data bus 9 so that the plurality of DSPs simultaneously input the program from the serial data bus 9. Therefore, the program can be transferred in one process, and the program can be transferred. It doesn't take long.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a program transfer system of the present invention.

FIG. 2 is a flow chart showing an example of the operation of the present embodiment.

FIG. 3 is a diagram showing an operation of a serial data bus.

FIG. 4 is a block diagram showing a conventional program transfer system.

[Explanation of symbols]

 1 Transmitter / Receiver 2 First Processor (CPU) 3 Storage Means (ROM) 4 Dual Port RAM (DPRAM) 5 Second Processor (DSP) 6 Transfer Controller 71 to 7n Processor (DSP) 8 Reset Control Line 9 Serial Data Bus 10 Reset control line 41 CPU 42 ROM 431 to 43n DPRM 441 to 44n DSP 45 Reset control line 461 to 46n DPRM 471 to 47n DSP 481 to 48n Reset control line 49 Transceiver

Claims (5)

[Claims] 1. A program transfer method for transferring a program used by the processor in an apparatus having a plurality of processors to these processors, a storage unit for storing the plurality of programs to be transferred in advance, and the plurality of programs. A first processor that reads one of the programs from the storage means and outputs the read program and a transfer destination of the program; and a predetermined program of the plurality of programs from the first processor. By receiving and executing a program other than the predetermined program and a transfer destination of the program from the first processor, and receiving the program to the processor indicated by the transfer destination of the received program. A second processor that outputs the A program transfer method comprising: a plurality of processors that receive the program output from the second processor and start normal operation by the program. 2. When one program of the plurality of programs stored in the storage means is used by some of the plurality of processors, the one of the plurality of processors is used by the second processor. The program transfer according to claim 1, wherein a program is simultaneously output to the some processors, and the some processors simultaneously receive the one program output from the second processor. method. 3. The program transfer system according to claim 1, wherein the second processor and the plurality of processors are connected by a serial data bus. 4. A transfer control means for displaying a transfer destination of the program to be transferred and controlling transfer of the program to be transferred is provided between the second processor and the plurality of processors. The program transfer method according to claim 1, 2, or 3. 5. The program transfer system according to claim 1, wherein the second processor and the plurality of processors are processors capable of high-speed arithmetic processing.