JPH08123774A - Method and equipment for communication - Google Patents

Abstract

PURPOSE: To improve communication efficiency between microcomputers and to reduce the load of the microcomputers. CONSTITUTION: Data for 32 bytes at maximum are supplied from a RAM 3 in a mechanical computer 1 to a buffer RAM 2a in a serial interface unit 2 and data for 32 bytes at maximum are supplied from a RAM 13 in a mode computer 11 to a butter RAM 12a in a serial interface unit 12. The data in the RAM 2a are transferred from a shift register 2b to a shift register 12b and written in the RAM 12a synchronously with a CSK signal supplied from the computer 11 to the computer 1 based upon the decay of a CS signal supplied from the computer 11 to the computer 1 and the data in the RAM 12a are transferred from the register 12b to the register 2b and written in the RAM 2a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication method and apparatus suitable for use in, for example, a serial interface unit that executes communication between microcomputers.

[0002]

2. Description of the Related Art Conventionally, a serial interface unit built in a microcomputer performs communication with other microcomputers in a FIFO (first-in first-out) format and has a size of 8 bytes per communication. It is designed to be able to send and receive data.

That is, data stored in, for example, a RAM incorporated in a microcomputer is read in units of 8 bytes, and FI
It is supplied to the FO buffer. This FIFO buffer is
Data of up to 8 bytes can be stored, and the data supplied first is output in order and supplied to other microcomputers.

Therefore, the data transmitted between the microcomputers is 8
If it is within the byte, data can be transmitted and received between the microcomputers in one communication.

[0005]

However, if the size of the data to be transmitted / received by the communication between the microcomputers is larger than 8 bytes, the communication between the microcomputers must be repeated a predetermined number of times, and the processing is complicated. There was a problem that became.

The present invention has been made in view of the above circumstances, and it is possible to transmit and receive 32 bytes of data by one communication between microcomputers.

[0007]

A communication method according to a first aspect of the present invention is a communication method for performing data communication between a plurality of microcomputers that store predetermined data and execute a predetermined job. When a predetermined timing signal whose electric potential changes is generated and the electric potential of the timing signal changes, when the data communication is not performed between the microcomputers, the predetermined data stored in the first microcomputer among the microcomputers is changed to The N-byte unit is serially transferred to the second microcomputer among the microcomputers, and the predetermined data stored in the second microcomputer is serially transferred to the first microcomputer in the N-byte unit, and the transfer is completed. Then, the first microcomputer reads the predetermined data of the second microcomputer transferred from the second microcomputer by the first job of the first microcomputer. Next, the predetermined data to be transferred to the second microcomputer is set in the first microcomputer, and after the transfer is completed, the second microcomputer transfers the first data at a predetermined timing in the second microcomputer. The predetermined data of one microcomputer is read out, and the predetermined data to be transferred to the first microcomputer is set in the second microcomputer next.

Data transfer between the first microcomputer and the second microcomputer can be performed by the DMA method.

This transfer can be performed in units of 32 bytes.

According to a fourth aspect of the present invention, there is provided a communication device which stores predetermined data and performs data communication between a plurality of microcomputers which execute a predetermined job. When data communication is not performed when the potential of the timing signal generated by the timing signal generating means (for example, the serial interface unit 12 in FIG. 1) and the timing signal generating means for generating the timing signal changes, The predetermined data stored in the first microcomputer among the microcomputers is serially transferred to the second microcomputer among the microcomputers in units of N bytes, and the predetermined data stored in the second microcomputer is transferred to the first microcomputer. Transfer means for serially transferring to the microcomputer in units of N bytes (for example, shift registers 2b and 1 in FIG. 1)
2b), and after the transfer by the transfer means is completed, the first job of the first microcomputer reads the predetermined data of the second microcomputer transferred from the second microcomputer, and then the second microcomputer. The predetermined data to be transferred to the first microcomputer is set in the first microcomputer, and after the transfer is completed, the second data is transferred to the second microcomputer.
In the microcomputer, the predetermined data of the first microcomputer transferred from the first microcomputer is read at a predetermined timing, and the predetermined data to be transferred to the first microcomputer is set in the second microcomputer. Data setting means (for example, the buffer RAMs 2a and 12a in FIG. 1).

The transfer means may transfer the data between the first microcomputer and the second microcomputer by the DMA method.

The transfer means can transfer predetermined data in units of 32 bytes.

[0013]

In the communication method or device according to the present invention, predetermined data are mutually transferred in 32-byte units between the microcomputers in accordance with a predetermined timing signal. Therefore, data of 32 bytes or less can be transmitted / received in one communication between the microcomputers.

In the communication method or apparatus according to the present invention, the data transfer between the microcomputers is performed by the DMA.
Method. Therefore, the load on the microcomputer can be reduced.

In the communication method or apparatus according to the third or sixth aspect, data transfer between the microcomputers is performed in units of 32 bytes. Therefore, efficient data transfer can be performed.

[0016]

1 is a block diagram showing the configuration of an embodiment of a serial interface unit to which a communication device of the present invention is applied. The serial interface unit (serial interface) 2 operates according to a predetermined control program and has a predetermined timing signal (CS
(Chip Select) signal, however, in FIG. 1, a CS terminal to which a bar is attached above the character string CS and an SCK (serial clock) signal (FIG. 1) are input.
In, a bar is attached to the upper part of the character string SCK)
Is provided with an SCK terminal for inputting / outputting, a SI terminal for inputting predetermined data serially, and an SO terminal for outputting predetermined data serially.

In the serial interface 2, the buffer RAM 2a is adapted to store 32 bytes of predetermined data. Shift register 2b
Stores the data serially (in 1-bit units) supplied from the SI terminal, and outputs the data stored therein serially via the SO terminal. Further, the data stored therein is supplied to the buffer RAM 2a in 8-bit units via the bus 2c, or predetermined data is input from the buffer RAM 2a in 8-bit units via the bus 2c. Has been done.

The serial interface 2 having such a structure constitutes a microcomputer (mechanical computer) 1 for performing mechanical control, and by temporarily writing the data stored in the RAM 3 incorporated in the mechanical computer 1 into the buffer RAM 2a,
The data is output from the SO terminal, or the data input from the SI terminal is loaded into the buffer RAM 2a and directly accessed to be read out to the RAM 3 (DMA (direct memory access) method).

The serial interface 12 operates according to a predetermined control program and outputs a CS signal.
It has one terminal, an SCK terminal for inputting / outputting an SCK signal, an SI terminal for serially inputting predetermined data, and an SO terminal for serially outputting predetermined data.

In the serial interface 12, the buffer RAM 12a is adapted to store 32 bytes of predetermined data. The shift register 12b stores the data serially supplied from the SI terminal, and stores the data stored therein in the SO
It is designed to output serially through the terminal.
Further, the data stored therein is supplied to the buffer RAM 12a in 8-bit units via the bus 12c, or predetermined data is input from the buffer RAM 12a in 8-bit units via the bus 12c. Has been done.

The serial interface 12 is a microcomputer (mode) which performs a process related to a human interface, for example, a key operated by a user is detected and a predetermined process is performed in a corresponding mode (fast forward, reproduction, rewind mode, etc.). 11), and mode con 11
By temporarily writing the data stored in the built-in RAM 13 in the buffer RAM 12a, the data is output from the SO terminal, or the data input from the SI terminal is loaded into the buffer RAM 12a and directly accessed. , Are read out to the RAM 13 (DMA method).

The data transferred from the mechanical control unit 1 to the mode control unit 11 is, for example, data indicating the state of the device, and the data transferred from the mode control unit 11 to the mechanical control unit 1 is, for example, data indicating the current mode.

Next, the time chart shown in FIG. 2 and FIG.
5 is a detailed block diagram of the serial interface 2 shown in FIG. 4, a detailed diagram of the shift registers 2b and 12b shown in FIG. 4, and the buffer RAM 2a shown in FIGS.
The operation will be described with reference to FIG.

The serial interface 12 of the mode controller 11 has one field period (1 in the case of the NTSC system).
6.67ms (millisecond), 20ms in case of PAL system)
A predetermined timing signal CS is generated on the basis of the synchronization signal having the period of, and is supplied to the CS terminal of the serial interface 2 constituting the mechanical controller 1 via the CS1 terminal. Further, the serial interface 12 of the mode controller 11 generates a predetermined SCK signal, and the serial interface 2 of the mechanical controller 1 is supplied via the SCK terminal.
Supply to.

The control program for controlling the serial interface 2 sets an automatic transfer start flag and a transfer end flag, and first turns on the automatic transfer start flag.

Next, the data D _{1 to} D ₃₂ to be transferred to the mode controller 11 stored in the RAM 3 are serial data.
It is supplied to predetermined addresses N to (N + 31) of the buffer RAM 2a of the interface 2 via the bus 4. On the other hand, similarly in the mode controller 11, RA
Data d _{1 to} d ₃₂ stored in M13 to be transferred to the mechanical controller 1 are supplied to predetermined addresses N to (N + 31) of the buffer RAM 12a via the bus 14, respectively. Then, the transfer end flag is turned off.

In this state, when the CS signal changes to the L level lower than the predetermined reference potential (time T1 in FIG. 2), the serial interfaces 2 and 12 start the predetermined operation. In the mechanical controller 1, as shown in FIG. 3, the data D ₁ (8
Bits) are supplied to the shift register 2b via the bus 2c. On the other hand, in the mode controller 11, the data d ₁ (8
Bits) are supplied to the shift register 12b via the bus 12c.

That is, in the serial interface 2, as shown in FIG. 4, the data D ₁ (composed of bit data D _{10 to} D ₁₇ ) stored in the shift register 2b is supplied from the mode controller 11. Serially through the SO pin bit by bit in synchronization with the SCK signal
Output to the interface 12 and serial
From the shift register 12b of the interface 12, the SO
The data d ₁ output via the terminal and input via the SI terminal of the serial interface 2 is stored in the shift register 2b.

That is, the shift register 2b of the serial interface 2 is used to form the data D ₁ from D ₁₀ to D _10.
17 is transferred to the shift register 12b of the serial interface 12, and the bit data d _{10 to} d ₁₇ forming the data d ₁ stored in the shift register 12b of the serial interface 12 are the shift registers of the serial interface 2. 2b.

In FIG. 4, the data D ₁ stored in the shift register 2b of the serial interface 2 is stored.
Of the data d ₁ stored in the shift register 12b of the serial interface 12 is supplied to the shift register 12b of the serial interface 12.
The state of being supplied to the shift register 12b of the interface 12 is shown.

Next, the data d ₁ supplied to the shift register 2b is supplied to the buffer RAM 2a via the bus 2c and written in the address N of the buffer RAM 2a. As a result, as shown in FIG.
Data d ₁ is stored in the address N of a, and data D _{2 to} D ₃₂ are stored in the addresses (N + 1) to (N + 31).
Will be stored.

For each of the data D _{2 to} D ₃₂ and the data d _{2 to} d ₃₂ , the shift registers 2b, 1 are transferred from the buffer RAM 2a in the same manner as described above.
It can be transferred to the buffer RAM 12a via 2b. FIG. 6 shows the buffer RAM 12 in this way.
The data d _{1 to} d ₃₂ stored in a are stored in the buffer R
The state of being transferred to the AM 2a is shown.

When the data transfer ends, the serial interface 2 generates a predetermined transfer end interrupt,
The automatic transfer start flag is automatically turned off. A predetermined system program is activated by the transfer end interrupt, and the transfer end flag is turned on.

When a predetermined job of Mechacon 1 is started
(Time T3 in FIG. 2), the transfer end flag is turned on.
When this is set, this job is mode con 11
The buffer RAM 2a via the shift register 2b.
Data transferred to₁Through d_{3 2}To RAM3
The data acquisition process is executed (time T4 in FIG. 2).
When the data acquisition process is completed, this job will
The transfer start flag is turned on (time T5 in FIG. 2).
As a result, when the CS signal changes to the L level next time,
Then, the next transfer process can be started.

Next, this job executes a data construction process for writing in the buffer RAM 2a the predetermined data stored in the RAM 3 and to be transferred to the mode controller 11 next. When the data construction process ends, the transfer end flag is turned off.

In this way, data transfer from the mechanical controller 1 to the mode controller 11 is sequentially executed.

In the above embodiment, 32 bytes of data are mutually transferred in one communication between the microcomputers, but data of any size of 32 bytes or less may be transferred. You can also do it.

Further, in the above embodiment, 32 bytes of data are mutually transferred in one communication between the microcomputers. However, the storage capacity of the buffer RAM is increased to increase the number of bytes of 32 bytes or more. It is also possible to transfer.

Further, in the above embodiment, the shift register having a size of 8 bits is used, but it is also possible to use the shift register having another size.

[0040]

According to the communication method or apparatus of the first or fourth aspect of the present invention, the predetermined data is transferred in N-byte units between the microcomputers according to the predetermined timing signal. In the case of the predetermined data, the data can be transferred by one communication between the microcomputers. Therefore, it is possible to simplify the processing in communication between the microcomputers and improve the efficiency.

According to the communication method or apparatus of the second or fifth aspect, since the data transfer between the microcomputers is performed by the DMA method, the load on the microcomputers can be reduced. Therefore, the processing performance of the microcomputer can be improved.

According to the communication method or apparatus of the third or sixth aspect, since data transfer between the microcomputers is performed in units of 32 bytes, efficient data transfer can be performed. Therefore, the processing performance of the device can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a serial interface unit to which a communication device of the present invention is applied.

FIG. 2 is a time chart showing the operation of the serial interface unit shown in FIG.

FIG. 3 is a diagram for explaining the operation of the serial interface unit 2 shown in FIG.

FIG. 4 is a shift register 2b of the mechanical controller 1 shown in FIG.
6A and 6B are diagrams for explaining the operation of the shift register 12b of the mode controller 11.

5 is a diagram showing data stored in a buffer RAM 2a shown in FIG. 3 at a predetermined timing.

FIG. 6 shows a buffer RAM 2 at the end of data transfer.
It is a figure which shows the data memorize | stored in a.

[Explanation of symbols]

 1 Mechacon 2 Serial Interface Unit 2a Buffer RAM 2b Shift Register 2c Bus 3 RAM 4 Bus 11 Modecon 12 Serial Interface Unit 12a Buffer RAM 12b Shift Register 12c Bus 13 RAM 14 Bus

Claims (6)

[Claims] 1. A communication method for performing data communication between a plurality of microcomputers that store predetermined data and execute a predetermined job, wherein a predetermined timing signal for changing a potential at a predetermined cycle is generated, When the potential of the signal changes and the data communication is not performed between the microcomputers, the predetermined data stored in the first microcomputer of the microcomputers is transferred to the second microcomputer of the microcomputers. The data is transferred serially in units of N bytes and the second
The predetermined data stored in the microcomputer of
Serially transferred to the microcomputer of N byte unit, and after the transfer is completed, in the first microcomputer,
By the first job of the first microcomputer, the predetermined data of the second microcomputer transferred from the second microcomputer is read, and then the predetermined data to be transferred to the second microcomputer is read. After being set to the first microcomputer and after the transfer is completed, in the second microcomputer,
The predetermined data of the first microcomputer transferred from the first microcomputer is read at a predetermined timing, and the predetermined data to be transferred to the first microcomputer next is transferred to the second microcomputer. A communication method characterized by being set. 2. The communication method according to claim 1, wherein the transfer of the data between the first microcomputer and the second microcomputer is performed by a DMA method. 3. The communication method according to claim 1, wherein the transfer is performed in units of 32 bytes. 4. A timing signal generator for generating a predetermined timing signal for changing a potential in a predetermined cycle in a communication device for storing data and performing data communication between a plurality of microcomputers for executing a predetermined job. And a predetermined data stored in the first microcomputer among the microcomputers when the data communication is not performed when the potential of the timing signal generated by the timing signal generator changes. A transfer means for serially transferring to the second microcomputer of the microcomputer in units of N bytes, and for transferring predetermined data stored in the second microcomputer to the first microcomputer in units of N bytes. And after the transfer by the transfer means is completed, the second job is executed by the first job of the first microcomputer. The predetermined data transferred from the second microcomputer is read out, predetermined data to be transferred to the second microcomputer next is set in the first microcomputer, and the transfer ends. After that, in the second microcomputer,
The predetermined data of the first microcomputer transferred from the first microcomputer is read at a predetermined timing, and the predetermined data to be transferred to the first microcomputer next is transferred to the second microcomputer. A communication device comprising: a data setting unit to be set. 5. The transfer means DM transfers the data between the first microcomputer and the second microcomputer.
The communication device according to claim 4, wherein the communication is performed by the A system. 6. The transfer means stores the predetermined data in 3
The communication device according to claim 4, wherein data is transferred in units of 2 bytes.