JP2001175585A - Device and method for transferring data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronously transfer the same data to plural storage regions. SOLUTION: When data are stored in an FIFO 12, a camera interface 11 simultaneously outputs the data stored in the FIFO 12 to both DMAC 13 and 15 on the basis of a data request from the DMAC 13, the DMAC 13 performs the DNA transfer of these data through a main memory interface 16 to a main memory 4 and the DMAC 15 performs the DMA transfer of these data through a display buffer interface 19 to a display buffer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device and a data transfer method, and more particularly to a data transfer device and a data transfer method suitable for application to DMA (Direct Memory Access) transfer control of image data in an image input device.

[0002]

2. Description of the Related Art In conventional DMA transfer control of image data in an image input device, the same image data output from an image input device such as a CCD camera or a CMOS image sensor is stored in both a main memory and a display buffer. was there. In this case, first, image data periodically output from the image input device is transferred to the main memory by DMA, and writing to the main memory is performed. Then, after the image data is written to the main memory, the image data is read from the main memory, transferred from the main memory to the display buffer, and written into the display buffer.

[0003]

However, in the conventional DMA transfer control of image data in the image input device, when the same image data is stored in both the main memory and the display buffer, the image data is periodically output from the image input device. It is necessary to transfer the image data to be written to the main memory by DMA transfer, read the image data from the main memory, and write it to the display buffer. Therefore, there is a problem that it takes time to store the same image data in both the main memory and the display buffer.

Further, in the main memory, both reading and writing of the same image data are performed, so that the number of accesses within a certain time increases, and there is a problem that power consumption increases.

Further, if the writing and reading to the main memory are not synchronized, the image data being read may be rewritten from the middle, and in order to avoid this, the writing area and the reading area must be rewritten. 2
It was necessary to provide two image areas in the main memory. For this reason, there is a problem that the use efficiency of the storage area of the main memory is deteriorated.

An object of the present invention is to provide a data transfer device and a data transfer method capable of transferring the same data to a plurality of storage areas in synchronization.

[0007]

According to the present invention, in order to solve the above-mentioned problems, the same data is transferred to a plurality of storage areas in synchronization with the same read timing.

Thus, the same data can be stored in a plurality of storage areas at the same time, and the time for storing data in the plurality of storage areas can be reduced.

Further, according to the present invention, the first data transfer means for transferring data, and the first data transfer means reads the data synchronously with the data read timing by the first data transfer means. And second data transfer means for transferring the data to be transferred.

[0010] This makes it possible to control the data transfer timing of the second data transfer means by the data transfer timing of the first data transfer means, and to perform a plurality of data transfer processes in synchronization. Becomes

Further, according to the present invention, the first data transfer means for transferring data, the second data transfer means for transferring the data, and the first data transfer means or the second data transfer means. A read control unit that controls reading of data by the first data transfer unit and the second data transfer unit based on one of the read timings of the data transfer unit may be provided.

Thus, a plurality of data transfer processes can be performed at one data transfer timing, and the data transfer timing can be switched according to the data transfer status, so that the data transfer can be efficiently performed. It is possible to do.

Further, according to the present invention, the reading control means can read data in synchronization with a later reading timing.

Thus, it is possible to prevent the data from being transferred before the data with the later read timing is read, thereby preventing the data from being read out with the later read timing. This makes it possible to prevent data loss when transferring the same data to a plurality of storage areas at the same time.

Further, according to the present invention, it is possible to provide a single operation control means for operating one of the first data transfer means and the second data transfer means independently.

This makes it possible to select any one of the plurality of storage areas to transfer data, and to transfer data when there is no need to transfer data to the plurality of storage areas. Efficiency can be improved.

Further, according to the present invention, the first data format conversion means for converting the format of the data input to the first data transfer means and the data output from the second data transfer means are provided. Second data format conversion means for performing format conversion can be provided.

Thus, even when the data format of the transfer destination is different, it is possible to transfer those data simultaneously.

According to the present invention, the first storage means for storing the data transferred by the first data transfer and the second storage means for storing the data transferred by the second data transfer means. Second storage means, and third data transfer means for transferring data stored in the first storage means to the second storage means.

Thus, the data once stored can be directly transferred to another storage area.

Further, according to the present invention, it is possible to provide an occupancy control means for controlling the occupation of the transfer path of the data output from the first data transfer means.

Thus, even when the data transfer path is shared with another device, data transfer can be prevented from being delayed due to transfer path competition, and high-speed transfer can be achieved. .

Further, according to the present invention, it is possible to provide a clock output control means for controlling a clock output to the first and second data transfer means based on a data transfer situation.

Thus, the supply of the clock can be stopped while the data is not being transferred.
Power consumption can be reduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a data transfer device according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a CMO for periodically outputting captured image data.
The S sensor 2 is a data transfer device for transferring image data output from the CMOS sensor 1 to the main memory 4 and the display buffer 5, 3 is a microcomputer for controlling the system (hereinafter, referred to as a microcomputer), and 4 is data. , A display buffer for storing image data, 6 a liquid crystal display (LCD), 7 a DSP (digital signal processor) for performing digital image processing, 11 a CMOS sensor 1 A camera interface for taking in the output image data and converting the format of the image data into a format handled by the main memory 4 according to the mode setting;
(First in Firstout), 13 is a DMAC (Direct Memory Access Controller) for transferring image data output from the camera interface 11 to the main memory 4, and 14 is a DMAC 13 and a DMAC.
15 is a DMA synchronization control unit that performs synchronization control, 15 is a DMAC that transfers image data output from the camera interface 11 to the display buffer 5, and 16 is a main memory interface that generates control signals for the main memory 4 and the like.
Reference numeral 7 denotes a DMAC for transferring image data stored in the main memory 4 to the display buffer 5, and reference numeral 18 converts a format of image data output from the camera interface 11 to a display format of the liquid crystal display device 6 according to a mode setting. A display data converter 19 for generating a control signal for the display buffer 5 and an LCD interface 20 for controlling display of the liquid crystal display device 6. The main memory 4 and the display buffer 5 are, for example, a DRAM, an SRAM, an EEPROM,
Etc. can be used.

Here, the DMA synchronization control section 14 selects, for example, the later of the data read timing from the DMAC 13 and the data read timing from the DMAC 15 and adjusts the camera interface 11 in accordance with the later data read timing. Can be output to both the DMAC 13 and the DMAC 15. The conversion mode of the data format performed by the camera interface 11 and the display data converter 18 can be set by the microcomputer 3.

An image picked up by the CMOS sensor 1 is stored in a DSP built in a module of the CMOS sensor 1.
After the correction in step 7, the image data is output as image data in RGB format or YUV format at a constant interval of several to several tens of sheets / second. When reading the image data output from the CMOS sensor 1, the camera interface 11 sequentially stores the image data in the FIFO 12.

Here, the camera interface 11
The format of the image data output from the CMOS sensor 1 is converted into the format of the image data handled by the system according to the mode setting. For example, the format of the image data output from the CMOS sensor 1 is the YUV format, and the format of the image data handled by the system is RG.
In the case of the B format, the conversion mode of the camera interface 11 is set to “the conversion mode from the YUV format to the RGB format”.
Can be set to On the other hand, the format of the image data output from the CMOS sensor 1 is the RGB format, and the format of the image data handled by the system is also the RGB format.
In the case of the format, the conversion mode of the camera interface 11 can be set to “off”.

The image data converted into the data format handled by the system is transmitted as FIFO data having a bus width of FIFO.
12 are sequentially stored.

Here, for example, when the data transfer speed from the DMAC 13 to the main memory 4 is lower than the data transfer speed from the DMAC 15 to the display buffer 5, the DMA synchronization control unit 14 , DMAC 13 and DMAC 15 to perform data transfer.

In this case, the camera interface 11
When data is stored in the FIFO 12, DMAC 1
3 and DMAC 13 and D
The data stored in the FIFO 12 is output to both of the MACs 15 at the same time.

When data is output from the camera interface 11, the DMAC 13 DMA-transfers the data to the main memory 4 via the main memory interface 16.

On the other hand, when data is output from the camera interface 11, the DMAC 15 outputs the data to the display data converter 18. Then, the data format of the data output from the camera interface 11 is
The data is converted into a data format displayed on the liquid crystal display device 6 and DMA-transferred to the display buffer 5 via the display buffer interface 19.

Here, the display data conversion unit 18 determines that the format of the image data output from the camera interface 11 is the YUV format and the format of the image data displayed on the liquid crystal display device 6 is the RGB format. The format of the image data output from the camera interface 11 can be converted to the format of the image data displayed on the liquid crystal display device 6. On the other hand, the format of the image data output from the camera interface 11 is the RGB format, and the format of the image data displayed on the liquid crystal display device 6 is also the RGB format.
In the case of the B format, the image data output from the camera interface 11 can be output as it is without converting the format of the image data output from the camera interface 11.

When the image data is stored in the main memory 4,
By processing the image data by the microcomputer 3, the image data can be edited or compressed.

On the other hand, when the image data is stored in the display buffer 5, the image data is read out via the display buffer interface 19 and displayed on the liquid crystal display device 6 via the LCD interface 20.

FIG. 2 is a block diagram showing a configuration example in which both the DMACs 13 and 15 perform data transfer based on a data request from the DMAC 13. In FIG. 2, a CMOS sensor 1 includes a camera interface 1
1 and outputs image data to the camera interface 11 when the camera interface 11 is ready to receive data. When receiving the image data from the CMOS sensor 1, the camera interface 11 stores the image data in the FIFO 12. And the camera interface 11 is a FIFO
If any data is stored in the memory 12, the REQ signal is output to the DMAC 13 and the DMAC 15. DM
When the data can be received from the camera interface 11, the AC 13 outputs an ACK signal to the camera interface 11 and also to the DMAC 15. The camera interface 11 is a DMAC1
3 receives the ACK signal from the DMAC 13 and DMAC 1 at that timing.
5 and output to both. DMAC13 and DMAC15
Receives image data output from the camera interface 11 based on the timing of the ACK signal,
The received data is DMA-transferred.

FIG. 3 is a timing chart showing an example of the data transfer method of the data transfer device 2 of FIG. FIG.
In (a), when even one data is stored in the FIFO 12, a REQ signal is output from the camera interface 11. Then, when the DMAC 13 is ready to receive data while the REQ signal is being output from the camera interface 11, the DMAC 13 outputs an ACK signal A0 to the camera interface 11 and the DMAC 15, as shown in FIG. . When the camera interface 11 receives the ACK signal A0,
The image data D1 for one cycle is transferred to the DMACs 13 and D
Output to MAC15. When one cycle of image data D1 is output from the camera interface 11, DM
The AC 13 and the DMAC 15 take in the image data D1. When the preparation for receiving the next data is completed, the DMAC 13 outputs an ACK signal A1 to the camera interface 11 and the DMAC 15. Upon receiving the ACK signal A1, the camera interface 11 outputs image data D2 for the next one cycle to the DMAC 13 and the DMAC 15. Camera interface 11
When the image data D2 for the next one cycle is output from the DMAC 13, the DMAC 13 and the DMAC 15 take in the image data D2.

As described above, the DMAC 13 sets the ACK signals A0, A1,.
.. Are sequentially output to the camera interface 11. Then, the camera interface 11 outputs the ACK signal A0,
.. Are received from the DMAC 13, the image data D is synchronized with the timing of the ACK signals A 0, A 1,.
0, D1,... Are output to both the DMAC 13 and the DMAC 15.

Here, the bus for accessing the main memory 4 is shared by the data transfer device 2 and the microcomputer 3. For this reason, data transfer from the DMAC 13 to the main memory 4 may conflict with access from the microcomputer 3 to the main memory 4, and data transfer from the DMAC 13 to the main memory 4 may involve data transfer from the DMAC 15 to the display buffer 5. May be delayed. Therefore, in accordance with the data transfer from the DMAC 15 to the display buffer 5, the FIFO 12
When the image data is read from the memory, the next image data is sent before the writing of the image data to the main memory 4 is completed, so that a part of the image data stored in the main memory 4 is lost.

Therefore, in the embodiment shown in FIG.
3 is supplied to the camera interface 11 and the DMAC 15, and the image data is read from the FIFO 12 in accordance with the ACK signal output from the DMAC 13. Thereby, DMAC
13 in accordance with the data transfer from the memory 13 to the main memory 4.
It becomes possible to read out the image data from the memory 12 and to prevent a part of the image data stored in the main memory 4 from being lost.

In the embodiment of FIG. 2, the DMAC 13
In accordance with the data transfer from the
Has been described for reading image data from
The image data may be read from the FIFO 12 in accordance with the data transfer from the MAC 15 to the display buffer 5. For example, since the data conversion process in the display data conversion unit 18 takes a long time, if the data transfer from the DMAC 15 to the display buffer 5 is later than the data transfer from the DMAC 13 to the main memory 4, the DMAC 1
3 in accordance with the data transfer from
When the image data is read from 2, the image data stored in the display buffer 5 is partially missing. Therefore, in such a case, the DMA synchronization control unit 14 switches the output source of the ACK signal, and
When the CK signal is transmitted to the camera interface 11 and the DMA
C13. Thereby, DMAC
15 in accordance with the data transfer from
Image data can be read from the FO12,
It is possible to prevent a part of the image data stored in the display buffer 5 from being lost.

Here, the microcomputer 3 comprises the DMACs 13, 1
5 and 17 are supplied with an enable signal and DMAC1 is supplied.
Which of 3, 15, and 17 to operate can be set. For example, when data output from the camera interface 11 is stored in both the main memory 4 and the display buffer 5, an enable signal is supplied to the DMACs 13 and 15 to operate the DMACs 13 and 15, and an unenable signal is supplied to the DMAC 17. And D
The operation of the MAC 17 is stopped.

When the data output from the camera interface 11 is stored only in the main memory 4, an enable signal is supplied to the DMAC 13 to
At the same time as operating the DMAC 13, an unenable signal is supplied to the DMACs 15 and 17 to stop the operations of the DMACs 15 and 17.

When data output from the camera interface 11 is stored only in the display buffer 5, an enable signal is supplied to the
In addition to operating C15, an unenable signal is supplied to the DMACs 13 and 17 to stop the operations of the DMACs 13 and 17.

When transferring the image data stored in the main memory 4 to the display buffer 5, the DMAC 1
7, the DMAC 17 is operated by supplying an enable signal, and an unenable signal is supplied to the DMACs 13 and 15 to stop the operation of the DMACs 13 and 15.

Here, when the DMAC 17 is operated,
The image data stored in the main memory 4 is DMA-transferred to the display buffer 5 via the display data converter 18. The festival / display data conversion unit 18 can convert the data format of the image data stored in the main memory 4 into the data format displayed on the liquid crystal display device 6. For example, when the format of the image data stored in the main memory 4 is the YUV format and the format of the image data displayed on the liquid crystal display device 6 is the RGB format,
The format of the image data stored in the main memory 4 can be converted to the format of the image data displayed on the liquid crystal display device 6. On the other hand, when the format of the image data stored in the main memory 4 is the RGB format and the format of the image data displayed on the liquid crystal display device 6 is also the RGB format, the format of the image data stored in the main memory 4 is Without format conversion,
The image data stored in the main memory 4 can be output as it is.

Next, a method for speeding up data transfer when a load is applied to the bus accessing the main memory 4 will be described.

FIG. 4 is a block diagram for explaining the operation of the data transfer device 2 of FIG. 1 when the bus is occupied. In FIG. 4, not only the data transfer device 2 but also a microcomputer 3 is connected to a bus for accessing the main memory 4.
Is accessing the main memory 4, the CMO
Even when the image data is output from the S sensor 1, the data transfer device 2 cannot access the main memory 4. Therefore, when image data is output from the CMOS sensor 1, the image data is stored in the FIFO 12,
When the FIFO 12 is full, the destination of the image data is lost, and the image data overflows.

Therefore, when performing the data transfer 32, the data transfer device 2 uses the R for occupying the bus of the main memory 4.
An EQ signal is output to the microcomputer 3. When the data transfer device 2 receives the GNT signal permitting the occupation of the bus from the microcomputer 3, the data transfer device 2 occupies the bus of the main memory 4 and performs the data transfer 32.

As a result, the data transfer device 2 can eliminate the waiting time due to the contention of the bus with the microcomputer 3 and can improve the data transfer speed to the main memory 4 and the display buffer 5. Also, CMOS
Even when the data transfer speed of the sensor 1 is high, it is possible to prevent the data from being missed and to prevent the image data stored in the main memory 4 and the display buffer 5 from being lost.

Next, a method of supplying a clock at the time of DMA transfer will be described.

When supplying a clock during DMA transfer,
The start and end of the DMA for one screen are detected, the clock is supplied to the DMACs 13, 15, and 17 only during the execution of the DMA, and the clock is stopped otherwise.

Thus, in a case where image data is transmitted intermittently, during a period when image data is not transmitted,
The clock can be stopped, and power consumption during data transfer can be reduced.

FIG. 5 is a time chart showing a clock supply method of the data transfer device of FIG. In FIG.
When input of data from the CMOS sensor 1 is started (t
1) The clock supply is started, and when the DMA transfer is completed (t2), the clock supply is stopped. Furthermore, CM
When the input of data from the OS sensor 1 is started again (t
3) The supply of the clock is started, and when the DMA transfer is completed (t4), the supply of the clock is stopped. As a result, t
During the period from 2 to t3, the supply of the clock remains stopped, and the power consumption can be reduced. Note that DM
The start of A can use the start trigger signal output from the CMOS sensor 1, and the end of DMA is D
END signals output from the MACs 13, 15, 17 can be used.

As described above, according to the above-described embodiment, it is possible to transfer the image data output from the CMOS sensor 1 to both the main memory 4 and the display buffer 5 at one time. Display buffer 5
This makes it possible to save time when the same image data is stored.

Although the CMOS sensor 1 has been described as an example of the image input device in the above-described embodiment, the image input device may be one using a CCD (charge coupled device) or an image pickup tube. Further, the liquid crystal display device 6 has been described as an example of the display device, but the display device may be a CRT, a plasma display device, or the like. Although the main memory 4 and the display buffer 5 have been described as examples of the storage area for storing image data, the storage area may be a print buffer, a backup memory, a cache memory, or the like.

[0059]

As described above, according to the present invention,
The same data can be simultaneously stored in a plurality of storage areas, and the time for storing data in the plurality of storage areas can be reduced.

Further, since the number of accesses to the storage area when storing the same data in a plurality of storage areas can be reduced, the storage area can be used effectively and the power consumption can be reduced. Reduction can also be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration example of a DMAC of the data transfer device of FIG. 1;

FIG. 3 is a timing chart showing an example of the operation of the data transfer device of FIG. 1;

FIG. 4 is a block diagram for explaining an operation of the data transfer device of FIG. 1 when a bus is occupied;

FIG. 5 is a time chart illustrating a clock supply method of the data transfer device of FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 CMOS sensor 2 Data transfer device 3 Microcomputer 4 Main memory 5 Display buffer 6 Liquid crystal display device 7 DSP 11 Camera interface 12 FIFO 13, 15, 17 DMAC 14 DMA synchronization unit 16 Main memory interface 18 Display data conversion unit 19 Display buffer interface 20 LCD interface

Claims (10)

[Claims] 1. A data transfer device for transferring the same data to a plurality of storage areas in synchronization with the same read timing. A first data transfer unit for transferring data; and a transfer of data read by the first data transfer unit in synchronization with a data read timing by the first data transfer unit. A data transfer device comprising: a second data transfer unit. 3. A first data transfer unit for transferring data, a second data transfer unit for transferring the data, and one of the first data transfer unit and the second data transfer unit Based on one reading timing,
A data transfer device, comprising: a read control unit that controls reading of data by the first data transfer unit and the second data transfer unit. 4. The data transfer device according to claim 3, wherein said read control means causes the data to be read in synchronization with a later read timing. 5. An apparatus according to claim 2, further comprising: an independent operation control unit configured to independently operate one of said first data transfer unit and said second data transfer unit.
5. The data transfer device according to any one of 4. 6. A first data format converter for converting the format of data input to the first data transfer device, and a second data converter for converting the format of data output from the second data transfer device. The data transfer device according to any one of claims 2 to 5, further comprising a data format conversion unit. 7. A first storage means for storing data transferred by the first data transfer, a second storage means for storing data transferred by the second data transfer means, The data transfer device according to claim 2, further comprising a third data transfer unit that transfers data stored in the first storage unit to the second storage unit. 8. The data transfer device according to claim 2, further comprising an occupation control unit that controls occupation of a transfer path of data output from the first data transfer unit. . 9. The method according to claim 1, further comprising the step of:
9. The data transfer device according to claim 2, further comprising a clock output control unit that controls output of a clock to the second data transfer unit. 10. A data transfer method, wherein data transfer control of a second DMAC is performed based on a data request from a first DMAC.