JPH05135161A - Image memory device - Google Patents

Abstract

PURPOSE:To efficiently utilize an input/output image data bus. CONSTITUTION:After A/D converting circuits 14 and 16 convert input signals into digital signals, a packet is composed of (q) data in an FIFO memory 24 and outputted to the image data bus 12. Then D/A converting circuits 18 and 20 decompose the packet from the image data bus 12 into picture element data, which are converted into analog data and outputted. A bus control circuit 26 obtains the head address of the packet by referring to an address converting circuit 28 and sends it to a memory control circuit 11. The memory control circuit 11 writes the data on the image data bus 12 in a memory 10 in order from the head address or reads the data out of the memory 10 to the image data bus 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device.

[0002]

2. Description of the Related Art Conventionally, access to an image memory device is basically on a pixel basis. Further, as a method for realizing multiport, that is, a plurality of input / output, a configuration in which an image memory is accessed via an input / output bus has been proposed, but in this configuration, access is basically performed in pixel units. ..

[0003]

As described above, even if multi-ports are used, the transfer speed of the input / output bus is limited, so that while one input / output (I / O) circuit is accessing. In addition, it is difficult to interrupt access to other input / output circuits, and in particular, in the case of a large-capacity image memory device, it is often kept waiting for a long time.

In the case of an image memory, it may be possible to simplify data management in units of image frames (or fields). However, if an access method in units of pixel data is applied to a multiport memory, it will be performed in units of frames. Data management becomes difficult and complicated address management becomes necessary.

It is an object of the present invention to provide an image memory device which makes effective use of an input / output bus and simplifies address management.

[0006]

An image memory device according to the present invention comprises a memory means having a storage capacity of a predetermined number of frames, an input / output bus for inputting / outputting to / from the memory means, and an input / output bus. Via one or more input / output means for accessing the memory means in units of a predetermined number of data packets.

[0007]

By the above means, the address management of the memory means is simplified. In addition, the occupation time of the input / output bus by one input / output means is shortened, and the interrupt can be easily used by another input / output means. These substantially speed up access.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 1A is an overall configuration block diagram, and FIG. 1B is an internal circuit example of an A / D conversion circuit which is an input port.

In FIG. 1 (a), 10 is a memory for storing image data, which has a memory capacity capable of storing a plurality of frames. A memory control circuit 11 controls the memory 10. Reference numeral 12 is an image data bus for accessing the memory 10 via the memory control circuit 11,
4 and 16 are A for digitizing analog video signals
The D / A conversion circuits 18 and 20 are D / A conversion circuits for converting the image data read from the memory 10 onto the image data bus 12 into analog signals and outputting the analogized image data.

In this embodiment, the A / D conversion circuit 14 is used for camera input, the A / D conversion circuit 16 is used for line input, and D
A / A conversion circuit 18 for VTR output, D / A conversion circuit 20
Is for monitor output, and is input / output to / from the image data bus 12 in packet units.

As shown in FIG. 1B, the A / D conversion circuit 14 includes an A / D converter 22 and eight A / D converters 22.
It consists of M FIFO (First In First Out) memories 24 for packetizing the bit outputs. A / D conversion circuit 16
Also has the same configuration. The D / A conversion circuits 18 and 20 are
Contrary to the D / D conversion circuits 14 and 16, the image data bus 1
M FIFO memories to which packets from 2 are input,
And a D / A converter for converting the output of the FIFO memory into an analog signal.

Reference numeral 26 denotes A / D conversion circuits 14, 16 and D via the image data bus 12 and the memory control circuit 11.
The bus control circuit controls input / output between the A / A conversion circuits 18 and 20 and the memory 10. Reference numeral 28 denotes an address conversion circuit that outputs the start address of the memory 10, the required number of packets, and the number of data of one packet in response to the designation of the frame number and the number of frames from the bus control circuit 26, and stores the initial value. It consists of a ROM and a RAM for updating during operation.

Reference numeral 30 is a CPU for controlling the whole, 32 is a monitor for displaying an operating state, 34 is a monitor control circuit for controlling the monitor 32, 36 is a CPU bus for interconnecting the CPU 30, the monitor control circuit 34 and the bus control circuit 26. Is.

First, the operation of this embodiment will be described by taking the case where the camera input is stored in the memory 10 as an example. FIG. 2 shows a flowchart of the operation. The CPU 30 outputs the recording start of the camera input and the recording amount (frame number and frame number) to the bus control circuit 26 (S1). The bus control circuit 26 refers to the address conversion circuit 28 and
From the frame number and the number of frames from the PU 30, the head address of the memory 10, the required packet number n and the data number q of one packet are obtained. Then, the obtained data number q of one packet is transferred to the A / D conversion circuit 14 via the image data bus 12, and the start address 10 is set to the memory control circuit 11
Transfer to.

In the A / D conversion circuit 14, the number q of data of one packet is set in the control unit of the FIFO memory 24 (S3), and the A / D converter 22 receives the analog input signal from the camera.
The video signal is digitized and stored in the FIFO memory 24. When q pieces of data for one packet are stored in the FIFO memory 24, the transfer request is sent to the image data bus 12
Print above.

On the other hand, the bus control circuit 26 clears the variable x for managing the number of packets (S5), transfers the start address of each packet to be transferred to the memory control circuit 11 (S7), and A / D. It waits for a transfer request from the conversion circuit 14 (S8). The image data bus 12 is released for the A / D conversion circuit 14 in response to the transfer request from the A / D conversion circuit 14, and the memory control circuit 11 transfers the data from the A / D conversion circuit 14 to the memory 10. I will write it.

The memory 10 is a D-RAM (dynamic
Random access memory), the data on the image data bus 12 can be transferred to the memory 1 at high speed in its high-speed page mode or its corresponding write mode.
Write to 0. After writing one packet of data,
An end message is sent to the bus control circuit 26 (S9). The bus control circuit 26 increments the variable x according to the end message (S10).

Until the required number n of packets are transferred, that is, until n = x (S6), S7 to 9 are repeated,
When n = x, an end message is sent to the CPU 30 and the CPU 30 ends the camera input storage control.

FIG. 3 shows the data structure of one packet.
q is the number of data of one packet designated by the bus control circuit 26 and can be changed. Further, p is the width (bytes) of the image data bus. The data number m of one packet is m = q × p.

FIG. 4 shows a timing chart for the above operation of writing the camera input to the memory 10. A in the figure
Indicates a period for accumulating one packet of data in the A / D conversion circuit 14, and B indicates a period for writing one packet of data in the memory 10. The image data bus 12 is not used for the period C except the period B in the period A, and the other A / D conversion circuits 16 or D are included in the period C.
It can be used by the / A conversion circuits 18 and 20.

FIG. 5 shows that the VTR output (D / A
Conversion circuit 18), line input (A / D conversion circuit 16),
2 shows a timing chart when the monitor output (D / A conversion circuit 20) is sequentially interrupted. As a result, the four tasks of writing the camera input to the memory 10, outputting the content of the memory 10 to the VTR, writing the line input to the memory 10, and outputting the content of the memory 10 to the monitor can be performed in a short period of time. Become.

[0023]

As can be easily understood from the above description, according to the present invention, the input / output bus can be efficiently used,
Moreover, address management becomes easier. Since the number of data in one packet can be changed, the memory means can be effectively used.
Further, there is an advantage that the access speed becomes substantially high.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of this embodiment.

FIG. 3 is a configuration diagram of a packet according to the present exemplary embodiment.

FIG. 4 is a timing chart of the present embodiment with respect to camera input.
It is a chart.

FIG. 5 is a timing chart of camera input, VTR output, line input, and monitor output according to the present embodiment.

[Explanation of symbols]

10: memory 11: memory control circuit 12: image data bus 14, 16: A / D conversion circuit 18, 20:
D / A conversion circuit 22: A / D converter 24: FIFO
(First-in first-out) Memory 26: Bus control circuit 28:
Address conversion circuit 30: CPU 32: Monitor 34: Monitor control circuit
36: CPU bus

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Ichiro Kuwana 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (1)

[Claims] 1. A memory means having a storage capacity of a predetermined number of frames, an input / output bus for inputting / outputting to / from the memory means, and the memory means in units of a predetermined number of data packets via the input / output bus. An image memory device comprising one or more input / output means for accessing the memory.