JP2743051B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which stores image data obtained by a visual sensor in a memory and outputs the stored image data to a monitor. The present invention relates to an image processing apparatus in which a configuration of a circuit for controlling an input is simplified.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a configuration of a conventional image processing apparatus. In the figure, reference numeral 1 denotes a visual sensor for acquiring image data. The visual sensor 1 outputs the acquired analog image data to the A / D converter 2. The A / D converter 2 converts the input data into digital data and outputs the digital data to the image input circuit 3. The image input circuit 3 stores the digitized image data 100 in the memory 4. Also,
The image output circuit 6 outputs the image data 10 stored in the memory 4.
0 is read as necessary and output to the D / A converter 7. The D / A converter 7 converts the input data into the original analog data and outputs it to the monitor TV 8. Then, an image corresponding to the input image data is displayed on the monitor TV8. The image data 100 stored in the memory 4 is subjected to image processing by an image processing circuit 9 controlled by a CPU 10 as necessary. Note that the image input circuit 3 and the image output circuit 6 generate image data according to an image input signal and an image output signal from the signal control circuit 5 controlled by the CPU 10.
100 write operations and read operations are individually controlled.

Normally, the output from the visual sensor 1 is a signal of a current television broadcast (hereinafter referred to as an NTSC signal). In order to store the NTSC signal in the memory 4, one line in one screen is required. An image input circuit 3 for inputting an NTSC signal to the memory 4 while managing the number of data, the number of lines, and the like is required. When handling such an interlaced NTSC signal,
The memory 4 is provided so that image processing in the memory 4 can be easily performed.
The image data 100 of one screen must be aligned within the image data, so that it is necessary for the image input circuit 3 to also determine the odd field and the even field. For the above reasons, the image input circuit 3 has a complicated internal circuit configuration.

FIG. 2 is a block diagram of the image input circuit 3 shown in FIG.
FIG. 2 is a block diagram showing the internal configuration of the image output circuit 6 described above. In FIG. 2, the same reference numerals as in FIG. 1 denote the same parts. The image input circuit 3 includes a screen management circuit 31 and
A line counter 32, a one-screen counter 33, and a field discriminating / combining circuit 34 are provided. The image output circuit 6
A screen control LSI 61, a memory management circuit 62,
And a serial conversion circuit 63.

Since a large capacity and high speed are required for the memory 4 used for image processing, a DRAM is generally used, and among DRAMs, a dual port memory which is convenient for image processing is used. Often.
FIG. 3 shows a memory 4 in FIG.
14 is a block diagram showing a configuration in the case of replacing with 14. FIG. In FIG. 3, reference numerals 13, 15, and 16 denote an image input circuit, a signal control circuit, and an image output circuit corresponding to the dual-port memory 14, and the same reference numerals as in FIG. 1 denote the same parts.

In FIG. 3, after inputting image data 100 to a SAM section 14a of a dual port memory 14, an image input circuit 13 stores the image data 100 in a RAM section 14b of the dual port memory 14. Become. Therefore, comparing the image input circuit 13 in FIG. 3 with the image input circuit 3 in FIG. 1, the control operation of the SAM unit 14a of the dual port memory 14 is required to be added to the image input circuit 13; The internal configuration of the input circuit 13 is further complicated.

Since the output signal to the monitor TV 8 is the NTSC signal as described above, the signal flow of the image output circuits 6 and 16 in FIGS. With such an internal circuit configuration, it has a complicated internal configuration like the image input circuit. However, for example, as shown in FIG. 2, it is known that the image output circuit 6 can be realized by a simple circuit by providing the screen control LSI 61. The same applies to the case of FIG. In addition, the internal configuration of the image output circuit 16 can be simplified.

[0008]

As described above, the image output circuit for controlling the output of the image data from the memory can be realized with a relatively simple circuit configuration, but controls the input of the image data to the memory. The image input circuit has a problem that a complicated circuit configuration is required, and simplification of the circuit configuration used for image data input is desired.

The present invention has been made in view of such circumstances, and has been made in view of reading and storing image data from storage means.
It is an object of the present invention to provide an image processing apparatus capable of simplifying the configuration of a circuit for writing image data to a unit .

[0010]

An image processing apparatus according to the present invention writes image data from a visual sensor into storage means.
In an image processing apparatus for reading image data from the storage means to a monitor, individual image data in the storage means
Image management signal, which is an address value string indicating the storage location of
And a read signal for reading image data.
Image data reading means; and image data for the storage means.
Determining means for determining whether to write or read data
When reading image data from the storage means.
Is an image management output from the image data reading means.
Signal and readout signal as they are via the determination means.
Output to the storage means, and the image data to the storage means.
In the case of writing, the image management
The readout signal writes the image data while the signal remains unchanged.
The signal is processed so as to be output to the storage means .

[0011]

According to the image processing apparatus of the present invention, image data is read out.
Writing and reading of image data in the storage means and the storage means.
Combined with the determination means to determine
Writing of the image data using a function provided in the out means
Because to perform the inclusive can, of image data read,
The entire circuit configuration can be simplified without complicating the configuration of the writing unit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments.

FIG. 4 is a block diagram showing the configuration of an embodiment of the image processing apparatus according to the present invention. In FIG. 4, portions denoted by the same reference numerals as those in FIGS. 1 and 2 shown in the conventional example indicate the same portions, and therefore description thereof will be omitted. In FIG. 4, 36
Reference numeral 0 denotes an input / output determination circuit for determining an input / output operation of image data. Reference numeral 50 denotes a signal control circuit that outputs a control signal to the input / output determination circuit 360 and the image output circuit 6 in response to a command from the CPU 10.

The input / output determination circuit 360 has a selector 361 having a plurality of input / output terminals and a delay circuit 362. A signal control circuit 50 is connected to one input terminal of the selector 361, and according to the type of control signal from the signal control circuit 50 (a screen output signal or a screen input signal described later),
The other four input terminals 1A, 1B,
The selection between 2A and 2B is controlled. The input terminal 1A is connected to the output terminal of the memory management circuit 62 that outputs the memory write signal 102. The input terminal 1B is connected via a delay circuit 362 to the output terminal of the memory management circuit 62 that outputs the memory read signal 103, and the input terminal 2A is directly connected to the output terminal of the memory management circuit 62. The input terminal 2B is connected to a constant power supply (5V) via a resistor 363. Also, the selector 361 outputs the write enable signal
In order to output 104 and read enable signal 105,
It is connected to the memory 4. Further, a signal (hereinafter, referred to as an image management signal) 106 for managing the number of data and the number of lines of one image line is input from the memory management circuit 62 to the memory 4.

Next, regarding the operation, the case where the image data 100 is output from the memory 4 and the case where the image data 100 is
The explanation will be given separately for the case where the input is made to the.

When outputting the image data 100, first, the signal control circuit 50 receiving a command from the CPU 10 sends a screen output signal to the selector 361 of the input / output determination circuit 360 and the screen control LSI 61 of the image output circuit 6. Is output. At this time, the selector 361 is selected on the A side. Screen control LSI
Upon receiving this screen output signal, the 61 outputs a request signal for requesting image data 100 necessary for screen output to the memory management circuit 62. The memory management circuit 62 outputs a memory read signal 103 to the selector 361 in response to the request signal. Here, since the selector 361 is selected to the A side by the screen output signal from the signal control circuit 50, the input memory read signal 103 is output as the read enable signal 105 to the memory 4 as it is. Then, the designated image data 100 is read from the memory 4 to the parallel / serial conversion circuit 63 of the image output circuit 6.

When receiving the screen output signal, the screen control LSI 61 outputs a request signal for requesting data conversion to the parallel / serial conversion circuit 63. The parallel / serial conversion circuit 63 converts the input image data 100 into interlaced data according to the request signal, and outputs the data to the D / A converter 7. The D / A converter 7 converts the interlaced data into the original NTSC data.
The signal is converted into an analog signal and output to the monitor TV8. Then, an image based on the NTSC signal is displayed on the monitor TV8.

As can be understood from the configuration shown in FIG. 4, when the selector 361 is selected on the A side, the memory 4
Performs normal data read / write operations. Therefore, even when the image data in the memory 4 is changed using the screen control LSI 61, the memory write signal 102 is used as it is as the write enable signal 10 to the memory 4.
It becomes 4.

Next, the operation when the image data 100 is input to the memory 4 will be described. When inputting the image data 100, first, the signal control circuit 50 receiving a command from the CPU 10 outputs a screen input signal to the selector 361 of the input / output determination circuit 360, and outputs a screen control LSI of the image output circuit 6.
The screen output signal is output to 61. At this time, the selector 361
Is selected on the B side. When this screen output signal is input, the screen control LSI 61 sends each request signal similar to that at the time of image data output to the memory management circuit 62 and the parallel / serial conversion circuit.
Output to 63. Here, since the selector 361 is selected on the B side by the screen input signal from the signal control circuit 50, the timing of the memory read signal 103 is adjusted via the delay circuit 362, and the write enable signal 104 is output to the memory 4. Then, the memory 4 is in a state of writing image data.

At this time, the image output circuit 6 is in an image output state, and the memory management circuit 62 outputs an image management signal 106 to the memory 4. The image management signal 106 and the write enable signal 104 cause the visual sensor 1 to output A
The image data 100 via the / D converter 2 is stored in the memory 4.

FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention. In this embodiment, a screen control LSI 61 is shown.
An LSI called a pack type which can simultaneously access a plurality of memory chips is used. In FIG. 5, portions denoted by the same reference numerals as those in FIG. 4 indicate the same portions, and thus description thereof is omitted. In FIG. 5, reference numeral 300 denotes a shift register which stores image data 100 from the A / D converter 2 in an amount that can be processed by the screen control LSI 61 at one time.
Is a signal control circuit for controlling the shift register 300 in addition to the operation of the signal control circuit 50 in the above embodiment.

Next, the operation will be described. The operation at the time of outputting the image data is the same as that of the above-described embodiment, and the description is omitted. At the time of image data input, the signal control circuit 51, which has received a command from the CPU 10, outputs a screen input signal to the selector 361, outputs a screen output signal to the screen control LSI 61, and outputs a shift register signal, as in the above-described embodiment. Output control signal to 300. When the shift register 300 receives the control signal, the shift register 300 accumulates image data 100 from the visual sensor 1 via the A / D converter 2 in an amount handled by the screen control LSI 61 at a time. According to the image management signal 106 and the write enable signal 104,
These are sequentially stored in the memory 4.

In the above embodiment, the case where the screen control LSI 61 is used as a component of the image output circuit 6 has been described. However, a screen control circuit having the same function as the screen control LSI 61 may be used. .

[0024]

As described in detail above, in the image processing apparatus according to the present invention, the image data reading means and the storage means are provided with a plurality
Image data to be written or read
And determining means for storing image data from the storage means.
When reading, the image management which is the output of the reading means
The signal and readout signal are stored in the memory
When outputting to a stage and writing image data to storage means
The image management signal by the decision means
The protruding signal is processed into a signal for writing image data.
Since the data is output to the storage means, a conventional image data writing circuit having a complicated circuit configuration becomes unnecessary, and the entire circuit configuration can be simplified. In addition, since an ordinary DRAM can be used as a memory for storing image data without using an expensive dual-port memory, a low-cost image processing apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a conventional image processing apparatus.

FIG. 2 is a block diagram showing an internal configuration of an image input circuit and an image output circuit in FIG.

FIG. 3 is a block diagram illustrating a configuration of another conventional image processing apparatus.

FIG. 4 is a block diagram illustrating a configuration of an image processing apparatus according to the present invention.

FIG. 5 is a block diagram illustrating a configuration of another image processing apparatus according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Visual sensor 2 A / D converter 4 Memory 6 Image output circuit 7 D / A converter 8 Monitor TV 9 Image processing circuit 10 CPU 50, 51 Signal control circuit 61 Screen control LSI 62 Memory management circuit 63 Parallel / serial conversion circuit 300 Shift register 360 I / O decision circuit 361 Selector 362 Delay circuit

Claims (1)

(57) [Claims] 1. A write image data from the vision sensor in the storage means, reading from the storage means the image data on the monitor
In the image processing apparatus for outputting images,
Image management, which is an address value string indicating the storage location of image data
Signal and a read signal for reading image data.
Image data reading means for inputting data and
The image data to be written or read
Reading out the image data from the storage means.
In this case, it is the output of the image data reading means.
The image management signal and the readout signal are passed through the determination means.
Output to the storage means as it is,
When writing data, the determining means
The readout signal is the image data and the image management signal is
An image processing device configured to process the data into a signal for writing data and output the processed signal to the storage unit .