JP3332570B2 - Video camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera for digitizing a video signal from an image sensor and performing arithmetic processing.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional video camera which digitizes a video signal and performs arithmetic processing. FIGS. 4 and 5 are timing charts showing the state of communication between a logical operation unit composed of a microcomputer or the like and the interface unit, and FIG. 6 shows the timing when data is written from the interface unit to the signal processing unit. FIG. 3 is a diagram in which data communication is performed between the logical operation unit and the signal processing unit through the interface unit.

In FIG. 3, reference numeral 1 denotes an imaging lens, 2 denotes an imaging device for photoelectrically converting a subject image (imaging light) projected by the lens 1 into an electric signal, and 3 denotes an analog video signal from the imaging device 2 which is digital. A / D converter for converting to a signal,
Reference numeral 4 denotes a signal processing unit which processes an A / D-converted digital signal to generate a video signal, 5 denotes an interface unit which reads or writes data from a data register in the signal processing unit 4, and 6 denotes an interface unit A microcomputer (hereinafter referred to as a microcomputer) which is a logical operation unit that receives read data or sends write data to the interface unit 5 processes a digital signal of a plurality of bits as data of one word. Reference numeral 7 denotes a D / A converter for converting a digital signal processed video signal into an analog signal.

In the signal processing section 4, 411-41
n is an n number of write registers (data registers) for writing data from the microcomputer 6, 421 to 42n are n number of read registers (data registers) for storing each data inside the signal processing unit 4 and sending the data to the microcomputer 6, Reference numeral 43 denotes a status register for holding a state as to whether data is stored in each of the read registers 421 to 42n for each register, and reference numeral 44 denotes each of the read registers 421 to 42n.
, An OR circuit for obtaining an interrupt signal from the load signal, a data selector 45, and a timing generator 46 for outputting a load signal to each of the read registers 421 to 42n at a predetermined timing.

In the interface section 5, 5
11 to 514 are address storage control registers;
Reference numeral 524 denotes a data storage control register, 53 denotes an address of a register to which data is to be transferred based on the output of the address storage control register 514, and a decoder for sending a transfer clock signal to the register. 54 denotes an address storage control. A counter that counts the number of words stored in the registers 511 to 514 and the data storage control registers 521 to 524 is a clock generator that generates a serial clock for data transfer to the microcomputer 6.

Each of the above registers is constituted by a shift register capable of serially inputting or outputting data by clock input.

In the above configuration, the subject image projected by the lens 1 is converted into an electric signal by the image sensor 2, converted into a digital signal by the A / D converter 3, and then input to the signal processing unit 4. .

The signal processing unit 4 receives data necessary for signal processing of the input digital signal from the microcomputer 6 via the interface unit 5, and the microcomputer 6 transmits data necessary for calculating the data. It is received from the signal processing unit 4 via the interface unit 5.

FIG. 4 shows a microcomputer 6 and an interface unit 5.
3 shows the timing of serial communication between the clock line (CLK), write data line (DW), and read data line (DW) in FIG.
R), and a line (MOD) for selecting each mode (MODE) of data reading, data writing, and addressing.
E).

As shown in FIG. 4A, when mode information for addressing is transmitted from the microcomputer 6 to the interface unit 5 through the MODE line, the interface unit 5 sends a clock signal to the microcomputer 6 through the CLK line. The microcomputer 6 sends an address signal through the DW line in synchronization with the clock signal.

The interface unit 5 receives the address signal and sets an address in an internal address register. Thereafter, for example, when data write mode information is transmitted from the microcomputer 6 through the MODE line, the interface unit 5 similarly sends a clock signal to the microcomputer 6 through the CLK line, as shown in FIG. 4B. In the microcomputer 6, the DW is synchronized with this clock signal.
A write data signal is sent through the line, and the interface unit 5 receives the write data.

In the interface section 5, the write data Da ₀ to Da _0-
The address Aa ₀ ~Aa ₇ of Da ₇ and the write destination at a timing shown in FIG. 5, stores temporarily transferred to the data storage control register 521 and address storing control register 511 of FIG.

Each of the above-mentioned control registers is constituted by a serial input / parallel output shift register, similarly to the above-mentioned write register in the signal processing section 4. For example, when a data write command is further issued from the microcomputer 6 in this state. , The data Da _{0 to} Da ₇ and the addresses Aa _{0 to} A
a ₇ is transferred similarly to the control registers 521,511, the next control register 52 data and address stored in the control register 521,511 to simultaneously now
2, 512, respectively. These data transfer is performed by the ADR-CLK, DATA-
This is performed at the timing shown in FIG. 5 by the clock of CLK.

In the above process, the write data and the transfer destination address sent from the microcomputer 6 are stored in the control registers 521 to 524, 5 during the effective video period of the video signal.
The data transfer to the target signal processing unit 4 is not performed only by storing the data in the data processing units 11 to 514. When the interface unit 5 obtains information on the retrace period of the video signal from the HBLK input, the address storage control register 51
The transfer destination address is determined based on the address information of the clock lines WCLK1 to WCLKn.
Clock signal for transmission through The data storage control register 52 is synchronized with this clock signal.
The data of 1 to 524 are transferred to the write registers 411 to 41n of the transfer destination through the WR line.

Next, the process of the above data communication will be described in detail with reference to FIG. The decoder 53 shown in FIG. 3 takes in address information from the parallel output of the control register 514 at the timing shown in the address setting in FIG. Further, the decoder 53 writes the set addresses of the write registers 411 to 41n.
, Only one of the clock lines WCLK1 to WCLKn is selected and the clock for communication is set to WCLK in FIG.
Output at the timings indicated by 1 to n. At the same time, a clock is sent to the control registers 521 to 524 at the timing shown by DATA-CLK in FIG.
Performs the parallel output shown in FIG. 6 in synchronization with this clock.

[0016] Then, these clock and data output, the data Da ₀ to DA ₇ and Db ₀ Db ₇ is taken into each address _{Aa 0 ~Aa 7, Ab 0 ~Ab} 7 write register.

In this case, since the data and the address sent from the microcomputer 6 during the effective video period are each two words, the control register 51 shown in FIG.
Addresses and data are stored in 511, 512 and 521 and 522, respectively, among the data 1 to 514, 521 to 524, and the control registers of the remaining 513, 514 and 523 and 524 are empty. Therefore, FIG.
In the data transfer timing shown in (1), "0" is output for both the data and the address at the transfer timing for the first two words.

Here, in the circuit of FIG. 3, the control register is provided with four words each for data storage and address storage. However, during the effective video period, the microcomputer 6 issues five or more data write commands to the interface unit. 5, the counter 54 indicates the number of transfers between the microcomputer 6 and the control register during the effective video period to ADRCLK.
When the count number becomes 4 or more, a prohibition command is given to the clock generator 55 in FIG.

The clock generator 55 does not output a communication clock even if the microcomputer 6 sends a write or address designation command to the interface unit 5 in accordance with the above-described prohibition command. At this time, the microcomputer 6 controls the control registers 511 to 514, 521 to 521 in the next flyback period.
It is in a standby state until the data and address of 524 are transferred to the signal processing unit 4.

In the signal processing unit 4 shown in FIG.
When a load signal is sent from the timing generator 46 to any of the read registers 421 to 42n, the read register loads predetermined data, and the load signal becomes an interrupt signal of the microcomputer 6 through the OR circuit 44. The bit of the status register 43 corresponding to the read register rises. This bit is held until the data loaded in the read register is read.

The load signal passed through the OR circuit 44 is
The microcomputer 6 interrupts the microcomputer 6, and at this time, the microcomputer 6 starts communication for obtaining information on which read register has been loaded. At this time, first, in order to set the address of the status register 43, the status register address is sent to the interface unit 5 through the DW line at the timing shown in FIG. Thereafter, the microcomputer 6 sends the MODE to the interface unit 5 as shown in FIG.
When the information of the data read mode is transmitted through the line, and the interface unit 5 receives the information of this mode, the data selector 4 receives the information of the data read mode based on the previously transmitted address.
5 is set so that the output of the status register 43 can be obtained. Further, a clock is sent only to the status register 43 through the clock lines RCLK1 to RCLKn shown in FIG. To the interface unit 5 through When this data is received by the interface unit 5, a clock signal is sent to the microcomputer 6 through the CLK line at the timing shown in FIG.
The data obtained from the status register 43 is sent through the R line.

The microcomputer 6 includes the status register 4
When receiving the data of No. 3, it is determined which read register of the signal processing unit 4 has been loaded based on the data,
The address of the register is sent to the interface unit 5 according to the timing shown in FIG. 4A, and the internal address of the interface unit 5 is set. After that, the microcomputer 6
Sends information of data reading to the interface unit 5 through the MODE line, and the interface unit 5 sends the data selector 45 based on the previously set address.
Is set, and a clock signal is sent to only the read register based on the address through the clock lines RCLK1 to RCLKn. Data is output from the read register in synchronization with the clock and transferred to the interface unit 5. The interface unit 5 sends the data through the RD line in synchronization with the clock signal on the CLK line at the timing shown in FIG. 4C.

[0023]

However, in a conventional video camera which performs the above-described data communication, the amount of data that can be communicated within one horizontal synchronization period of a video signal, that is, the amount of data between one line Is limited by the number of control registers of the interface unit regardless of the processing speed of the microcomputer.

For this reason, for example, in a camera autofocus system, a register for setting an area for capturing a focus signal in a video screen, or a system such as a white balance and an automatic exposure correction as well as an autofocus system, is similar. When one area is completed in one screen with respect to the register for area setting existing in the same area, and when data for the next area setting is transferred from the microcomputer on the same screen, many In some cases, a large amount of data is transferred, and the data cannot be stored in the control register and is carried over to the next line.

Normally, when setting a plurality of areas in one screen, each area is set as short as possible from the end of one area to the start of the next area, that is, a small number of lines. desirable. However, if the number of control registers is limited, a large number of lines are required for data transfer, and a desired area may not be set.

To avoid this, for example, it is conceivable to increase the number of control registers, but in this case, the amount of hardware increases. In addition, there is a limit to the retrace period during which transfer from the control register to the write register of the signal processing unit is possible. Depending on the clock rate, too many control registers may not be provided in the system.

The present invention has been made in view of the above problems, and a video camera which can transfer a predetermined amount of target data between a small number of lines and requires a small number of control registers. It is intended to provide.

[0028]

According to the present invention, there is provided a video camera, comprising: a signal processing section for processing a video signal photoelectrically converted by an image sensor and further digitized to generate a video signal; and a data register in the signal processing section. And a logical operation unit for performing data communication through the interface unit,
The interface unit includes a plurality of registers that hold addresses and data, an address determination unit that determines an address value to be transferred to the signal processing unit according to a predetermined condition, and an output of the control register according to a result of the determination. Switch means for selecting whether to output the logical operation unit, and stores the transfer data and the transfer destination address in the control register according to the transfer destination address of the data, and stores the transfer data and the transfer destination address from the control register during a blanking period of the video signal. It is configured to switch between transferring to the signal processing unit or transferring the transfer data and transfer destination address directly from the logical operation unit to the signal processing unit.

[0029]

According to the present invention, there is provided a discriminating means for discriminating between a register address which can be written in the address valid video period sent from the logical operation unit and a register address which is not so, and the discrimination result of this discriminating means A switch means for switching between the data sent from the logical operation unit and the output of the data of the control register and sending it to the write address in the signal processing unit is provided in the interface unit, and the address sent from the logical operation unit can be written within the effective video period. If there is no register address, the data is transferred to the signal processing unit via the control register during the retrace period, and if the register address is writable during the effective video period, the data is directly transferred to the signal processing unit. Causes the logical operation unit to transfer an amount of data exceeding the storage capacity of the control register during one line. If this is the case, if it is data of a register that can be written during the effective video period, it can be transferred directly to the signal processing unit without going through the control register, and the desired amount of data can be transferred during a small number of lines. it can.

[0030]

FIG. 1 is a block diagram showing a circuit configuration of a video camera according to an embodiment of the present invention. In the figure, 1-7
, 511 to 514, 521 to 524, and the elements inside the signal processing unit 4 and the elements inside the interface unit 5.
Elements 53 to 55 are the same as those of the circuit shown in FIG.

Reference numeral 56 denotes a switch (means) for switching the data line for the write register inside the signal processing unit 4 between the data line from the microcomputer 6 and the output line of the control register, and 57 transfers the signal line from the microcomputer 6 to the signal processing unit 4. An address discriminator (determining means) for discriminating the transmitted address value based on a predetermined condition determines whether or not the address value can be transferred to the signal processing unit 4 during the effective video period. The switch 56 is provided to select between the output of the control register and the output of the microcomputer 6 according to the result of determination by the address determiner 57.

The transfer data and the transfer destination address are stored in the control register according to the transfer destination address of the data, and are transferred from the control register to the signal processing unit 4 during the blanking period of the video signal, or are directly transferred. It is configured to switch whether to transfer the transfer data and the transfer destination address from the microcomputer 6 to the signal processing unit 4.

FIG. 2 shows the communication between the microcomputer 6 and the interface unit 5 and the communication between the interface unit 5 and the signal processing unit 4 when the address value sent from the microcomputer 6 can be transferred to the signal processing unit 4 during the effective video period. It is a figure showing a timing.

Although there are some registers in the write address group in the signal processing section 4 which cannot be written in the effective video period, the registers may be written in the effective video period, that is, data is rewritten in the effective video period. There are also registers where transfer noise does not affect the video signal. For example, the above-described register group for setting each area is only for giving a setting value of a circuit that gates a signal input necessary for an autofocus system or the like, and one area ends and the next area starts. Up to this point, even if the data is rewritten during the effective video period, it does not directly affect the video signal.

Therefore, in the present embodiment, the address discriminator 57
To determine whether the transfer destination address value from the microcomputer 6 can be transferred to the signal processing unit 4 during the effective video period, switch the switch 56 based on the determination result, and transfer the transfer data to the control register in the interface unit 5. And the transfer destination address is stored, and it is possible to select whether to transfer from the control register to the signal processing unit 4 during the retrace period of the video signal or to directly transfer from the microcomputer 6 to the signal processing unit 4.

That is, when addressing mode information is transmitted from the microcomputer 6 to the interface unit 5 shown in FIG. 1 through the MODE line, the interface unit 5 sends a clock signal to the microcomputer 6 through the CLK line. The microcomputer 6 sends an address signal through the DW line in synchronization with this clock.

Upon receiving the address signal, the interface unit 5 sets an address in an internal address register. The address discriminator 57 determines whether or not the address value set in the address register can be transferred to the signal processing unit 4 within the effective video period. The address value and the data sent from the microcomputer 6 are transferred to the address storage control register 511 and the data storage control register 521, respectively. This data is transferred to a target write register inside the signal processing unit 4 in the next flyback period.

On the other hand, if the address discriminator 57 determines that the address value sent from the microcomputer 6 can be transferred to the signal processing section 4 within the effective video period, the control output from the address discriminator 57 is used. The switch 56 is switched from the control register output side to the data output side of the microcomputer 6, and the decoder 53 is controlled to set the address by giving priority to the serial input from the microcomputer 6.

FIG. 2 shows the timing of the above-described process. When an address designation command is sent from the microcomputer 6 to the interface unit 5 through the MODE line, the clock generator 55 outputs the clock signal of CLK shown in FIG. Then, the microcomputer 6 synchronizes with the signal and outputs Aa ₀ to Aa _7.
Is sent to the interface unit 5 through the DW line. The address discriminator 57 inside the interface unit 5 determines that the address value Aa can be directly transferred to the signal processing unit 4, and sets the address value Aa in the decoder 53 at the timing shown in the figure. Then, the microcomputer 6 sends a data write command to the interface unit 5, the clock generator 55 sends the clock signal of the CLK through the CLK line to the microcomputer 6, data Da ₀ to DA ₇ microcomputer 6 in synchronization therewith The signal is sent to the interface unit 5 through the DW line.

Here, the switch 56 is switched to the data output side of the microcomputer 6 according to the result of the discrimination by the address discriminator 57, and the data signal Da from the microcomputer 6 is output.
₀ to DA ₇ is sent directly through WD lines to each serial input port of the internal write register 411~41n of the signal processing unit 4. Based on the previously set address value Ab, the decoder 53 performs only the write register of this address through the clock lines CLK1 to CLKn as shown in FIG.
Are sent to the signal processing unit 4.
Then, the data Da is written into the selected write register inside the signal processing unit 4 at the timing shown in FIG.

[0041] Thereafter, if further when the address signal Ab ₀ to ab ₇ in addressing shown in FIG. 2 is sent from the microcomputer 6, transferable address value the address value Ab is to the signal processing unit 4 to the effective video period Address setting is performed in the same manner, and then the data signal D sent from the microcomputer 6 is transmitted.
b ₀ Db ₇ is transferred to the write register of the address value, data value Db is written.

In the above transfer process, when the address discriminator 57 determines that the current address value can be transferred to the signal processing section 4 during the effective video period, the clock generator 5
5 is sent to ADR-CLK and DATA-CLK. As a result, the clock generator 55 controls the control registers 511 to 514 and 521 to 52
The output of the clock to 4 is stopped. Therefore, the counter 54 that counts the number of words stored in the control register does not increase the count value.

As described above, if the address value sent from the microcomputer 6 is an address of a register that cannot be written within the effective video period, the data is transferred to the signal processing unit 4 via the control register during the flyback period. If the address of the register is writable within the effective video period, the data is transferred directly to the signal processing unit 4 so that the microcomputer 6
Is trying to transfer an amount of data that exceeds the capacity of the control register during one line, and if it is a register address that can be written during the effective video period, the signal is processed directly without the control register. It is possible to transfer a desired amount of data to the unit 4 during a small number of lines, thereby reducing the number of control registers.

[0044]

As described above, according to the present invention,
A plurality of registers, an address discriminating unit for discriminating an address value from the logic operation unit, and an output of the control register according to the discrimination result. A switch is provided to select whether the output of the logic operation unit is provided. Depending on the transfer destination address of the data from the logic operation unit, the data is transferred to the signal processing unit through the control register or directly from the logic operation unit to the signal processing unit. Since it is possible to select whether or not to do so, it is possible to transfer a desired predetermined amount of data between a small number of lines, and there is an effect that the number of control registers can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing communication timing of the circuit of FIG. 1;

FIG. 3 is a block diagram showing a circuit configuration of a conventional example.

FIG. 4 is a diagram showing communication timing of the circuit of FIG. 3;

FIG. 5 is a diagram showing communication timing of the circuit of FIG. 3;

FIG. 6 is a diagram showing communication timing of the circuit of FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 lens 2 imaging device 3 A / D converter 4 signal processing unit 5 interface unit 6 microcomputer (logical operation unit) 7 D / A converter 56 switch (switch means) 57 address discriminator (address discriminating means) 411-41n Write registers (data registers) 421 to 42n Read registers (data registers) 511 to 514 Address storage control registers 521 to 524 Data storage control registers

Claims (1)

(57) [Claims] 1. A signal processing unit for processing a video signal photoelectrically converted by an imaging device and further digitized to generate a video signal, and a logical operation unit for performing data communication through a data register and an interface unit in the signal processing unit The interface unit comprises: a plurality of registers for holding addresses and data; address determining means for determining an address value to be transferred to the signal processing unit according to predetermined conditions; and the control register according to a result of the determination. And switch means for selecting between the output of the logical operation unit and the output of the logical operation unit. The transfer is performed from the control register to the signal processing unit, or the transfer data and the transfer destination address are directly transmitted from the logical operation unit. A video camera characterized in that it is configured to switch whether or not to transfer the address to a signal processing unit.