JP3697258B2 - Video camera and video signal processing method - Google Patents

Description

  The present invention relates to a video camera and a video signal processing method for digitally processing a video signal.

  An example of data communication between a logic operation unit (hereinafter referred to as a microcomputer) and a signal processing unit in a conventional video camera (hereinafter referred to as a digital camera) that performs digital operation processing on a video signal will be described with reference to FIGS. I will explain.

  FIG. 1 is a block diagram showing the configuration of the digital camera, and FIG. 2 is a timing diagram showing a communication state between the microcomputer and the interface.

  In FIG. 1, 1 is a lens, 2 is an image sensor that converts an object image projected by the lens 1 into an electrical signal, 3 is an A / D converter that converts a video signal from the image sensor into a digital signal, and 4 is an A A signal processing unit 5 that performs arithmetic processing on the / D-converted digital signal, 5 is an interface unit that reads or writes a data register in the signal processing unit 4, and 6 receives data read by the interface unit 5, and performs predetermined processing. A microcomputer 7 that performs or sends write data to the interface unit 7 is a D / A conversion unit that converts the processed video signal into an analog signal.

  In the signal processing unit 4, reference numerals 411 to 41 n are write registers for writing data received from the microcomputer 6 by the interface unit 5. The data stored in these registers is a process of processing a video signal in the signal processing unit 4. Required data (for example, AGC gain, white balance R, G, B gain, autofocus area setting value, etc.). Read registers 421 to 42n store each data inside the signal processing unit 4 and send it to the microcomputer 6. Reference numeral 43 denotes a status for holding for each register whether or not data is stored in each read register 421 to 42n. A register 44 is an OR circuit that obtains an interrupt signal from the load signals L1 to Ln of each read register, and 45 is a data selector. The above registers are shift registers that can input and output data serially by clock input. A timing generator 46 generates a load signal to each register at an appropriate timing in the process of signal processing.

  The subject image projected from the lens 1 is converted into an electrical signal by the image sensor 2, converted into a digital signal by the A / D converter 3, and sent as a signal to the signal processor 4. The signal processing unit 4 receives necessary data from the microcomputer 6 via the interface unit 5 in the process of processing the digital signal input from the A / D conversion unit 3. The microcomputer 6 receives data necessary for calculating the data from the signal processing unit 4 via the interface unit 5.

  FIG. 2 shows a timing diagram of serial communication between the microcomputer 6 and the interface unit 5. The communication during this period includes a clock line indicated by CLK in FIG. 1, a write data line indicated by DW, a read data line indicated by DR, and a MODE line for selecting data reading, data writing and addressing modes indicated by MODE. Is done by.

(Specify address)
As shown in FIG. 2A, when the addressing mode information is output from the microcomputer 6 to the interface unit 5 through the MODE line, the interface unit 5 sends a clock signal to the microcomputer 6 through the CLK line. The microcomputer 5 sends address signals (A0 to A7) via the DW line in accordance with this clock. The interface unit 5 receives this address signal and sets an address in an address register (not shown) in the interface 5.

(Data writing)
Thereafter, when data write mode information is output from the microcomputer 6 via the MODE line, for example, as shown in FIG. 2B, the interface unit 5 sends a clock signal to the microcomputer 6 through the CLK line as in the case of address designation. send. The microcomputer 6 sends write data signals (D0 to D7) via the DW line in synchronization with this clock, and the interface unit 5 receives this write data. At this time, the interface unit 5 sends a signal to WCLK1... N in FIG. 1 corresponding to the register of the address based on the previously set address, and writes it through the write line indicated by WD in synchronization with the clock signal. Transfer data.

(Reading status data)
In the signal processing unit 4 shown in FIG. 1, data is loaded into one of the read registers 421 to 42n through one load signal L1 to Ln by a load signal generated from the timing generator 46 based on the determined timing. In this case, the load signal becomes an interrupt signal for the microcomputer 6 through the OR circuit 44, and the bit of the status register 43 corresponding to the read register is raised, and the data loaded in the read register is read from this bit. Is held until Now, the load signal that has passed through the OR circuit 44 interrupts the microcomputer 6 via the IRQ line shown in FIG. The microcomputer 6 starts communication for obtaining information on which read register is loaded with data.

  In communication, first, in order to set the address of the status register 43, the status register address is sent to the interface unit 5 through the DW line at the timing shown in FIG. Next, the microcomputer 6 sends the read mode information to the data via the MODE line to the interface unit 5 as shown in FIG. 2C. When the interface unit 5 receives this mode information, the address sent earlier is sent. 1 is set so that the output of the status register 43 can be obtained, and RCLK1... N of FIG. 1 corresponding to the status register is sent to the signal processing unit 4. The status register 43 transfers data to the interface unit 5 through the RD line in synchronization with this clock. When the interface unit 5 receives this data, it sends a clock signal to the microcomputer 6 via the CLK line at the timing shown in FIG. 2C, and synchronizes with this via the data RD line obtained from the status register 43. Send it out.

(Reading data from the read register)
Next, when the microcomputer 6 receives the data of the status register 43, the microcomputer 6 determines which read register of the signal processing unit 4 is loaded from the data of the status register 43, and sets the address of the register in FIG. The data is sent to the interface unit 5 according to the timing of A. The interface unit 5 sets an address inside the interface. Thereafter, data read information is sent from the microcomputer 6 to the interface unit 5 through the MODE line. The interface unit 5 sets the data selector 45 based on the previously set address, and corresponds to the read register based on the address. RCLK1 ... n signals are sent. Data is output from the corresponding read register in synchronization with the clock and transferred to the interface unit 5 as RD. The interface unit 5 sends this data to the microcomputer 6 as an RD line in synchronism with the clock signal on the CLK line at the timing shown in FIG.

  However, in the above conventional example, (1) address designation of the status register 43 and (2) status after the read register is loaded inside the signal processing unit 4 until the microcomputer 6 actually receives the data of the read register. It is necessary to perform four serial communications such as register data transfer, (3) read register address specification, and (4) read register data transfer, and a lot of time is spent when the clock of the microcomputer is slow. Will slow down. That is, in the case of autofocus for adjusting the focus state of the optical system of the camera, the responsiveness deteriorates, and the responsiveness of the auto iris or the like for adjusting the incident light amount of the optical system deteriorates.

  In view of the above-described conventional problems, the present invention shortens the data read time from the read register, increases the processing speed of the video signal, and, for example, responsiveness such as autofocus for adjusting the focus state of the optical system of the camera. Or a video camera with improved responsiveness such as auto iris for adjusting the amount of incident light of the optical system.

  The present invention has been made for the purpose of solving the above-described problems, and includes the following configurations.

A microcomputer that outputs an address of a register to be accessed and data to be stored in the register, a plurality of write registers that store data output from the microcomputer, a plurality of read registers that store internal data, A status register for storing status information as to whether or not data is stored in the read register; and a signal processing unit interposed between the microcomputer and the signal processing unit, and the microcomputer and the signal processing A clock signal is supplied to the unit, and an address output from the microcomputer is input in synchronization with the clock signal. After the address is input, the microcomputer and the address correspond to the clock signal in synchronization with the clock signal. An interface unit for transferring data between the write register and the read register. A clock signal when the interface unit inputs data or an address output from the microcomputer is also supplied to the status register, and status information from the status register output in synchronization with the clock signal is supplied to the interface unit. By directly inputting to the microcomputer without going through, the data transfer or address transfer from the microcomputer and the reading of the status information of the status register to the microcomputer are performed substantially simultaneously in parallel, and the read status information is There is provided a video camera characterized in that a microcomputer is used to specify a read register to be subsequently accessed . Here, the status register further stores, as the status information, return section information indicating the timing of the return period of the video signal, and the microcomputer is configured to return the return section based on the return section information. Data transfer is performed at .
A microcomputer for outputting an address of a register to be accessed and data to be stored in the register; a plurality of write registers for storing data output from the microcomputer; a plurality of read registers for storing internal data; A status register that stores status information as to whether or not data is stored in each of the read registers; and a signal processing unit that is interposed between the microcomputer and the signal processing unit. Supply a clock signal to the signal processing unit, input an address output from the microcomputer in synchronization with the clock signal, and input the address, and then correspond to the microcomputer and the address in synchronization with the clock signal And an interface unit for transferring data between the write register and the read register. A camera video signal processing method, the status of the interface unit also supplies the clock signal when receiving the output data or the address from the microcomputer to the status register, and output in synchronization with the clock signal By directly inputting the status information from the register to the microcomputer without going through the interface unit, data transfer or address transfer from the microcomputer and reading of the status information of the status register to the microcomputer are omitted. Provided is a video signal processing method for a video camera, which is performed in parallel at the same time, and the read status information is used to specify a read register to be accessed thereafter by the microcomputer .

  According to the present invention, the time for reading data from the read register is shortened, the processing speed of the video signal is increased, for example, the responsiveness such as autofocus for adjusting the focus state of the optical system of the camera, or the incident light quantity of the optical system. It is possible to provide a video camera with improved responsiveness such as adjusting auto iris.

  That is, as described in the fourth embodiment, in the communication between the microcomputer 6 and the interface unit 5, when an address signal or data is transferred from the microcomputer 6 to the interface unit 5 through the DW line, the status is always transmitted via the DR line. By transferring data to the microcomputer, the number of serial communications between the signal processing unit 4 and the microcomputer 6 can be shortened. Further, by adding HD and VD information to the status information, the signal processing unit 6 is transmitted from the microcomputer 4. Even when data is transferred to the internal write register, data can be transferred at an appropriate timing.

(Example 1)
An embodiment of the present invention will be described with reference to FIGS. 3, 4 and 5, and FIGS. FIG. 3 is a block diagram showing the configuration of the embodiment of the present invention, and FIGS. 4 and 5 are diagrams showing the timing of serial communication between the microcomputer 6 and the interface 5 and the signal processing unit 4 shown in FIG.

  In FIG. 3, elements 1 to 6 and 4 are the same as those in the conventional example shown in FIG. In the interface 5, 511 to 514 are address storage control registers, 521 to 524 are data storage control registers, 53 is an address setting of the register to which data is to be transferred by the output of the address storage control register 514, and the registers Is a decoder that sends a clock signal to the.

  Now, the microcomputer 6 gives a data write command to the interface unit 5 through the MODE line, and the interface unit 5 sends a clock signal to the microcomputer 6 through the CLK line in the same manner as the communication timing of the conventional example shown in FIG. In 6, data is transferred to the interface unit 5 in synchronization with the clock signal. FIG. 4 shows the timing of this communication. As in the conventional example, the address of the register to which data is written is transferred to the interface unit 5 in advance by the communication indicated by (1) in FIG.

  In the interface unit 5, the write data Da0 to Da7 and the write destination addresses Aa0 to Aa7 fetched from the microcomputer 6 in the above process are shown in FIG. 3 according to the procedure of timings (1) and (2) shown in FIG. The data is temporarily transferred to the data storage control register 521 and the address storage control register 511 for storage. Each control register in the interface unit 5 is composed of a serial input / parallel output shift register, for example, like the write register in the signal processing unit 4. For example, in this state, a data write command is further sent from the microcomputer 6. If there is, the data Da0 to Da7 and the address Aa0 to Aa7 are similarly transferred to the control registers 521 and 511, simultaneously transferred to the control registers of the previous control registers 521 and 511, and simultaneously the previous control registers 521 and 511 are transferred. The data and address stored in are transferred as shifts to the next control registers 522 and 521, respectively. These data transfers are performed at the timing shown in FIG. 4 using the ADR_CLK and DATA_CLK clocks shown in FIG.

  The write data and the transfer destination address sent from the microcomputer 6 in the above process are stored in the control registers 521 to 524 and 511 to 514 in the effective video period of the video signal, and the data to the signal processing unit 4 is stored. No transfer is performed. When the interface unit 5 obtains information on the blanking period of the video signal from the HBLK input, the transfer destination register is determined based on the address information in the address storage control registers 511 to 514, and only for this, the clock lines WCLK1 to WCLK1 A clock signal is sent through one of n, and data in the data storage control registers 521 to 524 is transferred to one of the write registers 411 to 41n as transfer destinations through the WR line in synchronization with this clock signal.

  This process will be described in detail with reference to FIG.

  In the above process, the decoder 53 shown in FIG. 3 fetches address information from the parallel output of the control register 514 at the timing shown in FIG. 5 to set the address. Further, the decoder 53 selects one of the clock lines WCLK1 to WCLK for only one of the write registers 411 to 41n of the set address, and supplies a clock for communication as shown in FIG. It occurs at the timing indicated by ~ n. At the same time, a clock is sent to the control registers 521 to 524 at the timing indicated by DATA_CLK in FIG. 5, and the control register 524 outputs the serial output shown in FIG. 5 in synchronization with this clock. By this clock and data output, data Da0 to Da7 and Db0 to Db7 are taken into the write registers of Aa0 to Aa7 and Ab0 to Ab7, which are the respective addresses.

  In this case, since the data and address sent from the microcomputer 6 within the effective video period are two words each, at the start of the retrace period, 511 and 512 of the control registers 511 to 514 and 521 to 524 shown in FIG. Address is stored in 521 and 522, and the remaining control registers 513 and 514 and 523 and 524 are empty. Therefore, at the data transfer timing shown in FIG. 5, at the transfer timings (1) and (2) for the first two words, both the data and the address are output as “0”.

(Example 2)
In the first embodiment, if there are many data write commands from the microcomputer 6 within one effective video period, the allowable amount that can be stored in the control register of the interface unit 5 may be exceeded. At this time, the data is not transferred in order from the first stored data and address, and the data is shifted and the contents are lost.

  On the other hand, even if there is no data write command from the microcomputer in one effective video period, data transfer is performed while it is empty in the next blanking period, and power consumption is equivalent to this operation. Will increase.

  In this embodiment, a counter is provided for counting the number of control registers stored by a data write command from the microcomputer 6 in one effective video period, and transfer data and transfer destination address are stored in all the control registers according to the count value of this counter. When stored in an untransferred state, a prohibit command is given to the clock generator that generates a clock for the microcomputer, so that no clock is given to the microcomputer, and nothing is in effect during the end of one effective video period. When there is no data write command from the microcomputer, this is determined by the count value of the counter, and even if the blanking period is reached, data transfer from the control register to the signal processing unit 4 is not performed. Even if a write command exceeding the allowable amount of the control register is sent from the microcomputer 6 during the video period, The microcomputer 6 is kept waiting until the effective video period is reached to prevent data loss in the control register. Furthermore, when all the control registers are empty, wasteful transfer to the signal processing unit is prevented even during the retrace period. The power is reduced.

  Hereinafter, this will be specifically described with reference to FIG.

  FIG. 6 is a block diagram showing the same atmosphere with the same reference numerals or numbers as in FIG. 1 or FIG. 3, and 54 is stored in the address storage control registers 511 to 514 and the data storage control registers 521 to 524. A counter 55 for counting the number of words is a clock generator for generating a clock signal.

  When an address designation and data write command is sent from the microcomputer 6 to the interface unit 5, the address and data are transferred to the control registers 521 and 511, respectively. At this time, the counter 54 counts the address clock signal ADR_CLK, and counts how many words of addresses and data are transferred to the control register in one effective video period.

  In this embodiment, the control register is provided for each of four words for data storage and address storage, but when the microcomputer 6 gives five or more data write commands to the interface unit 5 in the effective video period. The counter 54 counts the number of transfers between the control registers from the microcomputer 6 within the effective video period with the ADR_CLK signal, and when the count number becomes 4 or more, it gives a prohibit command to the clock generator 55 shown in FIG. With this prohibition instruction, the clock generator does not generate a clock for communication even if the microcomputer 6 writes or sends an address designation instruction to the interface unit 5. In this case, the microcomputer 6 is in a standby state until the data and addresses of the control registers 511 to 514 and 521 to 524 are transferred to the signal processing unit 4 in the next blanking period.

  Also, when there is no data write command from the microcomputer in one effective video period, this is judged by the counter 54 based on the count value, and a prohibition command for each clock of ADR_CLK and DATA_CLK is issued. The clock generator 55 is prevented from generating a clock signal for the control register. In this case, data transfer from the control registers 511 to 514 and 521 to 524 to the signal processing unit 4 is not performed.

  In general, in the slave mode in which the clock of the serial communication of the microcomputer is generated from the side that receives data from the microcomputer, when the clock is stopped, the microcomputer 6 stops all operations and enters a standby state until the clock is sent. In this embodiment, the standby state continues until the retrace period, but if it is desired that the microcomputer perform computations during this time, an input / output port is provided between the microcomputer 6 and the interface unit 5 separately. It is also conceivable that information indicating whether or not the control register is free is given, and that the microcomputer 6 prevents the write command from being issued when there is no free space in the control register. In this case, other operations can be performed even during standby.

(Example 3)
In the above embodiment, when a data write command is received from the microcomputer 6, data and address are once stored in the control register of the interface unit 5, and then one data transfer is performed to transfer data from the control register to the signal processing unit. In this case, a microcomputer having a low clock rate may not be able to transfer the necessary number of data during the vertical blanking period.

  In the present embodiment, address designation in the decoder unit 23 is performed directly by the data line output of the microcomputer during vertical blanking, and a changeover switch is provided between the data output to the write register of the signal processing unit 4 and the control register output, Data output to the write register of the signal processing unit 4 is switched between the control register and the data line from the microcomputer 6 by a vertical blanking period signal (hereinafter abbreviated as VBLK), and the control register is not passed during the vertical blanking period. By performing data communication, a microcomputer having a low clock rate can transfer a necessary amount of data within the vertical blanking period.

  Hereinafter, the present embodiment will be described in detail with reference to FIGS.

  FIG. 7 is a block diagram showing the configuration of the embodiment of the present invention, and FIG. 8 is a diagram showing the timing of communication between the microcomputer 6 and the interface unit 5 and between the interface unit 5 and the signal processing unit 4 in the vertical blanking period.

  In FIG. 7, each element from 1 to 7 and each element from 511 to 514, 521 to 524, 53 to 55 inside each element 5 inside 4 are the same as those shown in FIG. This is a switch for switching the data line for the write register in the signal processing unit 4 between the data line from the microcomputer and the output line from the control register.

  When the VBLK signal is in a video period other than the vertical blanking period of the video signal, the decoder 53 in the interface unit 5 shown in FIG. 7 gives priority to the parallel output of the control register 514 as in the above embodiment. Address designation is performed. At this time, the switch selects the serial output side of the control register 524. In this state, the video period other than the vertical blanking period is processed via the control registers 511 to 514 and 521 to 524 in the same manner as in the above embodiment when there is a data write command from the microcomputer 6.

  During the vertical blanking period, this is detected by the VBLK signal, and the decoder 53 prioritizes serial input from the microcomputer 6 and performs address setting. FIG. 8 shows this process. As shown in (1) of FIG. 8, when the address designation command is sent from the microcomputer 6 to the interface unit 5 via the MODE line, the clock generator 55 generates CLK, and the microcomputer 6 synchronizes with this CLK. The address signals indicated by Aa0 to Aa7 are sent to the interface unit 5 via the DW line. The decoder 53 inside the interface unit 5 performs address setting at the timing shown in FIG. After the address Aa is set, when the microcomputer 6 sends a data write command to the interface unit 5 as shown in (2), the clock generator 55 similarly sends a clock signal to the microcomputer 6 through the CLK line. In synchronization with this, the data signals shown in FIGS. 8Da0 to Da7 are sent to the interface side via the DW line.

  Here, in the vertical blanking period, the switch 56 is selected on the DW line side from the microcomputer, and the data signal from this microcomputer is directly connected to each of the write registers 411 to 41n in the signal processing unit 4 via the WD line. Sent to serial input. Based on the previously set address Aa, the decoder 53 sends the clock shown in FIG. 8 to the signal processing unit 4 through the clock lines CLK1 to CLKn only to the write register of this address. Data Da (Da0 to Da7) is written to the selected write register in the signal processing unit 4 at the timing shown in FIG.

  Thereafter, even if the address signals Ab0 to Ab7 and the data write commands Db0 to Db7 are sent by the address designation shown in FIG. 8, the addresses shown in Ab (Ab0 to Ab7) are the same as described above if they are within the vertical blanking period. Setting is performed, and data indicated by Db (Db0 to Db7) is written in a write register corresponding to the setting.

  Here, the period during which data can be directly transferred from the microcomputer to the signal processing unit 4 is not limited to the vertical blanking period. For example, in the area designation for obtaining the information of the video signal for performing autofocus, data may be directly transferred to the write register for this area designation during a period other than the area designated in the video screen. Further, even if this type of data is in an effective video period, transfer noise does not affect the screen.

  Therefore, even if such data is outside the vertical transfer period, it can be considered that the data is directly transferred from the microcomputer to the signal processing unit based on the set address in the decoder.

(Example 4)
This embodiment will be described with reference to FIGS. 9, elements 1 to 7 and elements inside element 4 are the same as those in the conventional example shown in FIG. 1, and 46 is a data line changeover switch. FIG. 10 shows the timing of serial communication between microcomputer 6 and interface 5 shown in FIG.

  When any one of the read registers 421,... 42n is loaded in the signal processing unit 4 shown in FIG. 9, the status register bit corresponding to the loaded register is set and the register is transferred. Hold. On the other hand, the load signal interrupts the microcomputer 6 via the OR circuit 44, and the microcomputer 6 performs appropriate data transfer by this interrupt. Therefore, if it is necessary to write some data to the set address before the interruption occurs, the data is transferred. If it is not necessary, communication is performed to specify an appropriate address.

  In the interface unit 5, the data line selector switch 46 is switched to the output side of the status register, and the interface unit 5 sends a clock to the status register 43 in synchronism with the timing of transferring data or address from the microcomputer 6 to the interface unit 5. As shown in FIGS. 10A and 10B, the status register 43 transfers the data in the status register to the microcomputer 6 via the DR line in synchronization with the clock. In the above process, the communication for the microcomputer 6 to receive the data of the status register 43 which is the address information of the read register after the read register is loaded inside the signal processing unit 4 is shown in A and B of FIG. Any one of the serial communications can be performed.

  In order to receive the data of the status register 43 and then the data of the loaded read register, the microcomputer 6 receives two serial communications for addressing and data reading with respect to the interface unit 5 as in the conventional example. Can be done. Further, when another read register is loaded again before the address designation communication at this time and the microcomputer 6 is interrupted, the data in the status register 43 is transferred simultaneously with the address designation communication. At this time, the microcomputer 6 obtains address information of the next read register to be read.

  As described above, when loading of the read register in the signal processing unit 4 continues, the microcomputer 6 designates an address of a certain read register to the interface unit 5 and at the same time, the read register to be read next by the status register information. Since the address information can be obtained, reading of data from one read register requires only two communications, address designation and data read.

  Here, the data stored in the status register 43 need not be limited to the address information of the read register. For example, a horizontal synchronizing signal and a vertical synchronizing signal (hereinafter abbreviated as HD and VD, respectively) synchronized with the video signal of the video camera play an important role in the signal processing process. In some cases, it is more convenient to consider the timing of the synchronization signal. For example, when data for adjusting signal gain, color balance, etc. is transferred from the microcomputer 6 to the signal processing unit in the signal processing process, the data shift of the write register will occur if it is transferred within the effective video area of the video signal. In the middle, data in the middle of shifting that is completely different from the data to be written to be newly set may be output to the signal processing unit 4, and the effect of this output may appear as noise in the video screen depending on the register. .

  For this reason, there is a register that is better to transfer data in the blanking area of the video. Such a register is determined by the microcomputer 6 and transferred during the blanking period in consideration of the timing of HD and VD. The HD and VD information for this purpose can be obtained by providing dedicated bits in the status register 43 and status information read during register addressing and data transfer. The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can also be applied to a case where the present invention is achieved by supplying a program to a system or apparatus.

It is a block diagram which shows the structure of a prior art example. It is a timing chart which shows operation | movement of a prior art example. It is a block diagram which shows the structure of the 1st Example based on this invention. It is a timing chart in the 1st example. It is another timing chart in a 1st Example. It is a block diagram which shows the structure of the 2nd Example which concerns on this invention. It is a block diagram which shows the structure of the 3rd Example based on this invention. It is a timing chart in the 3rd example. It is a block diagram which shows the structure of the 4th Example based on this invention. It is a timing chart in the 4th example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lens 2 Image pick-up element 3 A / D conversion part 4 Signal processing part 5 Interface part 6 Microcomputer 7 D / A conversion part 43 Status register 44 OR circuit 45 Data selector 46 Data line changeover switch 411-41n Write register 421-42n Reading Register 53 Decoder 54 Counter 55 Clock generator 56 Changeover switch 511 to 514 Address storage control register 521 to 424 Data storage control register MODE mode line CLK clock signal DW data write DR data read IRQ interrupt WD write data WCLK1 to WCLKn write clock RCLK1 to RCLKn Read clock ADR_CLK Clock to set address DATA_CLK Clock to set data Click HBLK horizontal blanking interval signal VBLK vertical blanking period signal

Claims (3)

  A microcomputer that outputs the address of the register to be accessed and the data to be stored in the register;
  A plurality of write registers for storing data output from the microcomputer, a plurality of read registers for storing internal data, and a status register for storing status information as to whether data is stored in each of the read registers A signal processing unit comprising:
  Intervening between the microcomputer and the signal processing unit, supplying a clock signal to the microcomputer and the signal processing unit, inputting an address output from the microcomputer in synchronization with the clock signal, An interface unit for transferring data between the microcomputer and a write register and a read register corresponding to the address in synchronization with the clock signal after inputting the address;
  Supplying a clock signal when the interface unit inputs data or an address output from the microcomputer to the status register,
  By directly inputting the status information from the status register output in synchronization with the clock signal to the microcomputer without going through the interface unit, data transfer or address transfer from the microcomputer and the microcomputer to the microcomputer Reading the status information of the status register in parallel at substantially the same time,
  A video camera characterized in that the read status information is used to specify a read register to be subsequently accessed by the microcomputer.   The status register further stores, as the status information, return section information indicating the timing of the return period of the video signal, and the microcomputer transfers data in the return section based on the return section information. The video camera according to claim 1, wherein:   A microcomputer that outputs an address of a register to be accessed and data to be stored in the register, a plurality of write registers that store data output from the microcomputer, a plurality of read registers that store internal data, A status register for storing status information as to whether or not data is stored in the read register; and a signal processing unit interposed between the microcomputer and the signal processing unit, and the microcomputer and the signal processing The clock signal is supplied to the unit, the address output from the microcomputer is input in synchronization with the clock signal, and the address corresponding to the microcomputer and the address is input in synchronization with the clock signal after the address is input. And an interface unit for transferring data between the read register and the read register. A La of the video signal processing method,
  Supplying a clock signal when the interface unit inputs data or an address output from the microcomputer to the status register,
  By directly inputting the status information from the status register output in synchronization with the clock signal to the microcomputer without going through the interface unit, data transfer or address transfer from the microcomputer and the microcomputer to the microcomputer Reading the status information of the status register in parallel at substantially the same time,
  A video signal processing method of a video camera, wherein the read status information is used to specify a read register to be accessed thereafter by the microcomputer.

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