JP4724394B2 - Imaging apparatus and camera - Google Patents

Description

The present invention is related to an imaging apparatus and a camera.

  Many digital systems are composed of a large number of peripheral devices centering on a CPU (Central Processing Unit) that controls the entire system. The CPU performs complex signal processing and gives various commands to peripheral devices to control the system. For example, in a digital camera system, which is an example of a digital system, the CPU not only performs high-speed correction processing, compression processing, resolution conversion processing, etc. on the captured image signal, but also the imaging system, recording system, and display through communication control means. System and mechanical system are controlled.

  FIG. 13 is a diagram showing the configuration of the imaging system of the digital camera system. 1301 is a solid-state image sensor, and 1302 is an AD converter that converts an analog image signal 1351 from the solid-state image sensor 1301 into a digital image signal 1355. The timing generation device 1306 outputs the operation timing of the solid-state imaging device 1301 to the timing signal group 1360 and outputs the operation timing of the AD conversion device 1302 to the timing signal group 1361. Reference numeral 1307 denotes a CPU for controlling the system, and an operation mode of each unit is set by a control signal group 1359.

  The imaging system of the digital camera system is a solid-state imaging device known as a CMOS sensor or CCD, an AD converter that samples an analog electrical signal converted from optical information by a solid-state imaging device with a sample-and-hold circuit, and converts it into a digital signal, The timing generation device controls the operation timing of the solid-state image sensor and the AD converter, and includes a DA converter that generates an operation reference voltage for the solid-state image sensor and the AD converter. Therefore, the CPU must set and control the operation mode of each device so that an appropriate image can be obtained in parallel with the signal processing.

  However, while the image processing has been speeded up with the improvement of the processing capability of the CPU, the speed of the communication processing such as the operation mode setting is regulated by the communication processing capability of the peripheral device, and the signal that the CPU should originally perform The time required for processing is wasted. Conventionally, with respect to this problem, there is a method of reducing the time load of the CPU accompanying communication by arranging an intermediate communication control unit that performs high-speed communication with the CPU between the CPU and the peripheral device, In Patent Document 1, a proposal is made to perform a connection state investigation on a plurality of peripheral devices without imposing a load on the CPU by the communication bridge function of the intermediate communication control unit. Japanese Patent Application Laid-Open No. 2004-228561 also proposes a communication circuit for converting a communication frequency in a bridge circuit between a system bus having a different operating frequency and a bus for a peripheral device to prevent a performance degradation of the system bus.

  FIG. 14 shows a configuration in which the bridge function of the intermediate control unit is built in the timing generator of FIG. The number 1300 in the drawing means the same functional means as in FIG. 14 in FIG. 14 is obtained by adding a bridge function to the timing generator shown in 1306 in FIG. 13. The signal shown in 1451 is a signal group for setting the operation mode on behalf of the CPU 1307, and is integrated in the imaging system. In order to improve the degree, a configuration in which the bridge function of the intermediate control unit is incorporated in the timing generator is shown.

Japanese Patent Laid-Open No. 9-261278 JP 2003-228549 A

  On the other hand, in an imaging system of a digital camera, a plurality of AD conversion devices may be connected depending on the configuration of the output signal of the solid-state imaging device. In particular, analog image signals are generally output from the solid-state imaging device through a plurality of channels due to the increase in CPU processing speed and the number of pixels in the imaging device. Accordingly, the number of AD converters connected to the analog image signal output is also increasing.

  FIG. 2 is a block diagram illustrating an AD conversion apparatus having an AD conversion unit for one channel divided into an AD conversion unit and an operation mode setting register unit. In FIG. 2, 201 is a one-channel AD converter, 202 is an AD converter, 203 is a register interface and control register, and 204 is a signal group for performing write access to 203. If the number of registers for determining the operation mode of the one-channel AD conversion unit is N, the 203 has N mode setting registers.

  FIG. 4 is a diagram showing one configuration of the imaging unit of the digital camera system. Reference numeral 401 denotes a solid-state imaging device having a 4-channel output configuration for outputting analog image signals to four signal lines indicated by 451, 452, 453, and 454. Reference numerals 402, 403, 404, and 405 denote 1-channel AD converters for converting analog image signals output to the signal lines 451 to 454 into digital image signals, and N registers for setting each operation mode are provided. Have one by one. Reference numeral 407 denotes a CPU that controls the operation of the digital camera system. Regarding the AD converter of the imaging unit, information for setting the operation mode and the like is transferred to the intermediate communication control unit 406 via 465, 466, and 467. Send. The intermediate communication control unit 406 sets communication data from the CPU in the AD converters 402, 403, 404, and 405 via 459, 460, 461, 462, 463, and 464. Here, reference numerals 465, 466, and 467 denote a selection signal, a communication clock, and communication data from the CPU 407 to the intermediate communication control unit 406, respectively. Reference numerals 459 and 460 denote communication clocks and communication data from the intermediate communication control unit 406 to the AD converters 402, 403, 404, and 405, respectively. Reference numerals 461, 462, 463, and 464 are selection signals for the AD converters.

  FIG. 6 is a timing chart showing an operation in which the CPU writes data to the AD converter via the intermediate communication control unit. The numbers in the 400s attached to the waveforms in FIG. 6 correspond to the numbers of the signal lines in FIG. The flow of operation will be described using the timing of FIG. 6 as an example. During the period indicated by 601, the CPU sets the chip select signal 465 to low level (Low) and writes the value of the communication data 467 to the intermediate communication control unit with the communication clock 466. The number of data written at this time is generally equal to or greater than the number of AD converters multiplied by the number of registers N of each AD converter. The intermediate communication control unit holds the transmitted data in a storage area provided for each AD converter.

  FIG. 7 is a diagram showing a configuration of a register included in each intermediate communication control unit. The numbers in the 400 range in FIG. 7 correspond to the numbers in FIG. 701, 702, 703, and 704 in FIG. 7 are storage means for holding data to be communicated to the AD converters 402, 403, 404, and 405, respectively, and each of N pieces required for operation setting of the 1-channel AD converter It has a storage area. Reference numeral 705 in FIG. 7 denotes selection means for selecting one of the outputs of the holding means 701 to 704 and causing the data line 460 to output it.

  Here, returning to FIG. 6, the timing for transferring the data held in the intermediate communication control unit to each 1-channel AD converter will be described. In the periods indicated by 602, 603, 604, and 605 in FIG. 6, the intermediate communication control unit transfers data to the AD converter according to a data transfer instruction from the CPU to the AD converter that is not particularly shown as timing. It is a period. During the period 602, the signal 461 is set to Low, and communication is performed with the one-channel AD converter indicated by 402 in FIG. Similarly, in the period of 603, communication is performed with respect to the AD converter 405 in the period of AD converters 404 and 605 in the period of AD converters 403 and 604. During this communication process, data is set in 4N registers of all AD converters.

An object of the present invention is to improve the degree of freedom of system design by mounting an efficient control unit for a processing unit .

The imaging apparatus of the present invention includes a solid-state imaging device, a first processing unit that processes a signal output from the solid-state imaging device, a second processing unit that processes a signal output from the solid-state imaging device, A first operation mode information for setting an operation mode of the first processing unit, and a control unit for outputting second operation mode information for setting an operation mode of the second processing unit, and The control unit outputs the first and second operation mode information from a common output terminal in response to the input of the first state switching signal, and the second state in response to the input of the second state switching signal. The first and second operation mode information is output from different output terminals .

The camera of the present invention includes the above-described imaging device , a lens for forming an optical image on the imaging device , and a diaphragm for changing the amount of light passing through the lens.

It allows seed s configuration method, it is possible to improve the degree of freedom in system design by implementing an efficient control unit for processing unit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 is a block diagram illustrating an AD conversion unit and an operation mode setting register unit of an AD conversion apparatus having AD conversion units for two channels. In FIG. 3, 301 is a two-channel AD converter, and 302 and 304 are one-channel AD converters each for converting an analog signal into a digital signal. Reference numeral 303 denotes a register interface and control register unit, and reference numeral 305 denotes a signal group for performing write access to the register unit 303. Assuming that the number of registers for determining the operation mode of the one-channel AD conversion unit is N, the register unit 303 has 2N mode setting registers. In the AD converter shown in FIG. 2, it is only necessary to write data into the N registers, but in the AD converter shown in FIG. 3, it is necessary to write data into 2N registers. In order to reduce costs and reduce the mounting area, the AD converter can integrate processing circuits for a plurality of channels into one chip or one package. Thereby, the mounting form of the imaging system can have several variations.

  The AD conversion apparatus 301 includes a plurality of AD conversion units (processing units) 302 and 304 and one common interface for inputting the signal group 305. The interface is one common interface for inputting operation mode information in order to set the operation mode in the register units of the plurality of AD conversion units 302 and 304, respectively. One of the registers of the AD conversion units 302 and 304 is determined by the bank switching information in the operation mode information.

  FIG. 5 is a diagram illustrating the configuration of the imaging unit of the digital camera system according to the embodiment of the present invention. FIG. 5 is different from FIG. 4 in that a 2-channel AD converter is used as an AD converter to reduce the mounting area. Is different.

  In FIG. 5, reference numeral 501 denotes a solid-state imaging device, which has a 4-channel output configuration that converts an optical signal into an electrical signal and outputs an analog image signal to four signal lines indicated by 551, 552, 553, and 554. . Reference numerals 502 and 503 denote the 2-channel AD converter of FIG. 3 for converting the analog image signal output to the signal lines 451 to 454 into a digital signal, and N × 2 registers in which each operation mode is set One by one. 507 is a CPU that controls the operation of the digital camera system. Regarding the AD converter of the imaging unit, information for setting the operation mode, etc. is sent to the intermediate communication control unit of 506 via 565, 566, and 567. Send. 506 sets communication data from the CPU in the AD converters 502 and 503 via 559, 560, 561 and 562. Here, 565, 566, and 567 are a chip select signal, serial communication clock, and serial communication data from the CPU to the intermediate communication control unit, respectively. Reference numerals 559 and 560 denote a serial communication clock and serial communication data from the intermediate communication control unit to the AD converters 502 and 503, respectively. Reference numerals 561 and 562 denote chip select signals for the AD converters 502 and 503, respectively.

  The intermediate communication control unit 506 outputs operation mode information in order to set an operation mode in the AD converters 502 and 503 in response to a request from the CPU 507. After setting the operation mode, the AD converters 302 and 304 each convert a 2-channel analog image signal into a 2-channel digital image signal. The intermediate communication control unit 506 generates the operation timing of the AD converters 502 and 503.

  FIG. 9 is a diagram showing the relationship between the internal register of the intermediate communication control unit in FIG. 5 and the 2-channel AD converter, and unlike the case of FIG. 7, AD conversion corresponding to the registers indicated by 702 and 704 Indicates that the device does not exist.

The communication operation in this configuration will be described with reference to the timing chart of FIG.
FIG. 8 is a timing chart showing an operation in which the CPU writes data to the AD converter via the intermediate communication control unit. The numbers in the 500 range attached to the respective waveforms in FIG. 8 correspond to the numbers of the respective signal lines in FIG. First, during a period indicated by 801, the CPU sets the selection signal 565 to Low and writes the communication data 567 to the intermediate communication control unit with the communication clock 566. The data written at this time is data for N registers, each of which is generally required for setting for one channel of the two-channel AD converters 502 and 503, and is written in the holding means 901 and 903. In the subsequent period 802, N data held in the holding means 901 is written into N registers in the 2-channel AD converter 502. In the subsequent period 803, N data held in the holding means 903 is written into N registers in the 2-channel AD converter 503. In the subsequent period 806, the CPU writes the values to be written to the N registers that have not yet been written out of the 2N registers of the 2-channel AD converters 502 and 503, respectively, into the holding means 902 and 904. In the subsequent period 804 and 805, the intermediate communication control unit writes to the remaining N registers of the AD converters 502 and 503. In the configuration of FIG. 5, a two-channel AD converter can be used to reduce the mounting area.

  Here, when a 2-channel AD converter is used, the holding means for each communication target cannot be used effectively, and communication from the CPU to the intermediate communication control unit is divided twice in the communication process, and communication efficiency Will fall. Hereinafter, an embodiment for solving the problem will be described.

  FIG. 1 is one embodiment of the present invention. 101 is an intermediate communication control unit, 102 and 103 are 2-channel AD converters, 104, 105, 106 and 107 are communication information holding means, and 108 is a selection means for selecting communication information holding means. 158 is a clock signal for data communication with the AD converters 102 and 103, and 159 is a data signal for communicating data stored in the holding means selected by the selection means 108 to the AD converters 102 and 103. is there. Reference numeral 151 denotes a communication target selection signal corresponding to the communication information holding unit 104, which is a signal level in a selected state when data held in the holding unit 104 is transmitted. Reference numeral 152 denotes a communication target selection signal corresponding to the communication information holding unit 105, which is a signal level in a selected state when data held in the holding unit 105 is transmitted. Reference numeral 153 denotes a communication target selection signal corresponding to the communication information holding unit 106, which is a signal level in a selected state when data held in the holding unit 106 is transmitted. Reference numeral 154 denotes a communication target selection signal corresponding to the communication information holding unit 107, which is a signal level in a selected state when data held in the holding unit 107 is transmitted. Reference numeral 155 denotes a switching signal indicating whether the externally connected device is a 1-channel AD converter or a 2-channel AD converter. 156 is a selection signal of the AD conversion apparatus 102, and 157 is a selection signal of the AD conversion apparatus 103. 160, 161, 162 are communication signal lines from the CPU to the intermediate communication control unit 101, 160 is a selection signal of the intermediate communication control unit 101, 161 is a communication clock, and 162 is communication data. The operation of this embodiment will be described with reference to the timing chart of FIG.

  FIG. 10 shows the operation when the 1-channel / 2-channel switching signal 155 is Low. During the period 1001, 4N pieces of data are written in the communication information holding means 104, 105, 106, and 107 by the selection signal 160, the communication clock signal 161, and the communication data 162 from the CPU.

  In the period 1002, the communication information holding means 104 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 151 corresponding to the communication information holding unit 104 becomes Low, which is the selected state. At this time, since the input 151 of the AND circuit 109 is Low, the selection signal 156 for selecting the AD converter 102 becomes Low, and the data held in the communication information holding means 104 is transferred to the AD converter 102.

  In the period 1003, the communication information holding means 105 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 152 corresponding to the communication information holding unit 105 becomes Low which is a selected state. At this time, since the 1-channel / 2-channel switching signal 155 is Low, the output of the OR circuit 111 to which both 152 and 155 are input outputs the value of 152 as it is. The output of the logical sum circuit 111 is connected to the input of the logical product circuit 109. Since the selection signal 152 is low, the selection signal 156 for selecting the AD conversion device 102 becomes low, and the communication information holding means 105 is sent to the AD conversion device 102. The data held in is transferred. Here, the selection signals 156 and 152 become Low at the same time and two signals are selected, but the AD converter is not connected to the selection signal 152.

  In the period 1004, the communication information holding means 106 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 153 corresponding to the communication information holding means 106 becomes Low which is the selected state. At this time, since the selection signal 153 that is the input of the AND circuit 110 is Low, the selection signal 157 for selecting the AD converter 103 becomes Low, and the data held in the communication information holding means 106 is transferred to the AD converter 103. The

  In the period 1005, the communication information holding means 107 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 154 corresponding to the communication information holding means 107 becomes Low which is the selected state. At this time, since the 1-channel / 2-channel switching signal 155 is Low, the output of the OR circuit 112 to which both the signals 154 and 155 are input outputs the value of the signal 154 as it is. The output of the logical sum circuit 112 is connected to the input of the logical product circuit 110. Since the signal 154 is low, the selection signal 157 for selecting the AD conversion device 103 becomes low, and the AD conversion device 103 is connected to the communication information holding means 107. The retained data is transferred. Here, the selection signals 157 and 154 become Low at the same time and two are selected, but the AD converter is not connected to the selection signal 154.

  As described above, the data held in the communication information holding means 104 and 105 is transferred to the 2-channel AD converter 102, and the data held in the data holding means 106 and 107 is transferred to the 2-channel AD converter 103.

  FIG. 11 is a timing chart showing another operation of the embodiment of FIG. 1, and shows an operation when the 1-channel / 2-channel switching signal 155 is at a high level (High). Since this state is a suitable operation timing when four 1-channel AD converters are connected externally, the two AD converters connected to FIG. The operation will be described with reference to the timing charts of FIG. 12 and FIG. 11 in which only the connection to 121, 122, 123, and 124 which are four channel AD converters is changed. The other reference numerals in FIG. 12 are the same as those in FIG. In the period 1101, the same processing as that in the period 1001 in FIG. 10 is performed.

  During the period 1102, the communication information holding means 104 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 151 corresponding to the communication information holding unit 104 becomes Low, which is the selected state. At this time, since the selection signal 151 input to the AND circuit 109 is Low, the selection signal 156 for selecting the AD converter 121 becomes Low, and the data held in the communication information holding means 104 is transferred to the AD converter 121. The

  In the period 1103, the communication information holding means 105 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 152 corresponding to the communication information holding unit 105 becomes Low which is a selected state. At this time, since the 1-channel / 2-channel switching signal 155 is High, the output of the OR circuit 111 to which the signal 155 is input is fixed to High. Although the output of the logical sum circuit 111 is connected to the input of the logical product circuit 109, since its level is High, the value of the selection signal 151 is output to the signal line 156 and is not affected by the selection signal 152. For this reason, data is not transferred to the AD converter 121, and data is transferred only to the AD converter 122.

  In the period 1104, the communication information holding means 106 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 153 corresponding to the communication information holding means 106 becomes Low which is the selected state. At this time, since the selection signal 153 which is the input of the AND circuit 110 is Low, the selection signal 157 for selecting the AD converter 123 becomes Low, and the data held in the communication information holding means 106 is transferred to the AD converter 123. The

  In the period 1105, the communication information holding means 107 is selected, the held data is output to the data line 159, and the communication clock 158 outputs a clock signal. Further, the selection signal 154 corresponding to the communication information holding means 107 becomes Low which is the selected state. At this time, since the 1-channel / 2-channel switching signal 155 is High, the output of the OR circuit 112 to which the signal 155 is input is fixed to High. The output of the logical sum circuit 112 is connected to the input of the logical product circuit 110, but since its level is high, the value of the signal 153 is output to the signal line 157 and is not affected by the signal 154. Therefore, data is not transferred to the AD conversion device 123, and data is transferred only to the AD conversion device 124.

  As described above, the switching signal 155 is set to Low and an internal signal for selecting a slave device (AD converter) is subjected to negative logic OR processing to generate a selection signal. Data of 2N data holding means for 2 sets can be transferred. When the switching signal 155 is set to High, the number of data N for 1 set of data holding means for each channel AD converter Data can be transferred.

  When the intermediate communication control unit 101 outputs the operation mode information of the communication information holding means 104 to 107 to the specific AD conversion apparatus 102, the intermediate communication control unit 101 selects a selection signal corresponding to the specific AD conversion apparatus 102 according to the switching signal 155. Whether or not the selection signal line 152 other than the line 156 is selected is controlled. For example, as shown in FIG. 10, when the switching signal 155 is Low, when the signal is output to the AD converter 102 in the period 1003, the selection signal line 152 other than the selection signal line 156 corresponding to the AD converter 102 is set. Select. As shown in FIG. 11, when the switching signal 155 is High, when the signal is output to the AD converter 122 in the period 1103, the selection signal line 156 other than the selection signal line 152 corresponding to the AD converter 122 is not selected. Put it in a state. The same applies to the period 1005 in FIG. 10 and the period 1105 in FIG.

  In the description of the operation so far, the switching between when the 1-channel AD converter is connected and when the 2-channel AD converter is connected has been shown as a 1-channel / 2-channel switching signal for convenience of explanation. Whether to use a type of AD converter is fixed depending on the specifications of the digital camera system. Therefore, the 1-channel / 2-channel switching can be held in advance in the selection mode holding means, and the held information can be used as the 1-channel / 2-channel switching signal. FIG. 15 shows a configuration in which the switching signal 155 is switched by 108 selection mode holding means. FIG. 16 shows a configuration in which the selection signal modes are independently controlled by having two selection mode holding means 108 and 109.

  In the present embodiment, in the intermediate communication control unit having the communication information holding unit corresponding to each selection signal for communication with a plurality of slave devices, when the data held in the communication information holding unit is transmitted, the communication information By enabling selection signals other than the selection signal corresponding to the holding means to be in the selected state, the number of times of communication from the CPU to the intermediate communication control unit can be reduced, and the communication information holding means of the intermediate communication control unit can be reduced. An unusable area is eliminated, and the communication information holding means can be used efficiently.

  Further, the present embodiment is characterized in that the number M of channels from which the solid-state imaging device outputs analog image signals and the number N of AD converters have a relationship of M ≧ N. The intermediate communication control unit has a plurality of selection signal lines for selecting a plurality of AD converters, and the number L of the selection signal lines and the number N of AD converters are in a relationship of L> N. It is characterized by that.

  According to this embodiment, the selection signal of the slave device is generated as the OR condition of the selection signal for each communication information holding means corresponding to each slave device, so that the case where the one-channel AD converter is connected to the outside and the two channels In both cases when an AD converter is connected, the data held in the communication information holding means for each communication target of the intermediate communication control unit can be transferred without waste, and the number of communications from the CPU to the communication information holding means is minimized. It becomes possible.

  In the description of the embodiment, a case where a 1-channel AD converter and a 2-channel AD converter are connected has been described. However, a larger number of internal components can be obtained even when more AD converters and N-channel AD converters are connected. It is possible to obtain the same effect with an easy configuration that simply performs the OR condition processing of the selection signal. Further, although the case where the AD conversion apparatus is connected has been described in the present embodiment, it is obvious that the present embodiment is also effective when other slave apparatuses are connected.

  Based on FIG. 17, an example when the above-described imaging unit is applied to a still video camera will be described in detail. FIG. 17 is a block diagram illustrating a configuration example of a still video camera. The solid-state imaging device 4 corresponds to the solid-state imaging device 501 in FIG. 5, the A / D converter 6 corresponds to the AD converters 502 and 503 in FIG. 5, and the timing generator 8 corresponds to the intermediate communication control unit 506 in FIG. Correspondingly, the overall control / calculation unit 9 corresponds to the CPU 507 of FIG.

  In FIG. 17, 1 is a barrier that serves as a lens switch and a main switch, 2 is a lens that forms an optical image of a subject on the solid-state image sensor 4, 3 is an aperture for changing the amount of light that has passed through the lens 2, and 4 is A solid-state imaging device for capturing the subject imaged by the lens 2 as an image signal, 5 an imaging signal processing circuit that performs analog signal processing on an imaging signal (image signal) output from the solid-state imaging device 4, and 6 an imaging signal processing An A / D converter that performs analog-digital conversion of the image signal output from the circuit 5, a signal processing unit 7 that performs various corrections on the image data output from the A / D converter 6 and compresses the data; 8 is a solid-state imaging device 4, imaging signal processing circuit 5, A / D converter 6, and timing generator for outputting various timing signals to the signal processor 7, and 9 is overall control for controlling various operations and the entire still video camera. Arithmetic unit, 10 is a memory unit for temporarily storing image data, 11 is an interface unit for recording or reading on recording medium 12, 12 is a semiconductor memory for recording or reading image data, etc. A detachable recording medium 13 is an interface unit for communicating with an external computer or the like.

  Next, the operation of the still video camera at the time of shooting in the above configuration will be described. When the barrier 1 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the aperture 3, and the signal output from the solid-state image sensor 4 is converted by the A / D converter 6 via the image signal processing circuit 5. After that, the signal is input to the signal processing unit 7. Based on the data, the exposure calculation is performed by the overall control / calculation unit 9. The brightness is determined based on the result of this photometry, and the overall control / calculation unit 9 controls the aperture according to the result.

  Next, based on the signal output from the solid-state imaging device 4, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement. Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is A / D converted by the A / D converter 6 via the imaging signal processing circuit 5 and passes through the signal processing unit 7 by the overall control / calculation unit 9. It is written in the memory part. Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit 11 under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 13.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

FIG. 5 is a diagram illustrating the characteristics of the embodiment of the present invention, and a case where a two-channel AD converter is connected. It is a figure which shows the relationship between the AD conversion part of a 1-channel AD converter, and the operation setting register part. It is a figure which shows the relationship between the AD conversion part of a 2 channel AD converter, and the operation setting register part. It is a figure of the digital camera system which connected 1 channel AD converter. It is a figure of the digital camera system which connected 2 channel AD converter. FIG. 5 is a timing chart showing a register setting operation in FIG. 4. FIG. 5 is a diagram showing a relationship between a communication information holding unit and a 1-channel AD converter that the intermediate communication control unit of FIG. 4 has. FIG. 6 is a timing chart showing a register setting operation in FIG. 5. It is a figure which shows the relationship between the communication information holding means and 2 channel AD converter which the intermediate communication control unit of FIG. 5 has. FIG. 2 is a timing chart for explaining the operation of FIG. 1. FIG. 13 is a timing chart for explaining the operation of FIG. 12. FIG. 3 is a diagram illustrating the characteristics of an embodiment of the present invention, in which a 1-channel AD converter is connected. It is a figure which shows the prior art example which CPU sets a mode to the apparatus of an imaging system. It is a figure which shows the prior art example which a timing generator bridges the mode setting with respect to the imaging system from CPU, and performs mode setting to each apparatus of an imaging system. It is a figure which shows embodiment of the structure which changes collectively the control method of a selection signal by a selection mode holding means. It is a figure which shows embodiment of the structure which changes the control method of a selection signal independently by a selection mode holding means. It is a block diagram which shows the structural example of a still video camera.

Explanation of symbols

101 Intermediate communication controller
102, 103 2-channel AD converter
104, 105, 106, 107 Communication information holding means
108 Communication information holding means selection means
151 Selection signal corresponding to holding means 104
152 Selection signal corresponding to holding means 105
153 Selection signal corresponding to holding means 106
154 Selection signal corresponding to holding means 107
155 1 channel AD / 2 channel AD switching signal
156, 157 Communication selection signal to 2-channel AD
109 AND circuit for generating selection signal 156
111 OR circuit for masking selection signal 152
110 AND circuit for generating selection signal 157
112 OR circuit for masking selection signal 154

Claims (10)

A solid-state image sensor;
A first processing unit for processing a signal output from the solid-state imaging device;
A second processing unit for processing a signal output from the solid-state imaging device;
A control unit that outputs first operation mode information that sets an operation mode of the first processing unit and second operation mode information that sets an operation mode of the second processing unit;
The control unit outputs the first and second operation mode information from a common output terminal according to the input of the switching signal in the first state, and according to the input of the switching signal in the second state, An image pickup apparatus that outputs the first and second operation mode information from different output terminals . The imaging apparatus according to claim 1, further comprising a central processing unit that supplies the switching signal to the control unit. The imaging apparatus according to claim 1, wherein the control unit includes a first register unit that holds the first and second operation mode information. The imaging according to any one of claims 1 to 3, wherein the first and second processing units are AD converters that convert a signal output from the solid-state imaging device into a digital signal. apparatus. 5. The image pickup apparatus according to claim 4 , wherein the number M of channels through which the solid-state image pickup device outputs an analog image signal and the number N of the AD converters have a relationship of M ≧ N. The control unit includes a plurality of selection signal lines for selecting at least the first and second processing units , respectively, and the number L of the selection signal lines and the number N of the AD conversion devices satisfy L> N. imaging device according to claim 4 or 5, wherein the der relationship Ru. The control unit has a plurality of selection signal lines for selecting the first and second processing units , respectively.
Said first and second processor interfaces, in addition to the signal and the first and second operation mode information of the selected signal lines, according to claim 1, characterized in that inputting the clock from the control unit The imaging device according to any one of 6 . The imaging device according to claim 4, wherein the control unit generates operation timings of the solid-state imaging device and the AD converter. Wherein the control unit, imaging according to any one of claims 1-8, characterized by outputting said first and second operation mode information in a time series to the first and second processing unit apparatus. An imaging device according to claim 1;
A lens for forming an optical image on the imaging device ;
And a diaphragm for varying the amount of light passing through the lens.

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