JPH07298124A - Video camera - Google Patents

Abstract

PURPOSE:To transfer object data of a prescribed quantity with a few line number for the data communication between a logic arithmetic section and a signal processing section in the video camera digitizing a video signal from an image pickup element and applying arithmetic processing to the signal. CONSTITUTION:After a video signal from an image pickup element 2 is converted into a digital signal by an A/D converter 3, the signal is processed by a signal processing section 4 to generate a video signal and a D/A converter 7 converts the signal into an analog signal, which is outputted. Furthermore, an interface section 5 between a data register in the signal processing section 4 and a microcomputer 6 being a logic arithmetic section is provided with plural control registers, an address discrimination device 57 discriminating the address from the microcomputer 6, and a switch 56 selecting an output to the signal processing section 4 depending on the result of discrimination. When an address transmission destination of data fed from the microcomputer 6 is an address of a data register in which the data cannot be written within a valid video period, the data are transferred to the signal processing section 4 for a blanking period via the control register and when the destination is an address in which the data are written within a valid video period, the data are transferred directly from the microcomputer 6 to the signal processing section 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera which digitizes a video signal from an image pickup device and performs arithmetic processing.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional video camera which digitizes a video signal and performs arithmetic processing. Further, FIGS. 4 and 5 are timing charts showing a communication state between a logic operation unit including a microcomputer and the interface unit, and FIG. 6 shows a timing when data is written from the interface unit to the signal processing unit. In the figure, data communication is performed between the logical operation unit and the signal processing unit through an interface unit.

In FIG. 3, reference numeral 1 is an image pickup lens, 2 is an image pickup element for photoelectrically converting a subject image (image pickup light) projected by the lens 1 into an electric signal, and 3 is a digital analog image signal from the image pickup element 2. A / D converter that converts to a signal,
Reference numeral 4 is a signal processing unit that processes an A / D-converted digital signal to generate a video signal, 5 is an interface unit that reads or writes data from a data register inside the signal processing unit 4, and 6 is an interface unit A microcomputer (hereinafter, referred to as a microcomputer), which is a logical operation unit that receives the data read by 5 or sends the write data to the interface unit 5, processes a digital signal of a plurality of bits as one word data. Reference numeral 7 is a D / A converter that converts a digital signal-processed video signal into an analog signal.

In the signal processing unit 4, 411-41
n is n write registers (data registers) for writing data from the microcomputer 6, and 421 to 42n are n read registers (data registers) for storing each data inside the signal processing unit 4 and sending to the microcomputer 6. 43 is a status register that holds the state of whether or not data is stored in each of the read registers 421 to 42n, and 44 is each of the read registers 421 to 42n.
Is an OR circuit that obtains an interrupt signal from the load signal, 45 is a data selector, and 46 is a timing generator that outputs a load signal to each of the read registers 421 to 42n at a predetermined timing.

Further, in the interface section 5, 5
11 to 514 are control registers for storing addresses, 521 to
Reference numeral 524 is a data storage control register, 53 is a decoder for setting an address of a register to which data is to be transferred by the output of the address storage control register 514, and sending a transfer clock signal to the register, and 54 is an address storage control. A counter that counts the number of words stored in the registers 511 to 514 and the data storage control registers 521 to 524, and a clock generator 55 that generates a serial clock for data transfer to the microcomputer 6.

Each of the above registers is composed of a shift register which can serially input or output data by a clock input.

In the above structure, the subject image projected by the lens 1 is converted into an electric signal by the image pickup device 2, converted into a digital signal by the A / D converter 3, and then inputted to the signal processing section 4. .

The signal processing unit 4 receives the data required in the process of processing the input digital signal from the microcomputer 6 via the interface unit 5, and the microcomputer 6 receives the data necessary for calculating this data. It is received from the signal processing unit 4 via the interface unit 5.

FIG. 4 shows a microcomputer 6 and an interface section 5.
3 shows the timing of serial communication with the data line, and the communication during this time is the clock line (CLK), the write data line (DW), and the read data line (D) in FIG.
R), and a line (MOD) for selecting data read / data write / addressing mode (MODE).
Through E).

As shown in FIG. 4A, when mode information for addressing is transmitted from the microcomputer 6 to the interface section 5 through the MODE line, the interface section 5 sends a clock signal to the microcomputer 6 through the CLK line. The microcomputer 6 sends an address signal through the DW line in synchronization with this clock signal.

The interface unit 5 receives the address signal and sets the address in the internal address register. Thereafter, for example, when the mode information for data writing is transmitted from the microcomputer 6 through the MODE line, the interface unit 5 similarly sends a clock signal to the microcomputer 6 through the CLK line as shown in B of FIG. In the microcomputer 6, the DW is synchronized with this clock signal.
A write data signal is sent through the line, and the interface unit 5 receives the write data.

Further, in the interface section 5, the write data Da ₀ to ... fetched from the microcomputer 6 in the above process.
Da ₇ and its write destination addresses Aa _{0 to} Aa ₇ are temporarily transferred and stored in the data storage control register 521 and the address storage control register 511 of FIG. 3 at the timings shown in FIG.

Each of the above control registers is composed of a serial input / parallel output shift register, like the write register in the signal processing section 4, and, for example, when a data write command is further issued from the microcomputer 6 in this state. , Its data Da _{0 to} Da ₇ and addresses Aa _{0 to} A
a ₇ is similarly transferred to the respective control registers 521 and 511, and at the same time, the data and address stored in the control registers 521 and 511 until now are stored in the next control register 52.
2, 512, respectively, and transferred. These data transfers are performed by ADR-CLK and DATA- shown in FIG.
It is performed at the timing shown in FIG. 5 by the clock of CLK.

In the above process, the write data and the transfer destination address sent from the microcomputer 6 are the control registers 521 to 524, 5 during the effective video period of the video signal.
Only the data is stored in 11 to 514, and data transfer to the target signal processing unit 4 is not performed. Further, when the interface unit 5 obtains the information of the blanking period of the video signal from the HBLK input, the address storage control register 51
The transfer destination address is determined based on the address information 1 to 514, and only for this, the clock lines WCLK1 to
To send a clock signal for transfer through. Then, in synchronization with this clock signal, the data storage control register 52
The data of 1 to 524 are transferred to the write registers 411 to 41n of the transfer destination through the WR line.

Next, the above-mentioned data communication process will be described in detail with reference to FIG. The decoder 53 shown in FIG. 3 fetches address information from the parallel output of the control register 514 and sets the address at the timing shown in the address setting of FIG. 6 in the above process. Further, the decoder 53 has the write registers 411 to 41n for the set addresses.
Only for WCLK, a clock for communication is selected by selecting one of the clock lines WCLK1 to WCLK.
Output at the timings 1 to n. At the same time, a clock is sent to the control registers 521 to 524 at the timing shown by DATA-CLK in FIG.
Performs the parallel output shown in FIG. 6 in synchronization with this clock.

By these clock and data outputs, the data Da _{0 to} Da ₇ and Db _{0 to} Db ₇ are taken into the write registers of the respective addresses Aa _{0 to} Aa ₇ and Ab _{0 to} Ab ₇ .

In this case, since the data and the address sent from the microcomputer 6 are 2 words each within the effective video period, the control register 51 shown in FIG.
Addresses and data are stored in 511, 512 and 521, 522 of 1 to 514, 521 to 524, respectively, and the control registers of the remaining 513, 514 and 523, 524 are empty. Therefore, FIG.
At the data transfer timing shown in (1), "0" is output for both data and address at the transfer timing for the first two words.

Here, in the circuit of FIG. 3, the control register has four words for data storage and four words for address storage, but the microcomputer 6 issues five or more data write commands during the effective video period. 5, when the counter 54 gives the number of transfers between the control registers from the microcomputer 6 within the effective video period to ADRCLK.
It counts with a signal, and when this count becomes 4 or more, an inhibit command is given to the clock generator 55 of FIG.

The clock generator 55 does not output a clock for communication even if the microcomputer 6 sends a command for writing or addressing to the interface unit 5 in accordance with the above-mentioned prohibition command. At this time, the microcomputer 6 controls the control registers 511 to 514 and 521 to 521 in the next blanking period.
It is in a standby state until the data and address of 524 are transferred to the signal processing unit 4.

Further, in the signal processing section 4 of FIG.
When a load signal is sent from the timing generator 46 to any of the read registers 421 to 42n, the read register loads predetermined data, and the load signal becomes an interrupt signal of the microcomputer 6 through the OR circuit 44, and further, The bit of the status register 43 corresponding to the read register rises. This bit is held until the data loaded in that read register is read.

The load signal passed through the OR circuit 44 is
The microcomputer 6 is interrupted, and at this time, the microcomputer 6 starts communication for obtaining information on which read register is loaded. At this time, in order to first set the address of the status register 43, the status register address is sent to the interface unit 5 through the DW line at the timing shown in A of FIG. After that, the microcomputer 6 modifies the interface unit 5 as shown in C of FIG.
When the information of the data read mode is sent through the line and the interface unit 5 receives the information of this mode, the data selector 4 is sent based on the previously sent address.
5 is set so that the output of the status register 43 can be obtained, and a clock is sent to the status register 43 only through the clock lines RCLK1 to RCLK of FIG. 3, and the status register 43 synchronizes the data with the DW line. Through the interface unit 5. When the interface section 5 receives this data, it sends a clock signal to the microcomputer 6 through the CLK line at the timing shown in C of FIG.
The data obtained from the status register 43 is sent through the R line.

The microcomputer 6 uses the status register 4 described above.
When the data of 3 is received, it is determined which read register of the signal processing unit 4 is loaded by the data,
The address of the register is sent to the interface unit 5 in accordance with the timing shown in FIG. 4A, and the internal address of the interface unit 5 is set. After that, the microcomputer 6
From the MODE line to the interface section 5, data read information is sent, and the interface section 5 uses the data selector 45 based on the previously set address.
Is set, and the clock signal is sent through the clock lines RCLK1 to RCLK only to the read register based on the address. Data is output from the read register in synchronization with the clock and transferred to the interface unit 5. The interface section 5 sends the data through the RD line in synchronization with the clock signal on the CLK line at the timing shown in C of FIG.

[0023]

However, in the conventional video camera that performs the above-mentioned data communication, the amount of data that can be communicated within one horizontal synchronization period of the video signal, that is, the data for one line. Is limited by the number of control registers in the interface, regardless of the processing speed of the microcomputer.

Therefore, for example, in an autofocus system of a camera, not only a register for setting an area for capturing a focus signal in a video screen or an autofocus system, but also a system for white balance, automatic exposure correction, etc. In the register for area setting existing in 1), when one area is completed in one screen and the data for the next area setting is transferred from the microcomputer in the same screen, a lot of data is recorded in one line. There is a case where the transfer of a certain amount of data is forced, and the data cannot be stored in the control register and is carried over to the next line.

Normally, when setting a plurality of areas in one screen, the above-mentioned area settings are as short as possible between the end of one area and the start of the next area, that is, a small number of lines. desirable. However, if the number of control registers is limited, a large number of lines are required for data transfer, and it may not be possible to set the desired area.

In order to avoid this, for example, the number of control registers may be increased, but in this case, the amount of hardware increases. Further, there is a limit to the retrace line period during which transfer from the control register to the write register of the signal processing unit is limited, and depending on the clock rate, too many control registers may not be provided in the system.

The present invention has been made in view of the above problems, and a video camera that can transfer a predetermined amount of data for a small number of lines and requires a small number of control registers. Is intended to provide.

[0028]

A video camera according to the present invention includes a signal processing unit for processing a video signal photoelectrically converted by an image pickup device and further digitized to generate a video signal, and a data register in the signal processing unit. And a logical operation unit for performing data communication through the interface unit,
The interface unit includes a plurality of registers for holding addresses and data, an address discriminating unit for discriminating an address value to be transferred to the signal processing unit according to a predetermined condition, and the output of the control register or the output according to the discrimination result. And a switch means for selecting whether to output from the logical operation unit, the transfer data and the transfer destination address are stored in the control register according to the transfer destination address of the data, and the control register stores the transfer data and the transfer destination address during the blanking period of the video signal. It is configured to switch between transfer to the signal processing unit or transfer of transfer data and transfer destination address directly from the logical operation unit to the signal processing unit.

[0029]

According to the present invention, the discriminating means for discriminating whether the address of the register which may be written within the address valid video period sent from the logical operation unit or the address of the register which is not, and the discrimination result of this discriminating means are used. The interface section is provided with a switch means for switching the data sent from the logic operation section and the output of the data of the control register and sending it to the write address in the signal processing section, and the address sent from the logic operation section can be written within the effective video period. If it is the address of a register that does not exist, that data is transferred to the signal processing unit via the control register during the blanking period, and if it is the address of a register that is writable during the effective video period, that data is transferred directly to the signal processing unit. Causes the logical operation unit to transfer an amount of data that exceeds the storage capacity of the control register during one line. In this case, if it is data in a register that can be written during the effective video period, it can be transferred directly to the signal processing unit without going through the control register, and the desired amount of data can be transferred during a small number of lines. it can.

[0030]

1 is a block diagram showing a circuit configuration of a video camera according to an embodiment of the present invention. In the figure, 1-7
In the signal processing unit 4, 511 to 514, 521 to 524 in the interface unit 5.
Since each of the elements 53 to 55 is the same as that of the circuit shown in FIG. 3, the description thereof will be omitted.

Reference numeral 56 is a switch (means) for switching the data line for the write register inside the signal processing unit 4 between the data line from the microcomputer 6 and the output line of the control register, and 57 is transferred from the microcomputer 6 to the signal processing unit 4. An address discriminator (discriminating means) for discriminating the address value sent for that purpose according to a predetermined condition discriminates whether or not the address value can be transferred to the signal processing unit 4 during the effective video period. The switch 56 is provided to select the output of the control register or the output of the microcomputer 6 according to the result of the determination by the address discriminator 57.

Further, the transfer data and the transfer destination address are stored in the control register according to the transfer destination address of the above-mentioned data and transferred from the control register to the signal processing unit 4 during the blanking period of the video signal, or directly. It is configured to switch whether to transfer the transfer data and the transfer destination address from the microcomputer 6 to the signal processing unit 4.

FIG. 2 shows the communication between the microcomputer 6 and the interface unit 5 and the interface unit 5 and the signal processing unit 4 when the address value sent from the microcomputer 6 can be transferred to the signal processing unit 4 during the effective video period. It is a figure which shows a timing.

Although there are some registers in the write address group in the signal processing unit 4 which should not be written within the valid video period, registers which may be written within the valid video period, that is, data is rewritten during the valid video period. There is also a register in which transfer noise does not affect the video signal. For example, the register group for setting each area described above is only for giving a setting value of a circuit that gates a signal input necessary for an autofocus system or the like, and one area ends and the next area starts. Up to the above, even if the data is rewritten during the effective video period, it does not directly affect the video signal.

Therefore, in this embodiment, the address discriminator 57 is used.
Is provided to determine whether the transfer destination address value from the microcomputer 6 can be transferred to the signal processing unit 4 during the effective video period, the switch 56 is switched according to the determination result, and the transfer data is transferred to the control register in the interface unit 5. The transfer destination address is stored and it is possible to select whether to transfer from the control register to the signal processing unit 4 or directly from the microcomputer 6 to the signal processing unit 4 during the blanking period of the video signal.

That is, when the mode information for addressing is transmitted from the microcomputer 6 to the interface unit 5 shown in FIG. 1 through the MODE line, the interface unit 5 sends a clock signal to the microcomputer 6 through the CLK line. The microcomputer 6 sends an address signal through the DW line in synchronization with this clock.

When the interface section 5 receives the above address signal, it sets an address in the internal address register. Then, the address discriminator 57 discriminates whether or not the address value set in the address register can be transferred to the signal processing unit 4 within the effective video period, and if the address is not transferable, it is similar to the circuit of FIG. The address value and the data next sent from the microcomputer 6 are transferred to the address storage control register 511 and the data storage control register 521, respectively. This data is transferred to the target write register inside the signal processing unit 4 in the next blanking period.

On the other hand, when the address discriminator 57 determines that the address value sent from the microcomputer 6 can be transferred to the signal processor 4 within the valid video period, the address discriminator 57 outputs a control signal. The switch 56 is switched from the control register output side to the data output side of the microcomputer 6, and the decoder 53 is controlled to give priority to serial input from the microcomputer 6 for address setting.

FIG. 2 shows the timing of the above process. When an addressing command is sent from the microcomputer 6 to the interface section 5 through the MODE line, the clock generator 55 outputs the clock signal CLK shown in the figure. Then, the microcomputer 6 synchronizes with the signal and outputs Aa ₀ to Aa ₇
The address signal shown in is sent to the interface section 5 through the DW line. Then, the address discriminator 57 inside the interface unit 5 determines that this address value Aa can be directly transferred to the signal processing unit 4, and sets this address value Aa in the decoder 53 at the timing shown in the figure. After that, when the microcomputer 6 sends a data write command to the interface unit 5, the clock generator 55 sends the clock signal of CLK to the microcomputer 6 through the CLK line, and the microcomputer 6 synchronizes with this and outputs the data of Da ₀ to Da ₇ . The signal is sent to the interface section 5 through the DW line.

Here, the switch 56 is switched to the data output side of the microcomputer 6 according to the discrimination result of the address discriminator 57, and the data signal Da from the microcomputer 6 is outputted.
_{0 to} Da ₇ are directly sent to the respective serial input ports of the write registers 411 to 41n inside the signal processing unit 4 through the WD line. Based on the previously set address value Ab, the decoder 53 passes through the clock lines CLK1 to n only to the write register of this address.
The clocks of CLK1 to n shown in are sent to the signal processing unit 4.
Then, the data Da is written in the selected write register inside the signal processing unit 4 at the timing shown in FIG.

After that, when the address signals Ab _{0 to} Ab ₇ are further sent from the microcomputer 6 by the address designation shown in FIG. 2, if the address value Ab is an address value that can be transferred to the signal processing unit 4 during the effective video period. For example, the address setting is performed in the same manner, and the data signal D sent from the microcomputer 6 next.
b _{0 to} Db ₇ are transferred to the write register of the address value, and the data value Db is written.

In the above transfer process, when the address discriminator 57 determines that the current address value can be transferred to the signal processor 4 during the valid video period, the clock generator 5
A signal for stopping the signal output of ADR-CLK and DATA-CLK is sent to 5. As a result, the clock generator 55 causes the control registers 511 to 514 and 521 to 52.
The output of the clock to 4 is stopped. Therefore, the counter 54 counting the number of words stored in the control register does not increase the count value.

In this way, if the address value sent from the microcomputer 6 is the address of a register that cannot be written within the valid video period, the data is transferred to the signal processing section 4 via the control register in the blanking period, If the address of the register is writable within the valid video period, the data is directly transferred to the signal processing unit 4, and the microcomputer 6
Is trying to transfer an amount of data that exceeds the storage capacity of the control register during one line, and if it is the address of a register that can be written during the effective video period, direct signal processing is performed without going through the control register. The data can be transferred to the unit 4 and a desired amount of data can be transferred during a small number of lines, and the number of control registers can be reduced.

[0044]

As described above, according to the present invention,
A plurality of registers, an address discriminating means for discriminating an address value from the logical operation unit, and an output of the control register or a logical operation are provided in an interface unit between the logical operation unit and the signal processing unit such as a microcomputer. A switch for selecting whether to output from the logic operation unit is provided, and data is transferred to the signal processing unit through the control register or directly from the logic operation unit to the signal processing unit according to the transfer destination address of the data from the logic operation unit. Since it is possible to select whether or not to carry out, it is possible to transfer a target predetermined amount of data during a small number of lines, and there is an effect that the number of control registers can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a communication timing of the circuit of FIG.

FIG. 3 is a block diagram showing a circuit configuration of a conventional example.

FIG. 4 is a diagram showing a communication timing of the circuit of FIG.

5 is a diagram showing a communication timing of the circuit of FIG.

6 is a diagram showing a communication timing of the circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 lens 2 image sensor 3 A / D converter 4 signal processing section 5 interface section 6 microcomputer (logical operation section) 7 D / A converter 56 switch (switch means) 57 address discriminator (address discriminating means) 411 to 41n Write register (data register) 421 to 42n Read register (data register) 511 to 514 Address storage control register 521 to 524 Data storage control register

Claims (1)

[Claims] 1. A signal processing unit for processing a video signal photoelectrically converted by an image pickup device and further digitized to generate a video signal, and a logical operation unit for performing data communication through a data register and an interface unit in the signal processing unit. The interface unit includes a plurality of registers for holding addresses and data, an address discriminating unit for discriminating an address value to be transferred to the signal processing unit according to a predetermined condition, and the control register according to the discrimination result. Switch means for selecting whether to output the output of the logical operation unit or the output of the logical operation unit. Transfer from the control register to the signal processing unit, or directly from the logical operation unit to transfer data and transfer destination add A video camera, characterized in that it is configured to switch whether or not to transfer the response to the signal processing unit.