JPH08278938A - Dma device - Google Patents

Abstract

PURPOSE: To prevent DMA processings by a CPU from being concentrated in some specific time and to lighten the load on the CPU. CONSTITUTION: A DREQ signal is inputted, a priority decision circuit 1 selects a DMA channel, and an address selector 8 selects an address and outputs it to a memory. A RAM control signal is generated by a timing control circuit 3 and DMA is controlled thorugh a control register 2. Automatic memory address counters 4 and 5 and automatic transfer quantity counters 6 and 7 set a next memory head address and a data transfer quantity during DMA transfer. After the DMA transfer ends, a load signal is sent from a control register 2 to the automatic memory address counters and automatic transfer quantity counters and the memory head address and data transfer quantity which are set during the DMA transfer are loaded to internal counters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA device for transferring data between a memory and an input / output device by using an arbitrary number of data as one transfer block.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional 2-channel DMA.
1 shows a block diagram of the device.

In FIG. 3, reference numeral 1 is a priority determination circuit,
The priority of the DREQ (DMA Request) signal of each channel is determined, and the DACK (DMA Acknowledge) is determined.
dge) signal is output.

Reference numeral 32 is a control register, CP
U controls the DMA via this register. Also,
Status information such as DMA termination is also read through this register.

A timing control circuit 3 includes memory control signals CE (Chip Enable) and OE (Out).
put Enable), WE (Write Enable)
le) is generated.

Reference numerals 34 and 35 are memory address counters. When the memory start address is set before the start of the DMA transfer, the counter value is sequentially incremented each time the DMA transfer is executed once.

Reference numerals 36 and 37 are transfer number counters, and DM
If the number of data transfers is set before the start of the A transfer, the value of the counter is sequentially decremented each time the DMA transfer is executed once. When the transfer for the set transfer number is completed, the value of the transfer number counter becomes 0, and the DMA end signal is sent to the control register 2.

An address selector 8 selects the address of each channel and outputs it to the memory.

The CPU sets the memory start address and the number of data transfers before starting the DMA transfer of each channel,
To start. Then, when the DREQ signal is input, DMA transfer is started according to the priority order, and transfer is performed for the set number of transfers.

[0010]

Generally, in a DMA device, the memory start address and the number of data transfers are set before starting the DMA transfer. It is necessary to set the memory start address and the number of data transfers every time one block of DMA transfer is completed, and these settings cannot be made during the DMA transfer.

However, a CLV, such as a CD-ROM player, etc.
Since the data is continuously reproduced in the optical disc apparatus of the method, the DMA transfer is stopped only while the frame synchronization signal is being output, and the setting must be completed during this period. Moreover, the output time of the frame synchronization signal becomes shorter when the rotation speed is increased in order to increase the transfer speed.
There is a problem that the setting becomes difficult and, as a result, the transfer speed cannot be set too high.

An object of the present invention is to provide a DMA device capable of preventing DMA settings from being concentrated at a specific time and reducing the load on the CPU.

[0013]

In order to solve the above problems, the DMA device of the present invention employs the following technical means.

A memory means for storing the memory start address and the data transfer number is provided, and the next memory start address and the data transfer number are stored from the CPU during the DMA transfer. The address and the number of data transfers are set in the DMA counter.

Further, a transfer number memory in which the data transfer number is written in advance is provided, and after the preceding DMA transfer is completed, the data transfer number written in the transfer number memory is set to the transfer number. Set in the counter.

Further, a memory means for separately storing the upper and lower addresses of the memory start address of the transfer block is provided, and after the DMA transfer executed in advance is completed, the memory start address stored in the memory means is stored. Set the address in the memory address counter.

Furthermore, a plurality of storage means for storing the memory start address of the transfer block and a selector for selecting the output of the storage means are provided, and the DMA executed in advance.
After the transfer is completed, one of the memory head addresses stored in the storage means is selected and set in the memory address counter.

Further, a plurality of storage means for storing the memory start address of the transfer block, a selector for selecting the output of the storage means, a counter for sequentially incrementing each time the DMA transfer of one block is completed, and a counter. Is provided with a decoder for decoding the output of the memory to output a selection signal for selecting the selector, and after completion of the preceding DMA transfer, the memory start address stored in the plurality of storage means is stored in the memory address counter. Set in order.

[0019]

In the DMA device of the present invention, the next memory start address and the number of data transfers can be set during DMA transfer.
It is possible to prevent the DMA processing of the CPU from concentrating on a certain specific time and further reduce the load on the CPU.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the DMA device of the present invention is applied to a CD-ROM reproducing device will be described below with reference to the drawings. 1 is a block diagram showing a DMA device according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing the automatic memory address counter and the automatic transfer number counter of FIG.

In FIG. 1, 1 is a priority determination circuit,
The priority of the DREQ signal of each channel is determined and the DACK signal is output.

Reference numeral 2 is a control register, which is a CPU
Controls the DMA via this register. Also, D
Status information such as MA completion is read through this register. Then, from the automatic transfer number counters 6 and 7, DMA
When the end signal is sent, the load signal is returned.

A timing control circuit 3 generates memory control signals CE, OE, WE.

Numerals 4 and 5 are automatic memory address counters, and the CPU can set the memory address at any time during the DMA transfer. When the DMA transfer is completed, a load signal is sent from the control register 2, so D
The memory address set during MA transfer is loaded into the internal address counter. Then, the value of the counter is sequentially added every time the DMA transfer is executed once.

Reference numerals 6 and 7 are automatic transfer number counters, and CP
U can set the transfer number at any time during the DMA transfer. When the DMA transfer is completed, a load signal is sent from the control register 2, so the number of transfers set during the DMA transfer is loaded into the internal transfer number counter. Then, each time the DMA transfer is executed, the value of the counter is sequentially subtracted. When the transfer for the set transfer number is completed, the value of the transfer number counter becomes 0, and the DMA end signal is sent to the control register 2.

An address selector 8 selects an address of each channel and outputs it to the memory.

Hereinafter, automatic memory address counters 4 and 5
The details of the automatic transfer number counters 6 and 7 are shown in FIG.
Will be explained.

Reference numeral 21 is a memory address register, which is C
The PU writes the next memory start address during the DMA transfer.

Reference numeral 22 denotes a memory address counter, which loads the address written in the memory address register 21 by a load signal sent from the control register 2. Then, the value of the counter is sequentially added every time the DMA transfer is executed once.

Reference numeral 23 is a transfer number register, and the CPU is D
Write the next transfer count during MA transfer.

A transfer number counter 24 loads the transfer number written in the transfer number register 23 by a load signal sent from the control register 2. Then, each time the DMA transfer is executed, the value of the counter is sequentially subtracted. When the transfer for the set transfer number is completed, the value of the transfer number counter becomes 0, and the DMA end signal is sent to the control register 2.

In the first embodiment of the present invention having the above configuration, the CPU can write the next memory start address and the number of data transfers at any time during the DMA transfer, and the values are automatically set at the end of the DMA transfer. The internal memory address counter 22 and the transfer number counter 24 are set. As a result, it is possible to prevent the DMA processing of the CPU from concentrating on a certain specific time. Further, if the data transfer number of the next DMA transfer is the same as the previous data transfer number, it is not necessary to write the data transfer number again, and the load on the CPU can be reduced.

FIG. 4 shows an automatic transfer number counter of the second embodiment.

Reference numeral 41 is a transfer number memory in which the data transfer number is stored in advance.

A transfer number counter 42 loads the transfer number from the transfer number memory 41 in response to a load signal sent from the control register 2.

In the second embodiment of the present invention having the above-mentioned configuration, the transfer number is automatically set in the transfer number counter 42 at the end of the DMA transfer, so that the DMA channel in which the data transfer number is the same each time is set. If applied, it is not necessary to set the number of data transfers, and the load on the CPU can be reduced.

FIG. 5 shows an automatic memory address counter of the third embodiment.

Reference numeral 51 is a memory address register, which is D
The CPU writes the upper address of the next memory start address during MA transfer execution.

Reference numeral 52 is a lower address memory, which is a DMA.
Lower addresses are stored in advance.

Reference numeral 53 is a memory address counter, which receives a load signal sent from the control register 2 to send the memory address register 51 and the address memory 52.
Load the address from.

In the third embodiment of the present invention having the above-mentioned structure, the upper address of the next memory start address can be written during the DMA transfer, and the lower address is stored in advance. Those values are automatically set in the internal memory address counter 53. D
If it is applied to the DMA channel in which the MA lower address is the same every time, it is not necessary to set the DMA lower address, and the burden on the CPU can be reduced.

FIG. 6 shows an automatic memory address counter of the fourth embodiment.

Reference numerals 61, 62 and 63 are memory address registers, and the CPU writes the memory start address in each register.

Reference numeral 64 is an address selector which selects and outputs the output of the memory address register by the address select signal.

Reference numeral 65 is a memory address counter, which loads an address from the address selector 64 in response to a load signal sent from the control register 2.

In the fourth embodiment of the present invention having the above-mentioned structure, the CPU controls the memory address registers 61, 62, 6
If the memory start address is written in 3 and the address selector 64 is switched by the address select signal,
The value selected at the end of the DMA transfer is set in the internal memory address counter 65. The memory start address can be written by the number of memory address registers. For example, if there are three memory address registers as in this embodiment, the CPU can write three memory start addresses in advance. The CPU only has to select which of the three memory top addresses to use, resulting in C
The burden on the PU can be reduced.

FIG. 7 shows an automatic memory address counter of the fifth embodiment.

Reference numerals 61, 62 and 63 are memory address registers, and the CPU writes the memory start address in each register during the execution of the DMA transfer.

Reference numeral 64 is an address selector which selects and outputs the output of the memory address register by an address select signal.

Reference numeral 65 is a memory address counter, which loads an address from the address selector 64 in response to a load signal sent from the control register 2.

Reference numeral 71 denotes a counter, which sequentially adds the values of the counter in response to a DMA transfer end signal and outputs the result.

Reference numeral 72 denotes a decoder which decodes the output of the counter 71 so that the address selector 64 switches in order and outputs an address select signal.

In the fifth embodiment of the present invention having the above-mentioned structure, the CPU controls the memory address registers 61, 62, 6
If the memory start address is written in 3, the values are sequentially set in the internal memory address counter 65 at the end of the DMA transfer. As many memory start addresses as the number of memory address registers can be written. For example, if there are three memory address registers, the CPU can set the memory start addresses for DMA transfer up to three destinations at any time. As a result, it is possible to prevent the DMA processing of the CPU from concentrating on a certain specific time.

In each embodiment, the present invention is applied to the CD-RO.
Although the case of application to M has been described as an example, the present invention is not limited to each of the above-described embodiments, and various modifications can be carried out without departing from the spirit of the invention.

[0055]

According to the present invention, the following effects can be obtained.

A memory means for storing the memory start address and the number of data transfers is provided, and the next memory start address and the number of data transfers are stored from the CPU during the DMA transfer. The address and the number of data transfers are set in the DMA counter. As a result, it is possible to prevent the DMA settings from being concentrated at a certain specific time, and also to reduce the load on the CPU.

Further, a transfer number memory in which the data transfer number is written in advance is provided, and after the preceding DMA transfer is completed, the data transfer number written in the transfer number memory is counted. Set to. This can reduce the load on the CPU.

Further, a storage means for separately storing the upper and lower addresses of the memory start address of the transfer block is provided, and after the preceding DMA transfer is completed,
The memory start address stored in the storage means is set in the memory address counter. This prevents DMA settings from being concentrated at a specific time, and
The burden on U can be reduced.

Further, a plurality of storage means for storing the memory start address of the transfer block and a selector for selecting the output of the storage means are provided, and the DM executed in advance.
After the A transfer is completed, one is selected from the memory start addresses stored in the storage means and set in the memory address counter. This can reduce the load on the CPU.

Further, a plurality of storage means for storing the memory start address of the transfer block, a selector for selecting the output of the storage means, a counter for sequentially incrementing each time the DMA transfer of one block is completed, A DM is provided which is provided with a decoder which decodes the output of the counter and outputs a selection signal for selecting the selector.
After the A transfer is completed, the memory start addresses stored in the plurality of storage means are sequentially set in the memory address counter. As a result, it is possible to prevent DMA settings from being concentrated at a specific time.

[Brief description of drawings]

FIG. 1 is a block diagram of a DMA device according to a first embodiment.

FIG. 2 is an automatic memory address counter according to the first embodiment,
The block diagram of an automatic transfer number counter.

FIG. 3 is a block diagram of a conventional DMA device.

FIG. 4 is a block diagram of an automatic transfer number counter according to a second embodiment.

FIG. 5 is a block diagram of an automatic memory address counter according to a third embodiment.

FIG. 6 is a block diagram of an automatic memory address counter according to a fourth embodiment.

FIG. 7 is a block diagram of an automatic memory address counter according to a fifth embodiment.

[Explanation of symbols]

1 ... Priority determination circuit, 2 ... Control register, 3 ... Timing control circuit, 4, 5 ... Automatic memory address counter, 6, 7 ... Automatic transfer number counter, 8 ... Address selector.

Claims (6)

[Claims] 1. A DMA for transferring data between a memory and an input / output device by using an arbitrary number of data as one transfer block.
The device is provided with a memory address counter that sequentially adds the initially set memory start address and a transfer number counter that sequentially subtracts the initially set data transfer number, and one block of DMA transfer is completed. After that, the memory start address and data transfer number of the next block are automatically set in the memory address counter and the transfer number counter. 2. The storage device according to claim 1, further comprising storage means for storing the memory start address of the transfer block and the number of data transfers, and after completion of the preceding DMA transfer.
A DMA device for setting the memory start address and the data transfer number stored in the storage means in the memory address counter and the transfer number counter. 3. The transfer number memory according to claim 1, further comprising a transfer number memory in which the data transfer number is written in advance, and the data written in the transfer number memory after the preceding DMA transfer is completed. A DMA device for setting the transfer number in the transfer number counter. 4. The storage means according to claim 1, further comprising storage means for separately storing a high-order address and a low-order address of a memory start address of the transfer block, the storage means being provided after completion of a preceding DMA transfer. DM for setting the memory start address stored in the memory in the memory address counter
A device. 5. The method according to claim 1, further comprising a plurality of storage means for storing a memory start address of the transfer block, and a selector for selecting an output of the storage means, so that the DMA transfer executed in advance is completed. After that, the DMA device that selects one from the memory start addresses stored in the storage means and sets it in the memory address counter. 6. A plurality of storage means for storing a memory start address of the transfer block, a selector for selecting an output of the storage means, and a DM for one block.
After the A transfer is completed, a counter is sequentially added and a decoder for decoding the output of the counter and outputting a selection signal for selecting the selector is provided. A DMA device that sequentially sets the memory start addresses stored in the plurality of storage means in the memory address counter.