JP2896207B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an A / D (analog / digital) converter.

(Prior Art) Conventionally, there is an A / D conversion apparatus that processes A / D conversion requests generated by various request factors in accordance with their priorities.

 FIG. 3 shows a conventional example.

In this figure, 1 is an A / D conversion control circuit, 2 is an analog input channel multiplexer, 3 is an A / D converter,
4 is a read / write (hereinafter referred to as R / W) control circuit,
Reference numeral 5 denotes a data storage resist.

An A / D conversion request from a CPU (not shown) is accepted by an A / D conversion control circuit 1, a channel selection signal is given from the A / D conversion control circuit 1 to a multiplexer 2, and an A / D converter 3 A D conversion start signal is supplied, and a write control signal is supplied to the R / W control circuit 4.

Then, the multiplexer 2 supplies the input analog signal of the channel designated by the channel selection signal to the A / D converter 3, and the A / D converter 3 responds to the A / D conversion start signal to output the analog signal of the input analog signal. Perform D conversion.

The digital data is supplied to the R / W control circuit 4, which writes the digital data from the A / D converter 3 to the register 5 in response to the write control signal.

When the A / D conversion process is completed, the A / D converter 3
The conversion completion signal is given to the A / D conversion control circuit 1. Upon receiving this, the A / D conversion control circuit 1 sends an end notification to the CPU. Thus, one A / D conversion process is completed.

In order to achieve the above priority control using the A / D conversion device, the CPU, when another A / D conversion request occurs during the A / D conversion for a certain A / D conversion request, According to the priority, the currently executing A / D conversion is aborted, the A / D conversion control is performed for a new A / D conversion request, or a new A / D conversion
Remember that the / D conversion request is made after the currently executing A / D conversion is completed.

If the running A / D conversion process is aborted halfway, remember the A / D conversion request that was aborted, and after completing the interrupted A / D conversion process, perform the above control. A / D that was discontinued
The processing is resumed by performing the conversion request.

As described above, even with the above-described conventional device, the priority control of the A / D conversion process can be achieved under the control of the CPU.

However, since priority control is performed by the CPU,
The order of conversion according to the priority and the timing of issuing the conversion start command must be managed by software, during which processing of the CPU is hindered, and this problem becomes serious depending on the type of conversion request.

That is, one conversion process is performed by converting the voltage signal of one channel of the multiplexer 2.
Among various conversion requests, there is a request for performing a plurality of conversion processes by one request. In such a case, you have to spend more time controlling the CPU.

When the processing of one conversion request is terminated and the processing of another conversion request is started, the data by the processing of one conversion request is saved from the register 5, and when the A / D conversion is restarted, Since the processing must be performed from the beginning, there is a problem that the processing that has been performed halfway before the interruption is wasted.

That is, a request for performing a plurality of conversion processes as described above invalidates some processed conversion processes.

(Problems to be Solved by the Invention) As described above, the above-described A / D converter has a problem that the more conversion requests are made, the more CPU is occupied and other processes are stagnated, and the A / D conversion that has been interrupted is performed. When restarting, the process must be performed again from the beginning, so that there has been a problem that the process that has been completed halfway before the interruption is wasted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an A / D converter that enables priority control by hardware.

Further, the present invention provides an A / D conversion device capable of resuming processing of a request without wasting processed data even when processing of a certain conversion request is interrupted when resuming interrupted processing. To provide.

[Configuration of the invention]

(Means for Solving the Problems) In an A / D converter according to the present invention, an analog signal is input from a plurality of channels, and one of the plurality of channels is selected based on a channel selection signal.
Channel conversion means for outputting an analog signal of the selected channel as an input analog signal; and a plurality of conversion request storage means provided for each of the plurality of conversion requests for receiving and holding the corresponding conversion request. A plurality of conversion request storage units each having a different priority for processing, and a plurality of conversion request storage units, each of which is provided in correspondence with the plurality of conversion request storage units and stores a channel to be selected by the channel selection unit. Output as a selection signal, a plurality of conversion channel storage means, and while the input analog signal is input from the channel selection means,
Conversion means for converting an input analog signal into a digital signal in response to a conversion start signal and outputting the data as data, data storage means for storing the data converted into the digital signal, and the plurality of conversion request storages A conversion request storage unit having the highest priority among the plurality of conversion request storage units when a conversion request is held in one or more of the units and a state of any one of the plurality of request storage units is updated; In order to process the conversion request stored in the conversion request storage means, a conversion channel storage means connected to the conversion request storage means having the highest priority is selected, and the channel stored in the selected conversion channel storage means is selected by the channel selection. Controlling to output to the channel selection means as a signal,
Priority control means, start control means for outputting the conversion start signal, which is a signal for starting processing for converting an analog signal of a channel selected by the priority control means to a digital signal, to the conversion means, and the conversion means And a termination control unit for clearing the corresponding conversion request from the plurality of conversion request storage units when the processing of one conversion request is completed.

The A / D converter according to claim 2, wherein the data storage means for storing data converted into a digital signal,
A plurality of the conversion request storage means are provided opposite to each other, and when storing the converted data, the data storage corresponding to the conversion request storage means for processing the conversion request is provided. Stored in the means.

(Operation) According to the present invention, a plurality of conversion request storage units having different priorities for processing conversion requests, and one or more conversion request storage units are stored in the plurality of conversion request storage units. When the priority is held, the priority is controlled, and the priority control means for starting the conversion process from the conversion request having the higher priority is provided, so that the CPU only needs to output the conversion request, and thereafter, Can execute other processing, and stagnation of other processing caused by priority control of conversion requests can be prevented.

In addition, a plurality of data storage means for storing data converted into digital signals are provided opposite to the plurality of conversion request storage means, and when storing the converted data, a conversion request process is performed. Since the data is stored in the data storage means provided opposite the conversion request storage means, even when the processing of a certain conversion request is interrupted, when the interrupted processing is resumed,
The processing for the request is resumed without wasting the processed data.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an A / D conversion apparatus according to an embodiment of the present invention, which is configured to handle three A / D conversion requests.

In this figure, 6 is an R / W control circuit, 71 to 73 are data storage registers, and the registers 71 to 73 are provided corresponding to each A / D conversion request (（). The digital data from the converter 3 is converted by the R / W control circuit 6 into registers 71 (to 7) corresponding to each A / D conversion request (to).
3) is written.

Numerals 81 to 83 denote status circuits. These status circuits 81 to 83 are provided for the respective A / D conversion requests S1 to S3, and each of them is a conversion request storage unit 81a (83a) and a conversion channel storage unit. 81b (up to 83b). Each status circuit 81
(〜83) receives the corresponding A / D conversion request signal S1 (〜S3), and stores the conversion request flag in the conversion request storage unit 81a (〜83a).
F1 (~ F3) is set, and the conversion request storage unit 81a (~ 83
"H" is output from a). Each status circuit 81 (.about.83) holds the conversion channel in the multiplexer 2 as a BCD code in its channel storage section 81b (.about.83b) and outputs this to the multiplexer 2 via a tristate buffer 91 (.about.93). I do.

Reference numeral 101 (-103) denotes a conversion request gate circuit, which is provided for each of the conversion request storage units 81a-83a, receives "H" as the flag signal F1 (-F3) at the conversion request input terminal, and receives an execution permission input terminal. A conversion request signal S1 'corresponding to a conversion request corresponding only when receiving "H" as an enable signal E1 (-E3).
“H” as (〜S3 ′) is supplied to the A / D conversion control circuit 11.

The outputs of the conversion request gate circuits 101 to 103 are supplied to corresponding tri-state buffers 91 (to 93) as on / off control signals, and the conversion request signals S1 '(to 3').
Are supplied to the multiplexer 2.

Reference numeral 12 denotes an uppermost detection circuit to which the flag signals F1 to F3 are input.
The highest-order detection circuit 12 holds priority data defined for the three A / D conversion requests and sets a new flag in the conversion request storage units 81a to 83a, that is, receives a new conversion request. Alternatively, upon receiving an end notification signal from the A / D conversion control circuit 11 described later, if only one conversion request is currently received, the conversion request gate circuit 101 (to 103) corresponding to that conversion request is enabled. Signal E1
(-E3), and when a plurality of conversion requests are currently received, the priority of the plurality of conversion requests is compared, and the conversion request gate circuit 101 having the highest priority corresponds to the highest conversion request. (~ 103) to enable signal E1 (~ E3)
Is output.

The A / D conversion control circuit 11 has conversion request gate circuits 101 to 103.
A / D conversion request signals S1 'to S3' from
Upon receiving any of the A / D conversion request signals S1 'to S3', the conversion control circuit 11 enters the A / D conversion mode, and supplies an A / D conversion start signal to the A / D converter 3, and The channel rewrite signal d1 (〜d3) is provided to the conversion channel storage unit 81b (〜83b), and the write start signal and the write register selection signal are provided to the R / W control circuit 6. Channel rewrite signal d1
(〜D3) is a signal for writing a conversion channel to the corresponding channel storage unit 81b (〜83b). When a plurality of channels are converted by one conversion request, channel data is converted after one conversion. Is rewritten, and the conversion channel input to the multiplexer 2 is switched. The A / D converter 3 performs A / D conversion on an analog signal input in response to the conversion start signal. The R / W control circuit 6 activated in response to the write start signal sends the A / D converter 3 to the register 71 (to 73) designated by the write register selection signal.
The digital data sent from is written, and if the A / D conversion request at this time is one that performs multiple conversion processes in succession, it is written sequentially for each process .

In addition, the A / D conversion control circuit 11
Other A / D conversion request signal S1 '(~ S3') during / D conversion mode
In response to this new conversion request, A /
It becomes the D conversion mode.

That is, the conversion start signal and the write start signal
The D-request S1 '(-S3') is output again, and the channel rewrite signal d1 (-d3) and the write register selection signal are sent to the new A / D conversion request S1 '(-S3'). Is switched to.

Next, the operation of the A / D converter configured as described above will be described with reference to FIG.

First, it is assumed that the conversion request flag F1 is set at time t1 as shown in FIG. Then, this is detected by the highest-order detection circuit 12, and at this time, the flags F2 and F3 of other requests are not set.
The enable signal E1 is input to the gate circuit 101, and the conversion request S1 'is supplied from the gate circuit 101 to the A / D conversion control circuit 11. Then, the A / D conversion control circuit 11 receiving this outputs a conversion start signal and a channel rewrite signal d1 to the channel storage unit 81b as shown in FIG. The signal is input to the R / W control circuit 6. Further, since the conversion request S1 'is also supplied to the tri-state buffer 91, it is turned on, and the channel data from the conversion channel storage unit 81b is supplied to the multiplexer 2.

Thereby, the A / D converter 3
Is supplied with the signal of the channel specified by the conversion request, and A /
The D converter 3 converts the signal into a digital signal. R
The / W control circuit 6 writes the digital signal into the register 71 specified by the register selection signal.

It is assumed that a flag F3 of a conversion request having a lower priority than the conversion request is set at a time t2 during the conversion process as shown in FIG. This is the top detection circuit
12, the priority is compared with the conversion request, but since the priority of the conversion request is higher, the enable signal E3 is not generated. Therefore, the processing for the conversion request is continued, and the conversion request is suspended.

Eventually, at time t3, the A / D conversion processing of the conversion request ends, and the converter 3
Is supplied to the conversion control circuit 11, the conversion control circuit 11 outputs the completion signal at time t4 when the completion signal falls.
The flag F1 is output by outputting the clear signal c1 at
Clear

Since the highest-order detection circuit 12 detects the clearing of the flag F1 and only the flag F3 is set,
The enable signal E3 is output, and the A / D conversion request signal S3 'is input to the conversion control circuit 11. Then, as shown in FIG. 2 (g), a conversion start signal is generated from the conversion control circuit 11, a channel rewrite signal d3 is input to the channel storage unit 83b, and a write start signal and a write register selection signal are output. It is provided to the R / W control circuit 6. The tristate buffer 93 is turned on by the conversion request signal S3 '.

As a result, the analog signal specified by the conversion channel of the conversion request is supplied from the multiplexer 2 to the A / D converter 3, and the converted data is written into the register 73.

At time t5 during the conversion processing of this conversion request, the second
Assume that a flag F2 of a conversion request having a higher priority than the conversion request is set as shown in FIG. Then, since the conversion request has a higher priority in the uppermost detection circuit 12, the enable signal is switched from E3 to E2. Thereby, the conversion request signal to the conversion control circuit 11 is also changed from S3 'to S2'.
To the conversion request from the control circuit 11.
The A / D conversion start signal, the write start signal, the channel rewrite signal d2, and the register selection signal are output, and the tri-state buffer 93 is turned off and the tri-state buffer 92 is turned on, thereby starting the conversion processing of the conversion request. At this time, the data up to the middle of the conversion request remains held in the register 73, and the output channel of the channel storage unit 83b is held in the state at the time of stop of the permission signal output due to the stop of the output of the channel rewrite signal d3. .

When the conversion request processing is completed and the completion signal is generated from the A / D converter 3 at time t6 as shown in FIG. 2 (h), the clear signal is generated at time t7 which is the falling time. Clears flag F2 by outputting c2.

The highest-order detection circuit 12 detects the clearing of the flag F2, and only the flag F3 is set.
The enable signal E3 is output, and the A / D conversion request signal S3 'is input to the conversion control circuit 11. Then, as shown in FIG. 2 (g), a conversion start signal is generated from the conversion control circuit 11, a write start signal and a write register selection signal are given to the R / W control circuit 6, and the channel rewriting is performed. The signal d3 is provided to the channel storage unit 83b. Also, the conversion request signal S3 'causes the tristate buffer 93
Turns on.

As a result, the conversion for the conversion request is restarted.

At this time, the data for the processing completed before the interruption is secured in the register 73, and the conversion channel storage unit 83b is held in the state at the time of the interruption, so that the A / D conversion processing starts from the conversion channel at that time. Will be done.

As described above, according to this embodiment, the priority control by the hardware is achieved, and when the interrupted process is restarted, the processed data is wasted even if the process of a certain conversion request is interrupted. The processing for the request can be resumed without performing the request.

〔The invention's effect〕

As described above, according to the present invention, the A / D converter includes a plurality of conversion request storage units having different priorities for processing the conversion requests, and one or more conversion request storage units in the plurality of conversion request storage units. When the request is held, the priority is controlled, and the priority control means for starting the conversion process from the conversion request having the higher priority is provided, so that the CPU only needs to output the conversion request, and thereafter, Can execute other processing, and can prevent stagnation of other processing caused by priority control of conversion requests.

In addition, a plurality of data storage means for storing data converted into digital signals are provided opposite to the plurality of conversion request storage means, and when storing the converted data, a conversion request process is performed. Since the data is stored in the data storage means provided opposite the conversion request storage means, even when the processing of a certain conversion request is interrupted, when the interrupted processing is resumed,
Processing of the processed data can be resumed without wasting the data.

[Brief description of the drawings]

FIG. 1 is a block diagram of an A / D converter according to an embodiment of the present invention, FIG. 2 is an operation timing chart thereof, and FIG. 3 is a block diagram of a conventional A / D converter. 2 ... Analog input channel multiplexer, 3 ... A /
D converter, 6 R / W control circuit, 71 to 73 Data storage register, 81 to 83 A / D status circuit, 91 to 93
... tri-state buffers, 101 to 103 ... conversion request gate circuits, 11 ... A / D conversion control circuits, 12 ... top-level detection circuits, E1 to E3 ... enable signals (execution permission), F1 to F3 ...
… Conversion request flag, S1 to S3 …… A / D conversion request signal, S
1 'to S3' A / D conversion request signal (execution command).

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-147618 (JP, A) JP-A-62-133 (JP, A) JP-A-2-166549 (JP, A) JP-A-3- 134782 (JP, A) JP-A-63-225821 (JP, A) JP-A-62-204305 (JP, A) Japanese utility model application Sho 61-60340 (JP, U) (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 3/05 H03M 1/12

Claims (2)

(57) [Claims] An analog signal is input from a plurality of channels, one of the plurality of channels is selected based on a channel selection signal, and an analog signal of the selected channel is output as an input analog signal. Selecting means; and a plurality of conversion request storage means provided for each of the plurality of conversion requests and receiving and holding the corresponding conversion request, wherein a plurality of conversion request storages having different priorities for processing the conversion requests are provided. A plurality of conversion channel storage means provided for each of the plurality of conversion request storage means, storing a channel selected by the channel selection means, and outputting the selected channel to the channel selection means as the channel selection signal; The input analog signal is input from the channel selection means, and the input analog signal is input in response to the conversion start signal. And outputs it as data and converts the signal into a digital signal,
A conversion unit; a data storage unit for storing the data converted into the digital signal; and a conversion request held in at least one of the plurality of conversion request storage units, and one of the plurality of request storage units. When the one state is updated, the highest-priority conversion request storage means is processed to process the conversion request stored in the highest-priority conversion request storage means of the plurality of conversion request storage means. Priority control means for selecting the conversion channel storage means provided opposite thereto, and controlling to output the channel stored in the selected conversion channel storage means as the channel selection signal to the channel selection means; Means for converting the analog signal of the channel selected by the means into a digital signal. Start control means for outputting to a stage, and end control means for clearing a corresponding conversion request among the plurality of conversion request storage means when the processing of one conversion request is completed by the conversion means. A / D converter characterized by the fact that: 2. The data storage means for storing data converted into a digital signal is provided in a plurality opposite to the plurality of conversion request storage means, and when storing the converted data, 2. The A / D conversion apparatus according to claim 1, wherein the data is stored in the data storage unit provided opposite the conversion request storage unit that processes the conversion request.