JP2000010908A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a runaway occurring when a process is performed again in array chain transfer mode and restarted after being interrupted by providing a latch circuit which stores the head address of a transfer parameter memory and a latch circuit which stores the number of all transfer blocks transferred to a TCR latch. SOLUTION: The latch circuit SAR latch 2 of a transfer source address register and a register FBSAR 11 which stores the head address of the transfer parameter memory dedicated to the array chain transfer mode are provided in the same addresses where a transfer source address register is set. In the same addresses where a transfer counter register is set, a TCR latch 6 and a register FBTCR 12 which stores the total number of transfer block are provided. Consequently, when a DMA request for the same DMA transfer is accepted, the head address of the transfer parameter memory is specified from the FBSAR 11 and the contents of the FBTCR 12 are transferred to the TCR latch 6, so an array state operates normally and no runaway is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct) having a function of transferring data without a CPU.
Memory Access) controller.

[0002]

2. Description of the Related Art A conventional DMA controller previously stores transfer parameters (a transfer start address of a transfer source, a transfer start address of a transfer destination, and the number of bytes of transfer data) in a DMA-related register. When a transfer request is received, data is transferred between memories based on the value of the register without going through the CPU.

FIG. 8 is a diagram for explaining the configuration of this DMA controller. In FIG. 8, reference numeral 1 denotes a transfer source address register (SAR), 2 denotes a SAR latch of the transfer source address register 1, and 3 denotes a transfer destination address register. (DA
R), 4 is a DAR latch of the transfer destination address register 3,
5 is a transfer counter register (TCR), 6 is a TCR latch of the transfer counter register 5, 7 is a DMA latch, 8 is an increment / decrementer, 9 is a decrementer,
0 is a memory.

Next, the operation will be described. First, at the same time as writing the transfer parameter data to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5, the SAR latch 2, the DAR latch 4,
The same contents are written in the TCR latch 6.

[0005] When a DMA request is received in the DMA enabled state, a read cycle is first performed. In this read cycle,
The transfer source address is specified by the SAR latch 2 of the transfer source address register 1, then the contents of the transfer counter register 5 are updated by the decrementer 9, and the contents of the transfer source address register 1 are updated by the increment / decrementer 8. Then, data is read from the memory 50 and the DMA latch 7
Hold with.

On the other hand, in the write cycle, the transfer destination address is specified by the transfer destination address register 3 and the contents of the transfer destination address register 3 are updated by the increment / decrementer 8. Then, the contents of the DMA latch 7 are written into the memory 50, and this operation is repeated until the value of the transfer counter register 5 becomes "0". However, in the single transfer mode as described above, the SAR latch 2, D
Values are read from the AR latch 4 and the TCR latch 6 and used. The result updated by the increment / decrementer 8 is written to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5. Also, except for the first transfer of the block, values are read from other than the transfer source address register 1, transfer destination address register 3, and transfer counter register 5 and used. As a result, after the DMA transfer is normally completed, the DMA permission bit is set again, and when a DMA request is input, the data of the first transfer parameter of the block is stored in the SAR latch 2, the DAR latch 4, and the TCR latch 6. The same DMA
Transfer can be resumed from the beginning.

On the other hand, in the case of the array chain transfer mode for transferring data of a plurality of blocks, according to the information of each block (the transfer start address of the transfer source, the transfer start address of the transfer destination, and the number of bytes of the transfer data) set in the memory area. Transfer multiple blocks of data. First, as shown in FIG. 9, transfer parameters are written in an arbitrary memory area in advance. Transfer parameters are arranged continuously. In the program, the start address of the transfer parameter memory of the first block is written in the transfer source address register 1 and the SAR latch 2, and the number of transfer blocks is written in the transfer counter register 5 and the TCR latch 6.

When a DMA request is received in the DMA enabled state, first, the transfer source address register 1 designates the start address of the first block of the transfer parameter memory written in an arbitrary memory area from the SAR latch 2. Then, the information (transfer source transfer start address, transfer destination transfer start address, number of bytes of transfer data) of the transfer parameter memory is sequentially transferred to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5 for one block. Write. Source address register 1, destination address register 3,
The transfer counter register 5 is continuously arranged as a DMA-related register. At this time, the SAR latch 2
Sequentially decrements the address of the transfer parameter memory that is being read and stores it.

In this case, a cycle in which the transfer parameters are sequentially read from the transfer parameter memory and written into the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5 is called an array state.

Once the array state is completed, the TCR
The value of the transfer block number stored in the latch 6 is decremented and stored in the TCR latch 6 again. Also,
At this time, the value of the start address of the transfer parameter memory of the next block is stored in the SAR latch 2.

The transfer source address, transfer destination address, and the number of bytes of the transfer data stored in the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5, respectively, depending on the array state. , DMA transfer for blocks. This is called a transfer state.

In the array chain transfer mode, S
The AR latch 2 stores the address of the transfer parameter memory,
The transfer source address register 1 stores the next transfer source address. The DAR latch 4 is not used, and the destination address register 3 stores the next destination address. The TCR latch 6 stores the number of remaining transfer blocks,
Is used to store the number of bytes remaining in the block being transferred.

When the transfer state ends, if the number of remaining blocks stored in the TCR latch 6 is not "0", the transfer source address register 1 stores the next block after the block in which the address is stored in the SAR latch 2. Designates the address of the start address of the transfer parameter memory. Then, the value of the transfer parameter memory for the next one block is written to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5, and the next transfer state is executed. When the value of the number of remaining blocks stored in the TCR latch 6 becomes “0” and the value of the transfer counter register 5 becomes “0”, the process ends normally. At this time, since the value of the SAR latch 2 continues to be decremented during the array state, the value of the address next to the last address of the transfer parameter memory is stored.

When the transfer is normally completed in the array chain transfer mode, the same DMA transfer is performed again, and the DMA permission bit is set in the same manner as in the single transfer mode.
When the MA request is input, the value of the address next to the last address of the transfer parameter memory is stored in the SAR latch 2, and this address is specified in the array state. No data is stored beyond this address,
In the array state, indeterminate values are respectively stored in the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5, and a runaway occurs after the transfer to the transfer state.

Therefore, after the normal end, the same DMA
To resume the transfer, in the single transfer mode,
All that was required was to set the enable bit and enter the DMA request. However, in the case of the array chain transfer mode, the start address of the transfer parameter memory of the first block is again stored in the transfer source address register 1 and the SAR latch 2 by the program.
The number of transfer blocks is written to the transfer counter register 5 and the TCR latch 6, and the DMA
I have to put a request.

If the DMA transfer is forcibly interrupted during the array state, the value of the address in the middle of the block of the transfer parameter memory is stored in the value of the SAR latch 2 and the transfer parameter of the next block is stored. The address value of the start address of the memory is not stored. Therefore, if the DMA permission bit is set as it is to restart the transfer and a DMA request is input, the array state starts from the middle and goes out of control immediately after the transfer to the transfer state. Also,
Even if the DMA transfer is forcibly interrupted during the array state, the start address of the transfer parameter memory of the first block is stored in the transfer source address register 1 and the SAR latch 2 again by the program to restart the transfer. , TCR latch 6 must be written with the number of transfer blocks.

[0017]

Since the conventional DMA controller is configured as described above, in the array chain transfer mode, there is no problem if it is executed only once, but it is executed many times or interrupted. In such a case, if the program is restarted, there is a problem of runaway unless the program is carefully configured as described above.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and provides a DMA controller which can avoid runaway in the case of re-executing or resuming after interrupting once in the array chain transfer mode. The purpose is to:

[0019]

A DMA controller according to the present invention includes a first latch circuit for storing a start address of a transfer parameter memory designated at the start of an array chain transfer, and a TCR at the time of an array chain transfer. And a second latch circuit for storing the total number of transfer blocks transferred to the latch.

In the DMA controller according to the present invention, the first latch circuit and the second latch circuit are registers assigned to specific addresses.

In the DMA controller according to the present invention, the transfer parameter memory is allocated to a specific storage area,
The start address is fixed to a specific address. In the array state and the transfer state, when starting the array chain transfer, the transfer parameter data is read from the start address, and the transfer source address register, the transfer destination address register and the transfer After writing to the counter register, the DMA transfer is started.

In the DMA controller according to the present invention, at the start of the array chain transfer, a selection bit for selecting whether the transfer parameter memory area is freely set or fixed is provided.

The DMA controller according to the present invention has decrement means for decrementing the values of the first latch circuit and the second latch circuit during the array chain transfer as the DMA transfer progresses, and forcibly executes the DMA transfer. When the DMA transfer is started again after the interruption, the DMA transfer is restarted from the beginning of the block during the DMA transfer based on the values of the first latch circuit and the second latch circuit decremented by the decrement means. It is something to do.

In the DMA controller according to the present invention, apart from the first latch circuit for storing the start address of the parameter memory at the start of the array chain transfer, the DMA controller further stores the next address of the block following the block being transferred in the array chain. A third latch circuit for storing the start address of the transfer parameter memory after the transfer from the array state to the transfer state;
The third latch circuit outputs the address of the start address of the transfer parameter memory of the block being transferred, so that the transfer is restarted from the beginning of the block being transferred.

When the DMA controller according to the present invention restarts after the interruption of the array chain transfer, a selection bit for selecting whether to restart the DMA transfer from the beginning of the block being transferred or to restart the DMA transfer from the first block. Is provided.

In the DMA controller according to the present invention, when the array chain transfer is restarted immediately after the transfer, the DMA transfer is restarted from the address immediately after the transfer was interrupted.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. In the DMA controller according to the first embodiment, the transfer source address register, the latch circuit of the transfer source address register (hereinafter, referred to as SAR latch), and the data are transferred exclusively to the array chain transfer mode at the same address where the transfer source address register is set. Register for storing the start address of the parameter memory (hereinafter referred to as File)
st Block Address Register
r, hereinafter referred to as FBSAR). Also, the transfer counter register, the TCR latch, and a register (First Block) for storing the total number of transfer blocks in the same address where the transfer counter register is set.
Transfer Counter Register
r, hereinafter referred to as FBTCR).

FIG. 1 is a block diagram showing the configuration of the DMA controller according to the first embodiment.
Is the source address register (SAR), 2 is the SAR latch of the source address register 1, 3 is the destination address register (DAR), and 4 is the D of the destination address register 3.
AR latch, 5 is a transfer counter register (TCR), 6
Is the TCR latch of the transfer counter register 5, and 7 is the DMA
A latch, 8 is an incrementer / decrementer, 9 is a decrementer, 10 is a DMAC, and 11 is the FBSAR (first latch circuit) for storing the start address of the transfer parameter memory exclusively for the array chain transfer mode. It is a register. Reference numeral 12 denotes an FBTCR (second latch circuit), which is a register for storing the total number of transfer blocks, and keeps holding a value initially written by a program.

Next, the operation will be described. When the DMA transfer is started in the array chain transfer mode, first,
The start address of the transfer parameter memory is designated by FBSAR11. At the same time, the contents of FBTCR12 are
Transfer to Then, in the array state, the transfer parameters for one block are written to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5. At this time, the SAR latch 2 sequentially decrements the address of the read transfer parameter memory and stores the address. Once the array state is completed, the value of the number of transfer blocks stored in the TCR latch 6 is decremented and stored in the TCR latch 6 again. At this time, the value of the start address of the transfer parameter memory of the next block is stored in the SAR latch 2. Thereafter, the transfer state is executed, and this operation is repeated until the contents of the TCR latch 6 and the transfer counter register 5 become "0", thereby terminating the array chain transfer.

At the end of the normal operation, the value of the SAR latch 2 has been decremented during the array state. Therefore, the value of the address next to the last address of the transfer parameter memory is stored. Is also "0". FBSAR11 and FBTCR12
Is a state where the contents written by the program at the beginning are held.

Therefore, when the same DMA transfer is performed again and the DMA request is set and the DMA request is input in the same manner as in the single transfer mode, the FBSAR 11
The start address of the transfer parameter memory is specified from
Since the contents of the TCR 12 are transferred to the TCR latch 6,
The array state operates normally and does not run away.
In addition, it is not necessary to write values to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5 again as in the related art, and the operation can be restarted easily.

As described above, according to the first embodiment, when the same DMA transfer is performed again, the FB in which the contents initially written by the program are held is held.
SAR11 and FBTCR12 are used and FBSA
Since the start address of the transfer parameter memory is specified from R11 and the contents of the FBTCR 12 are transferred to the TCR latch 6, the transfer source may be re-executed in the array chain transfer mode, or may be interrupted and restarted. There is no need to rewrite values to the address register 1, the transfer destination address register 3, and the transfer counter register 5 by a program, and a DMA controller that can avoid runaway due to re-execution in the array chain transfer mode, resumption after interruption, or the like can be obtained. effective.

Embodiment 2 FIG. FIG. 2 shows the second embodiment.
FIG. 4 is a diagram showing a memory arrangement configuration of DMA-related registers in the DMA controller of FIG. In FIG. 2, reference numeral 13 denotes a first array chain transfer mode dedicated register (register), 1
Reference numeral 4 denotes a second array chain transfer mode dedicated register (register).

In the DMA controller of the second embodiment, in the array chain transfer mode, the first array chain transfer mode dedicated register 13 for storing the start address of the transfer parameter memory and the total number of transfer blocks are stored in advance. When the second array chain transfer mode dedicated register 14 for storing is provided separately to execute the array chain transfer mode, it is not necessary to write a value to the transfer source address register 1 and the transfer counter register 5 as in the conventional case. To

Next, the operation will be described. In the array chain transfer mode, when a DMA request is input in a DMA enabled state, the first array chain transfer mode dedicated register 13
, The start address of the transfer parameter memory is output and specified, and the data of the total number of transfer blocks is stored in the TCR latch 6 from the second array chain transfer mode dedicated register 14.
Is forwarded to Thereafter, the array state and the transfer state are repeated as in the conventional example, and the DMA transfer is completed.

After the normal end of the DMA transfer, the first address of the transfer parameter memory and the number of transfer blocks are stored in the first array chain transfer mode dedicated register 13 and the second array chain transfer mode dedicated register 14, respectively. Has become. For this reason, the same DMA transfer can be performed again without going out of control simply by entering the DMA request again and entering the DMA request.

As described above, according to the second embodiment, the first array chain transfer mode exclusive register 13 and the second array chain transfer mode register in which the start address of the transfer parameter memory and the number of transfer blocks are stored respectively. In the array chain transfer mode, when the DMA is enabled, the DMA
When a request is received, the first address of the transfer parameter memory is designated from the first array chain transfer mode dedicated register 13, and the data of the total number of transfer blocks is transferred from the second array chain transfer mode dedicated register 14 to the TCR latch 6. Therefore, there is an effect that a DMA controller that can avoid runaway occurring when re-executing in the array chain transfer mode can be obtained.

Embodiment 3 FIG. 3 shows the third embodiment.
3 is a memory layout diagram of a transfer parameter memory in the DMA controller of FIG. In the DMA controller according to the third embodiment, the address of the transfer parameter memory is set to a fixed address. In the memory layout diagram of FIG. 3, addresses “00F000H” to “00F100H” in the ROM area are fixed as transfer parameter memory areas.

When the array chain transfer mode is executed, the transfer parameters are read from the address "00F000H" and transferred to the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5, and then the transfer state is changed. Let it run.

The end of the array chain transfer mode is determined by adding “0” to the head data (transfer source transfer start address) of the transfer parameter of one block following the parameter of the block to be transferred.
"00000H" is written in advance, DMA transfer is executed, and when "000000H" is read into the SAR latch 2 at the end of the array state, the transfer state of the block is executed and then the DMA transfer is terminated.

In the example of FIG. 3, since "300000H" is written in the first address (transfer source transfer start address) of the transfer parameter of the fourth block after three blocks have been transferred.
When the array state of the block ends, the SAR
“000000” is stored in the latch 2. Therefore, the transfer state of the third block ends, and all DMA transfers end.

In this embodiment, in order to set the address of the transfer parameter memory to a fixed address, it is necessary to write the head address of the transfer parameter memory and the number of transfer blocks in the SAR latch 2 and the TCR latch 6 in advance. There is no.

As described above, according to the third embodiment, the same DMA is again performed in the array chain transfer mode.
When it is desired to execute the transfer, there is an effect that a DMA controller capable of performing the same DMA transfer without runaway can be obtained by a simple operation of putting a DMA request in a DMA enabled state.

Embodiment 4 FIG. In the third embodiment, the method of fixing the transfer parameter memory area to a specific address has been described.
Any of the above methods may be selectable. FIG. 4 is a diagram illustrating a DMAC control register in the DMA controller according to the fourth embodiment. FIG.
, 21 is a DMAC control register. As shown in FIG. 4, a transfer parameter memory area selection bit is assigned to a specific bit (in this case, bit 0) of the DMAC control register 21. When the content of the transfer parameter memory area selection bit is "0", the array state is executed by the method of the first embodiment. That is, FBSAR1
First, the start address of the transfer parameter memory is set to F
Write the total number of transfer blocks in the BTCR 12
When the MA controller is started, it specifies the start address of the first block of the transfer parameter memory written in an arbitrary memory area from the FBSAR 11, executes the array state, and executes the transfer state.

When the content of the transfer parameter memory area selection bit is "1", the array state is executed by the method of the third embodiment. That is, the transfer parameters fixed at a specific address are sequentially read and stored in the transfer source address register 1, the transfer destination address register 3, and the transfer counter register 5, and the transfer state is executed. If there is a memory area that is obviously not used, it is easier to build a program by setting the transfer parameter area selection bit to “1” and using the fixed transfer parameter area.

As described above, according to the fourth embodiment, there is provided an effect that a DMA controller that can select fixed or non-fixed fixed parameter areas according to the presence or absence of unused memory areas and can facilitate program construction is obtained. There is.

Embodiment 5 In the first embodiment, the FB
Since the contents of SAR11 and FBTCR12 did not change unless rewritten by a program, D
After suspending the MA transfer, if the DMA is enabled and a DMA request is input and restarted as it is, the transfer is always restarted from the first address of the first block. Therefore, at the time of restarting after the transfer is interrupted, if it is desired to restart the DMA transfer from the block immediately after the interruption, the contents of the FBSAR 11 and the FBTCR 12 must be rewritten.

In the fifth embodiment, the first embodiment is used.
As the DMA transfer progresses, the values of FBSAR11 and FBTCR12 are decremented by one block as the DMA transfer progresses, so that when the DMA transfer is interrupted, when the DMA transfer is restarted, the DMA transfer is started from the block next to the block being transferred. Be able to resume.

In the array chain transfer mode, when the array state is completed, the SAR latch 2 stores the address value of the start address of the next block in the transfer parameter memory. When initiating the transfer state, typically D
The configuration is such that the trigger signal T is generated for about one cycle of the internal clock in the MA controller.
As shown in (1), data is transferred from the SAR latch 2 to the FBSAR 11 and from the TCR latch 6 to the FBTCR 12 in response to the trigger signal T. Therefore, after the transition from the array state to the transfer state, the start address of the transfer parameter memory of the next block is stored in the FBSAR 11 and the number of remaining blocks is stored in the FBTCR 12.

When the DMA transfer is interrupted during the transfer state and then restarted, the FBSAR 11 specifies the start address of the block next to the block at the time of the transfer interruption. Transfer can be resumed. If the DMA transfer is interrupted during the array state, the FBSAR 11 stores the start address of the transfer parameter memory of the block at the time of the transfer interruption. Can be resumed.

As described above, according to the fifth embodiment, the values of FBSAR11 and FBTCR12 are
As the A transfer progresses, it is decremented for each block, so that when the DMA transfer is interrupted and restarted, the DMA transfer can be restarted from the block following the block being transferred without rewriting the contents of the FBSAR 11 and the FBTCR 12. There is an effect that a DMA controller can be obtained.

Embodiment 6 FIG. In the fifth embodiment, runaway does not occur when the operation is restarted after the interruption in the array state. However, in the last block, the FBSAR11
If an address outside the transfer parameter memory area is stored in the memory, the program will run out of control if it is restarted. Therefore, as shown in FIG. 6, the NBSAR (Next Block Sou) is stored in the same address of the transfer source address register 1.
rc (Address Register) (third latch circuit) 15 is similarly stored in the same address of the transfer counter register 5 in the NBTCR (Next Block Tr).
answer CounterRegister) 16
Is provided separately.

When shifting from the array state to the transfer state, the trigger signal T causes the SAR latch 2 to switch to NBSA.
Data is transferred from the R15 and the TCR latch 6 to the NBTCR 16, respectively. Therefore, after shifting from the array state to the transfer state, the start address of the transfer parameter memory of the next block is stored in the NBSAR 15 and the number of remaining blocks is stored in the NBTCR 16 respectively.
1 and the contents of the FBTCR 12 do not change unless rewritten by a program.

Interrupting the DMA transfer during the array state,
When the restart is performed as it is, the head address of the transfer parameter memory is designated from the NBSAR 15, and the DMA transfer is restarted from the beginning of the block at the time of the transfer interruption. When the DMA transfer is interrupted during the transfer state and restarted as it is, the head address of the transfer parameter memory is designated from the NBSAR 15, and the DMA transfer is restarted from the beginning of the block following the block at the time of the transfer interruption. Whether the DMA transfer is interrupted or terminated normally is automatically determined based on the contents of the transfer counter register 5 and the TCR latch 6. D
When starting the MA transfer, in the array chain transfer mode and when the contents of the transfer counter register 5 and the TCR latch 6 are "0", it is determined that the transfer is completed normally. If the contents of the transfer counter register 5 and the TCR latch 6 are other than "0" in the array chain transfer mode, it is determined that the transfer was interrupted halfway.

If the operation is restarted as it is after the normal termination, the contents of the transfer counter register 5 and the TCR latch 6 are checked, the head address of the transfer parameter memory is automatically designated from the FBSAR 11, and the start of the array chain transfer mode is started. DMA transfer is started from the beginning of the block. Also, as when the array chain transfer mode is started for the first time, the transfer source address register 1, SA
When the same value is stored in the R latch 2, FBSAR11 and NBSAR15, the transfer counter register 5 and T
Regardless of the contents of the CR latch 6, the start address of the transfer parameter memory is designated from the FBSAR 11, and the DMA transfer is started from the beginning of the first block in the array chain transfer mode.

As described above, when starting the array chain transfer mode, the transfer counter register 5 and the TC
The contents of the R latch 6 are checked, and the start address of the transfer parameter memory is designated by the FBSAR 11 or the NBSAR 11
At 15, it is automatically determined whether the start address of the transfer parameter memory is specified.

As described above, according to the sixth embodiment, when the array chain transfer mode is executed for the first time or when the operation is restarted after the normal termination, the start can be easily started from the first block. Even when restarting after an interruption, it is automatically determined whether the interruption is in the array state or in the transfer state, and it is easy to restart from the block being transferred or the block after the transfer was interrupted. When the transfer is interrupted in the transfer state, there is an effect that a DMA controller that does not run out of control even when restarted as it is can be obtained.

Embodiment 7 FIG. In the sixth embodiment, when the array chain transfer mode is started, the contents of the transfer counter register 5 and the TCR latch 6 are checked,
Whether the start address of the transfer parameter memory is designated by the BSAR 11 or the start address of the transfer parameter memory is designated by the NBSAR 15 is automatically determined. As shown in FIG. 7, the transfer is performed by either the FBSAR 11 or the NBSAR 15. An FB / NB selection bit for selecting whether to specify the start address of the parameter memory may be provided.

FIG. 7 shows FBSAR11 and NBSAR15.
Is assigned a FB / NB selection bit for selecting which of the above specifies the start address of the transfer parameter memory.
FIG. 3 is a diagram illustrating a MAC control register 21. As shown in FIG. 7, the FB / NB selection bit (in this case, bit 1)
Is "0", the array chain transfer mode is started, the start address of the transfer parameter memory is designated by the FBSAR 11, and the DMA transfer is started from the beginning of the first transfer block.

When the array chain transfer mode is started when the content of the FB / NB selection bit is "1", the start address of the transfer parameter memory is designated by the NBSAR 15. First, when the value of the start address of the transfer parameter memory is written to the transfer source address register by the program, it is simultaneously written to the transfer source address register 1, the SAR latch 2, the FBSAR11, and the NBSAR15. When starting, the value of the start address of the transfer parameter memory of the first block same as FBSAR11 is stored in NBSAR15.

Therefore, when the array chain transfer mode is executed for the first time with the content of the FB / NB selection bit set to "1", the content of the FB / NB selection bit is set to "0".
Performs the same operation as When interrupted during the execution of the array chain transfer mode and restarted as it is, N
The BSAR 15 specifies the start address of the transfer parameter memory and restarts the DMA transfer. However, NBSAR15
Depending on the contents of the NBSAR15, such as when restarting after interrupting in the transfer state of the last block.
There is a possibility that the value of an address outside the transfer parameter memory area is stored in the memory and a runaway occurs. Therefore, when starting the array chain transfer mode, if the contents of the transfer counter register 5 and the TCR latch 6 are "0", the start address of the transfer parameter memory is designated from the FBSAR 11 regardless of the contents of the bit.

Therefore, when the array chain transfer is interrupted and restarted, it is possible to select from a program whether to restart from the first block or to restart from an intermediate block.

As described above, according to the seventh embodiment, when starting the array chain transfer mode,
Whether the start address of the transfer parameter memory is specified by the FBSAR 11 or the start address of the transfer parameter memory by the NBSAR 15 can be selected by a program based on the FB / NB selection bit, eliminating the possibility of runaway. There is an effect that a DMA controller that can be obtained is obtained.

Embodiment 8 FIG. In the eighth embodiment, in FIG. 6 of the sixth embodiment, when the DMA transfer is restarted after the DMA transfer is interrupted, the DMA transfer can be resumed from the address immediately after the transfer is interrupted. When starting the array chain transfer mode, the transfer source address register 1,
When the SAR latch 2, FBSAR11, and NBSAR15 all contain the same value, regardless of the contents of the transfer counter register 5 and the TCR latch 6, the FBSAR
11, the start address of the transfer parameter memory is designated, and the DMA transfer is started from the beginning of the first block in the array chain transfer mode.

As in the case of normal termination, the transfer source address register 1, SAR latch 2, FBSAR11, NBSAR
15 and the contents of both the transfer counter register 5 and the TCR latch 6 are both "0", the start address of the transfer parameter memory is designated by the FBSAR 11, and DM
A transfer is started.

When the DMA transfer is interrupted on the way, first,
When interrupted in the array state, the transfer source address register 1, SAR latch 2, FBSAR11, NBSAR15
And the transfer counter register 5
Of the TCR latch 6 takes a value other than "0". At this time, the value of the start address of the transfer parameter memory of the block at the time of the transfer interruption is stored in the NBSAR 15.

When interrupted during the transfer state, the transfer source address register 1, SAR latch 2, FBSAR1
1, the same value is not entered in the NBSAR 15, and the contents of the transfer counter register 5 and the TCR latch 6 both take values other than "0". However, in the last block, the contents of the transfer counter register 5 are other than "0",
The content of the R latch 6 becomes "0". At this time, NBSA
R15 stores the value of the start address of the transfer parameter memory of the next block at the time of transfer interruption.

Therefore, when the array chain transfer mode is interrupted and restarted in that state, whether the interrupt was interrupted during the array state or during the transfer state is determined by the contents of the transfer counter register 5.

As a result, if the transfer is interrupted during the array state, the contents of the transfer counter register 5 are other than "0" and the contents of the TCR latch 6 are other than "0" at the time of restart. Specify the starting address. Then, the array state is executed, the transfer state is executed, and the normal array chain transfer mode is continued to end.

If the transfer state is interrupted, the SAR latch 2 and the FBSAR 2 are determined at the time of restart by judging from the contents of the transfer counter register 5 and the TCR latch 6.
11, the NBSAR 15 outputs the transfer start address of the transfer source immediately after the transfer is interrupted from the transfer source address register 1 and resumes the DMA transfer (transfer state) from the state immediately after the transfer was interrupted. Even after the transfer state is completed, the head address of the transfer parameter memory of the next block is designated from the SAR latch 2 and the array state is executed.
Execute the array chain transfer mode until the end.

As described above, in the prior art, after the array chain transfer is interrupted, when restarting, the address immediately after the interrupted transfer is
When the MA transfer is restarted, the array chain transfer mode is temporarily changed to the single transfer mode, and only the remaining data of the block being transferred can be DMA-transferred. There is an effect that a DMA controller that can easily restart the DMA transfer from the subsequent data can be obtained.

[0072]

As described above, according to the present invention, the first latch circuit for storing the start address of the transfer parameter memory designated at the start of the array chain transfer, and the TCR latch at the time of the array chain transfer And a second latch circuit for storing the total number of transfer blocks transferred to the transfer source address register in the array chain transfer mode in the re-execution and resumption after interruption as in the prior art. This makes it possible to re-execute in the array chain transfer mode, resume after an interruption, etc. without having to rewrite the values to the transfer destination address register and the transfer counter register by a program. This has the effect of avoiding possible runaway.

According to the present invention, the first latch circuit and the second latch circuit are configured as registers assigned to specific addresses. Therefore, in the array chain transfer mode, a DMA request is issued again in the DMA enabled state. When you enter,
The start address of the transfer parameter memory is designated from the register, and the data of the total number of transfer blocks is transferred from the register to the TCR latch, thereby avoiding runaway that occurs when re-executing in the array chain transfer mode. .

According to the present invention, the transfer parameter memory is allocated to a specific storage area, and the starting address is fixed to a specific address. After reading the transfer parameter data from the address and writing the data to the transfer source address register, transfer destination address register and transfer counter register, respectively, the DMA transfer is started. With the simple operation of simply inputting a DMA request, the same DMA transfer can be performed without runaway.

According to the present invention, when the array chain transfer is started, the transfer parameter memory area can be set freely,
Since the selection bit for selecting whether to fix the data is provided, the transfer parameter memory area is fixed according to the presence or absence of the unused memory area, thereby facilitating the program and realizing the DMA transfer without runaway in the array chain transfer mode. effective.

According to the present invention, during the array chain transfer, the first latch circuit for storing the start address of the parameter memory at the start of the array chain transfer and the total number of transfer blocks during the array chain transfer are stored. A decrement means for decrementing the value of the second latch circuit for keeping the DMA transfer as the DMA transfer progresses. When the DMA transfer is restarted after the DMA transfer is forcibly interrupted, the value is decremented by the decrement means. Since the DMA transfer is restarted from the beginning of the block in the middle of the DMA transfer based on the values of the first latch circuit and the second latch circuit, the first latch circuit and the second Since the value of the latch circuit is decremented every block as the DMA transfer proceeds,
When the DMA transfer is restarted after the DMA transfer is interrupted, the DMA transfer can be restarted from the beginning of the block during the DMA transfer without rewriting the contents of the first latch circuit and the second latch circuit.

According to the present invention, apart from the first latch circuit for storing the start address of the parameter memory at the start of the array chain transfer, the transfer parameter of the block next to the block being transferred in the array chain is further A third latch circuit for storing a head address of the memory after the transfer from the array state to the transfer state, and when the transfer is resumed after the interruption of the array chain transfer, the transfer of the block being transferred from the third latch circuit is performed. By outputting the address of the start address of the parameter memory, the transfer is restarted from the beginning of the block being transferred.
When the array chain transfer mode is executed for the first time, or when restarting in that state after normal termination, it is easy to start from the first block. It can automatically determine whether the transfer state has been interrupted or not, and can easily restart from the block being transferred or the block after the transfer was interrupted. This has the effect of disappearing.

According to the present invention, when restarting after the transfer of the array chain is interrupted, D from the beginning of the block in the middle of the transfer.
Since the selection bit for selecting whether to restart the MA transfer or to restart the DMA transfer from the first block is provided, when starting the array chain transfer mode, from the beginning of the block being transferred, or Whether to restart the DMA transfer from the first block can be selected by a program based on the FB / NB selection bit,
This has the effect of eliminating the possibility of runaway.

According to the present invention, the DMA transfer is resumed from the address immediately after the interruption of the transfer when the array chain transfer is restarted immediately after the interruption of the array chain transfer. Thus, there is an effect that the DMA transfer can be easily restarted from the data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DMA controller according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a memory arrangement configuration of DMA-related registers in a DMA controller according to a second embodiment of the present invention;

FIG. 3 is a memory layout diagram of a transfer parameter memory in a DMA controller according to Embodiment 3 of the present invention.

FIG. 4 is a diagram illustrating a DMAC control register in a DMA controller according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a DMA controller according to Embodiment 5 of the present invention.

FIG. 6 is a block diagram showing a configuration of a DMA controller according to a sixth embodiment of the present invention.

FIG. 7 is a diagram illustrating a DM to which an FB / NB selection bit is assigned in a DMA controller according to a seventh embodiment of the present invention;
FIG. 3 is a diagram illustrating an AC control register.

FIG. 8 is a diagram illustrating a configuration of a conventional DMA controller.

FIG. 9 is a diagram illustrating transfer parameters written in advance in an arbitrary memory area of a conventional DMA controller.

[Explanation of symbols]

1 transfer source address register, 2 SAR latch, 3
Transfer destination address register, 5 transfer counter register,
6 TCR latch, 11 FBSAR (first latch circuit), 12 FBTCR (second latch circuit), 13
First array chain transfer mode dedicated register (register), 14 Second array chain transfer mode dedicated register (register), 15 NBSAR (third latch circuit).

Continuation of the front page (72) Inventor Danichi Komatsu 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5B061 DD01 DD06 QQ01

Claims (8)

[Claims] A transfer source address register for storing a next transfer source address of a transfer parameter memory; a SAR latch for storing an address of the transfer parameter memory; a transfer destination address register for storing a next transfer destination address; A transfer counter register for storing the number of bytes of the block, and a TCR latch for storing the number of remaining transfer blocks;
A DMA controller for performing a DMA transfer of data by repeating an array state and a transfer state; a first latch circuit for storing a start address of the transfer parameter memory designated at the start of the array chain transfer; A second latch circuit for storing the total number of transfer blocks transferred to the TCR latch. 2. The DMA controller according to claim 1, wherein the first latch circuit and the second latch circuit are registers assigned to specific addresses. 3. A transfer parameter memory, in which a specific storage area is allocated and a start address is fixed to a specific address. In an array state and a transfer state, when starting an array chain transfer, transfer is performed from the start address. 3. The DMA according to claim 1, wherein the DMA transfer is started after the parameter data is read and written into the transfer source address register, the transfer destination address register, and the transfer counter register, respectively.
controller. 4. The DMA controller according to claim 3, further comprising a selection bit for selecting whether to freely set or fix the transfer parameter memory area at the start of the array chain transfer. 5. A first latch circuit for storing a start address of a parameter memory at the start of an array chain transfer during an array chain transfer, and a first latch circuit for storing a total number of transfer blocks during an array chain transfer. A decrement means for decrementing the value of the second latch circuit as the DMA transfer progresses; when the DMA transfer is forcibly interrupted and the DMA transfer is started again, the first decremented by the decrement means. From the beginning of the block in the middle of DMA transfer based on the values of the latch circuit and the second latch circuit.
3. The DMA controller according to claim 1, wherein the A transfer is restarted. 6. A head address of a transfer parameter memory of a block next to a block being transferred in the array chain, separately from a first latch circuit for storing a head address of the parameter memory at the start of the array chain transfer. A third latch circuit for storing after the transfer from the array state to the transfer state, and when the array chain transfer is interrupted and resumed, the third latch circuit stores the start of the transfer parameter memory of the block being transferred from the third latch circuit. 3. The DMA controller according to claim 1, wherein the DMA controller restarts the transfer from the beginning of the block being transferred by outputting the address of the address. 7. When restarting after an array chain transfer is interrupted, a selection bit is provided for selecting whether to restart the DMA transfer from the beginning of the block being transferred or to restart the DMA transfer from the first block. 7. The DMA controller according to claim 6, wherein 8. The DMA controller according to claim 6, wherein the DMA transfer is restarted from the address immediately after the transfer is interrupted when the array chain transfer is restarted immediately after the transfer is interrupted.