JPH0285951A - Input/output bus cycle control system - Google Patents

Abstract

PURPOSE:To improve the performance of an input/output bus cycle control system by transferring the number of idle clocks stored in a 2nd memory means to a counter and delaying the start of the input/output bus cycle in the case the coincidence is secured between the address stored in a 1st memory means and the address of the input/output bus cycle. CONSTITUTION:The data '1011101011001101' is stored in a recovery time control register 111. In the case an address '1011101011001XXX' is outputted as an input/output address of 16 bits with execution of an input/output instruction, the coincidence is secured between the higher 13 bits of the register 111 and the higher 13 bits of the input/output address. Therefore a coincidence signal line 115 of a comparator 112 is set at '1' and the lower 3 bits '101' of the register 111 are outputted to a signal line 114. When an input/output bus cycle end signal line 308 is set at '1', '101' is loaded to a counter 302 and 5 clocks are set as the recovery time. Thus the performance is improved in an input/ output bus cycle control system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and more particularly to a microprocessor capable of inserting an idle cycle between input/output bus cycles caused by input/output instructions.

[Conventional technology]

In general, when a microprocessor reads data from a peripheral device with an input instruction or writes data with an output instruction, it requires a certain amount of recovery time between I/O bus cycles. During this period, access to the same 9 peripheral devices must not be made. Generally, this recovery time differs for each peripheral device.

Conventionally, the number of idle clocks to be inserted has been set in accordance with the device that requires the longest recovery time, as the recovery time differs depending on each device.

The configuration and operation of a microprocessor that secures recovery time by inserting a fixed idle clock between input/output bus cycles caused by input/output instructions will be described below with reference to the drawings.

FIG. 3 is an example of a conventional microprocessor.

In FIG. 3, 300 is a bus cycle request unit;
1 is a bus cycle control unit, and 302 is a counter. Further, 303 is a memory bus cycle request signal line;
4 is an input/output bus cycle request signal line, 305 is a counter zero detection signal line, 306 is a memory bus cycle start signal line, 307 is an input/output bus cycle start signal line, and 308 is an input/output bus cycle end The signal lines 309 are READY signal lines, and 310 is a clock.

Next, the operation of this conventional example will be explained using the drawings.

In FIG. 3, when an input command or an output command is executed, the input/output bus cycle request signal line 304 is set to “1n
and requests the bus cycle control unit 301 to start an input/output bus cycle. If the bus cycle control unit 301 is in a state where it can start the bus cycle, it sets the input/output bus cycle start signal line 307 to "1" to start the input/output bus cycle. The input/output bus cycle is completed in two clocks, TI and T2, and the input/output bus cycle end signal line 308 is set to "1".

Here, if there is a wait cycle insertion request from the READY signal line, the input/output bus cycle end signal line 308 becomes "1" with a delay of that amount.The input/output bus cycle end signal line 307 becomes "1". When it reaches "1", the counter starts counting and the zero detection signal line 305 becomes "0".
1, and while this signal line 305 is "0", the input/output bus cycle request signal line 304 is masked and no bus cycle is activated. Next, when the counter finishes counting down and becomes "0" again, the zero detection signal line 305 becomes "1", permitting activation of the input/output bus cycle. FIG. 4 shows this series of timing diagrams. In FIG. 4, Ti (idle cycle) inserted while the counter is performing a counting operation is called recovery time. In the conventional example, the recovery time is set to 7 clocks. Also, the memory bus cycle request signal line 30
3 is accepted whenever the bus is available, regardless of the recovery time of the I/O bus cycle, and sets the memory bus cycle start signal line 306 to "1n."

[Problem to be solved by the invention]

In the microprocessor of the conventional example, the recovery time is set according to the device that requires the longest recovery time among the peripheral devices that can be normally connected. As a result, more idle clocks than necessary may be applied to peripheral devices that require a short recovery time, and CPU
Since the number of idle clocks to be inserted is determined according to the maximum operating frequency of the U, even when using a clock with a low frequency, more recovery time than necessary may be inserted, which may cause considerable problems depending on the system used. This had the disadvantage of causing a decline in performance.

[Differences between the invention and the prior art]

In a microprocessor, the number of idle clocks between the end of an I/O bus cycle and the start of the next I/O bus cycle is determined in order to obtain adequate recovery time for the I/O devices. This differs from the prior art in that it can be freely set for each input/output address according to the peripheral device used.

[Means to solve the problem]

The present invention provides a microprocessor having a function of inserting an idle clock between the end of an input/output bus cycle and the start of the next input/output bus cycle. storage means for storing the number of idle clocks to be inserted, and a second storage means for storing the number of idle clocks to be inserted.
a comparison means for comparing the address stored in the first storage means and the address of the input/output bus cycle; a counter for counting the number of clocks from the end of the input/output bus cycle; and bus cycle control means for inhibiting the start of the next input/output bus cycle.

〔Example〕

Next, the configuration and operation of the present invention will be explained using the drawings.

[Example 1] A first embodiment of the invention is shown in FIG.

In FIG. 1, 300 is a bus cycle request unit;
1 is a bus cycle control unit, and 302 is a counter. Further, 303 is a memory bus cycle request signal line;
4 is an input/output bus cycle request signal line, 305 is a counter zero detection signal line, 306 is a memory bus cycle start signal line, 307 is an input/output bus cycle start signal line, and 308 is an input/output bus cycle end The signal lines 309 are READY signal lines, 310 are clocks, 111 are recovery time control registers, 112 are comparators, 113 are upper 13 bits of the internal address bus of the CPU, and 115 is a match signal line of the comparators.

The recovery time control register 111, as shown in FIG.
The lower 3 bits store the clock number of the recovery time, and the higher 13 bits store the input/output address. This register is set before accessing each peripheral device.

Next, the operation of this conventional example will be explained using the drawings.

In FIG. 1, when an input command or an output command is executed, the input/output bus cycle request signal line 304 becomes "1".
and requests the bus cycle control unit 301 to start an input/output bus cycle. If the bus cycle control unit 301 is in a state where it can start the bus cycle, it sets the input/output bus cycle start signal line 307 to "1" to start the input/output bus cycle. An input/output bus cycle is completed in two clocks, Tl and T2. During this time, the upper 13 bits of the input/output address are output to the internal address bus 113, and the upper 13 bits of the preset recovery time control register 111 and the comparator 112 are output.
If they match, the value of the lower three bits of the recovery time control register 111 is output to the signal line 114. When the input/output bus cycle ends, the bus cycle control unit 310 sets the input/output bus cycle end signal line 308 to "1". Here, if there is a wait cycle insertion request from the READY signal line, the input/output bus cycle end signal line 308 becomes "1" with a corresponding delay. When the input/output bus cycle end signal line 308 becomes "1", the contents of the signal line 114 are loaded into the counter 302, and the counter 302 starts counting. While the counter 302 is performing counting operation, the zero detection signal line 305 is “0”
become. The zero detection signal line 305 is input to the bus cycle control unit 301, and while the zero detection signal line 305 is "0", it masks the input/output bus cycle request signal line 304 and prevents the activation of the input/output bus cycle. Not performed. Next, when the counter finishes counting down and becomes '0' again, the zero detection signal line 305 becomes '1', allowing the start of the input/output bus cycle. Line 303 is accepted whenever the bus is available, regardless of the recovery time of the I/O bus cycle, and is used as the memory bus cycle start signal line 30.
Change 6 to 1”.

Next, a more specific explanation will be given using FIG. 6.

First, write “1011101” in the recovery time control register 111.
Data 011001101'' is stored.

Next, when the address “1011101011001XXX” is output as a 16-bit input/output address by executing an input/output instruction, the upper 13 bits of 111 and the upper 13 bits of the input/output address match, so the comparator 112 The match signal line 115 becomes "1", and the lower three bits of 111, "101", are output from the signal line 114-. When the input/output bus cycle end signal line 308 reaches ",""101"' is loaded into the counter 302, and five clocks are set as the recovery time. In this embodiment, the lower three bits of the input/output address are ignored. However, by changing the register length of the recovery time control register 111, the bit length of the input/output address to be compared can be freely determined.

In this embodiment, there is one recovery time control register, and if the input and output addresses do not match, no recovery time is set and the recovery time is set to "0". Next, an example having a plurality of recovery time control registers will be explained.

[Example 2] A second embodiment of the present invention will be described.

In the first embodiment, there is only one set of recovery time control registers and comparators, so there is only one type of input/output address for which the recovery time can be set, but multiple recovery time control registers and comparators are used. By having a set of different recovery times for multiple input/output addresses, different recovery times can be set for multiple input/output addresses. In the second embodiment, an example will be described in which two sets of recovery time control registers and comparators are provided.

A second embodiment of the invention is shown in FIG.

In FIG. 2, 300 is a bus cycle request unit;
1 is a bus cycle control unit, and 3o2 is a counter. Further, 303 is a memory bus cycle request signal line;
4 is an input/output bus cycle request signal line, 305 is a counter zero detection signal line, 306 is a memory bus cycle start signal line, 307 is an input/output bus cycle start signal line, and 308 is an input/output bus cycle end Signal line, 309 is READY signal line, 310 is clock, 211°216
is a recovery time control register, 212 and 217 are comparators, 2
13 is the upper 13 bits of the CPU's internal address bus,
215 and 218 are match signal lines.

As shown in FIG. 5, the recovery time control registers 211 and 216 store the clock number of the recovery time in the lower 3 bits and the input/output address in the upper 13 bits. 9 registers are set before accessing each peripheral device.

Next, the operation of this conventional example will be explained using the drawings.

In FIG. 2, when an input command or an output command is executed, the input/output bus cycle request signal line 304 becomes "1".
and requests the bus cycle control unit 301 to start an input/output bus cycle. If the bus cycle control unit 301 is in a state where it can start the bus cycle, it sets the input/output bus cycle start signal line 307 to "1" to start the input/output bus cycle. An input/output bus cycle is completed in two clocks, Tl and T2. During this time, the upper 13 bits of the input/output address are output to the internal address bus 213, and are compared with the upper 13 bits of the recovery time control register 211 set in advance by the comparator 212. If they match, the upper 13 bits of the input/output address are output to the recovery time control register 211 The value of the lower 3 bits and g of is output to the signal line 214. Similarly, the upper 13 bits of the recovery time control register 216 and the comparator 21
7, and if they match, the value of the lower three bits of the recovery time control register 216 is output to the signal line 214.

When the input/output bus cycle ends, the bus cycle control unit 301 sends an input/output bus cycle end signal line 308.
If there is a wait cycle insertion request from the READY signal line, the input/output bus cycle end signal line 308 becomes "1" with a corresponding delay.

When the input/output bus cycle end signal line 308 becomes "1", the contents of the signal line 214 are loaded into the counter 302;
Counter 302 starts counting. counter 302
is performing counting operation, the zero detection signal line 305
becomes “0”. The zero detection signal line 305 is input to the bus cycle control unit 301, and while the zero detection signal line 305 is "0", the input/output bus cycle request signal 304 is masked and the input/output hash cycle is started. do not have. Next, the counter finishes counting down and becomes “0” again.
When this happens, the zero detection signal line 305 becomes "1", permitting activation of the input/output bus cycle. Also, memory /
(The X cycle request signal line 303 is accepted and sets the memory bus cycle start signal line 306 to "1" whenever the bus is available, regardless of the recovery time of the I/O bus cycle. .

Next, a more specific explanation will be given using FIG. 7.

First, the recovery time control register 211 contains “101110”.
The data “1011001101” is stored in the recovery time control register 216, and the data “111100001111” is stored in the recovery time control register 216.
Next, when an input/output instruction is executed and the address "1111000011110XXX" is output as a 16-bit input/output address, the upper 13 bits of 216 and the upper 13 of the input/output address are stored. Since the bits match, comparator 2
The match signal line 218 of No. 17 becomes “1”, and the signal line 214
The lower 3 bits "110'" of 216 are output. When the input/output bus cycle end signal line 30g becomes "1", "110" is loaded into the counter 302 and 5 clocks are set as the recovery time. Although the lower three bits of the input/output address are ignored in this embodiment, the bit length of the input/output address to be compared can be freely determined by changing the register length of the recovery time control registers 211-216.

As described above, by setting the input/output address of a peripheral device and the recovery time for that peripheral device in the recovery time control register, it is possible to set the optimum recovery time for each peripheral device.

Although an example of setting recovery times for two sets of input/output addresses has been described here, by increasing the number of recovery time control registers and comparators, different recovery times can be set for even more input/output addresses.

〔Effect of the invention〕

In conventional microprocessors, the recovery time is set according to the device that requires the longest recovery time among the peripheral devices that can be normally connected, and therefore the recovery time is set according to the device that requires the longest recovery time among the peripheral devices that can be connected. More idols than necessary
If the clock is inserted, or because the number of idle clocks to be inserted is determined according to the maximum operating frequency of the CPU, more recovery time than necessary is inserted when using a low frequency clock. However, with the present invention, the recovery time from the end of a bus cycle caused by an I/O instruction to the start of a bus cycle caused by the next I/O instruction can be improved. It can be set to the optimal value for each peripheral device used, and performance can be improved without inserting unnecessary idle clocks. In particular, when used as an input/output-only processor such as an input/output processor, input/output instructions are used frequently and are more effective.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of Example 1, Figure 2 is Example 2.
Figure 3 is a diagram showing the configuration of a conventional example;
FIG. 4 is a drawing showing the timing of the conventional example, FIG. 5 is a drawing showing the configuration of the recovery time control register, and FIG. 6 is a drawing showing the embodiment 1.
FIG. 7 is a drawing showing the structure of the second embodiment. 300... Bus cycle request section, 301...
... Bus cycle control unit, 302 ... Down counter, 303 ... Memory bus cycle request signal line, 304 ... Input/output bus cycle request Signal line, 305... Zero detection signal line, 306... Memory bus cycle start signal line, 307... Input/output bus cycle start signal line, 308... ...I/O bus cycle end signal line, 309...READY signal line, 310...
...Clock, 111,211°216...
・Recovery time control register, 112, 212° 217...
...Comparator, 113,213...Address bus, 114,214...Recovery time transfer signal line, 115.215,218...Address match signal line . Agent Patent Attorney Susumu Uchihara Figure 3 3θδ Figure 4 Chrysanthemum

Claims (1)

[Claims] In a microprocessor having a function of inserting an idle clock between the end of an input/output bus cycle and the start of the next input/output bus cycle, a first storage means for storing an address of an input/output device; , a second storage means for storing the number of idle clocks to be inserted, a comparison means for comparing the address stored in the first storage means and the address of the input/output bus cycle, and an end of the input/output bus cycle. a counter for counting the number of clocks from the first storage means; and bus cycle control means for prohibiting the start of the next input/output bus cycle while the counter is in the counting operation, When the stored address matches the address of the input/output bus cycle, the number of idle clocks stored in the second storage means is transferred to the counter, and counting of the set number of counts ends. An input/output bus cycle control method characterized by deferring the start of an input/output bus cycle until the start of an input/output bus cycle.