JPH08202648A - Direct memory access transfer system and method - Google Patents

Abstract

PURPOSE: To provide a DMAC which can fast answer the transfer requests given from many channels without increasing the circuit scale. CONSTITUTION: This system/method includes a memory 13 which stores the information including transferer addresses, transfer destination addresses and the transfer frequency of respective plural channels, and a DMAC 12 which has a pair of internal registers that store the information including the transferer addresses, the transfer destination addresses and the transfer information and reads the corresponding information out of the memory 13 to set them into the internal registers when a direct memory access request is received from one of those channels to carry out a direct memory access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access transfer system and method for transferring data between multiple channels.

[0002]

2. Description of the Related Art Generally, a direct memory access controller for transferring data between a memory and an input / output device or between a memory and a memory without going through a CPU (hereinafter, direct memory access is called "DMA", direct memory access controller is called "DMAC"). Abbreviated) internally has a register for holding information of a transfer source address, a transfer destination address, and the number of transfers, and data is generated based on the contents of the internal register by a request signal from an external device or an instruction from the CPU. It was supposed to transfer.

Therefore, when a plurality of sets of data are transferred by this DMAC, a register for holding information of the transfer source address, the transfer destination address and the number of transfers is prepared by the number of sets, or one set is stored. It was necessary to share the register by rewriting the contents of the register of 1 by the CPU.

[0004]

However, the former method of preparing the registers for the number of sets causes a problem that the circuit scale of the DMAC becomes large.
Further, in the latter method of rewriting the contents of a set of registers by the CPU to share the registers, the DMAC
However, the rewriting of the register must be realized by software control of the CPU, and the time required to start data transfer becomes significantly longer than that of the former method. Further, since the load on the CPU also increases, there is a problem that the meaning of adopting the DMA for the purpose of reducing the load on the CPU and performing high-speed data processing is diminished in the first place.

The present invention has been made in view of the above situation, and an object thereof is to provide a direct memory access transfer capable of responding to a transfer request from a large number of channels at a high speed without increasing the circuit scale. A method and method are provided.

[0006]

Means for Solving the Problems That is, the present invention provides (1) an external memory for storing information including a transfer source address, a transfer destination address and a transfer count of each of a plurality of channels, a set of transfer source address, and a transfer It has an internal register that holds information including the destination address and the number of transfers, and when a direct memory access request is received from any of the plurality of channels, the corresponding information is read from the external memory and set in the internal register. And a direct memory access control circuit for executing direct memory access. (2) In the above item (1), when the direct memory access control circuit receives direct memory access requests from the plurality of channels at the same time, a priority order is set and one channel is selected to execute the direct memory access. It is something that is done.

[0007]

With the configuration as described in (1) above,
It is possible to execute data transfer in response to a transfer request from a large number of channels without increasing the circuit scale and without lowering the speed because software control from the CPU is not required.

By adopting the configuration of the above item (2), in addition to the operation of the above item (1), when the transfer requests from a plurality of channels are simultaneously received, it is necessary to consider the priority order thereof. It becomes possible to execute data transfer from the channel.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the circuit configuration, and 11 is a CP.
U and 12 are DMACs, 13 are memories, and 14a to 14g are first to seventh I / O devices.

CPU 11 and DMAC 12 and memory 13
The first to seventh I / O devices 14a to 14g are connected by, for example, a 24-bit width address signal bus a, a 16-bit width data signal bus b, and a control signal bus c, and a control signal bus c. Comprises a chip select signal CS, a read strobe signal RD and a write strobe signal WR.

Further, the first to seventh I / O devices 14a-
14g sends the DMA request signal DRE to the DMAC 12.
It sends out Q1 to DREQ7, and in response to this, D
From the MAC 12 to the first to seventh I / O devices 14a to 14
The DMA acceptance signals DACK1 to DACK7 are sent to g.

Further, the DMAC 12 sends a bus right release request signal BREQ (e) to the CPU 11, and in response to this, the CPU 11 sends a bus right release signal BACK (d) to the DMAC 12.

Next, FIG. 2 shows a detailed structure in the DMAC 12. As shown in the figure, the DMAC 12 has a base address upper register (“BAHR” in the figure).
21), a base address lower register (indicated by “BALR” in the figure) 22, a transfer source address register (indicated by “SAR” in the figure) 23, a transfer destination address register 24, and a transfer count register (indicated by “TCR” in the figure). 25 and a channel control register (in the figure, "CHC
Designated as "R") and has a register group of 26,
Count control unit 27, register control unit 28, start control unit 29
Also, a control unit group including the request priority control unit 30 and a bus interface 31 are provided.

The bus interface 31 is connected between the address signal bus a, the data signal bus b and the control signal bus c and the registers 21 to 26 constituting the register group, and is sent from the activation control section 29. Data is transmitted and received according to the incoming control signal.

The number-of-times control section 27 receives the contents held in the transfer count register 25 and receives the channel control register 26.
Set the channel number to. The register control unit 28 receives the control signal from the activation control unit 29 and receives each of the registers 21 to 21.
26 to control the write / read state.

The activation control unit 29 sends a bus right release request signal BREQ (e) to the CPU 11, and the bus right release signal BAC sent from the CPU 11 in response thereto.
It receives K (d) and controls the operation at the time of activation of the DMA. In addition to referring to the value held in the channel control register 26, it also transmits / receives a control signal to / from the request priority control unit 30.

The request priority control unit 30 internally has a priority register ("N" in the figure) for holding the number of a channel having a high priority.
o. 30a), and the DMA request signal D from the first to seventh I / O devices 14a to 14g.
Upon receiving REQ1 to DREQ7, and further referring to the value held in the channel control register 26, operation control is performed to determine a high priority channel by transmitting / receiving a control signal to / from the activation control unit 29. 1st to 7th
DMA acceptance signal DACK to the I / O devices 14a to 14g
1 to DACK7 are transmitted.

Among the registers 21 to 26 included in the DMAC 12, the base address upper register 21, the base address lower register 22 and the channel control register 26 can be written / read by the CPU 11 as shown in FIG. Shows each bit configuration.

That is, FIGS. 3A and 3B show the bit configurations of the base address upper register 21 and the base address lower register 22. The lower 8 bits of all 16 bits of the base address upper register 21 are used. The upper 8 bits of the start address of the indexed register, which will be described later, are stored in the memory 13 and the lower 16 bits of the start address of the indexed register are held by using all 16 bits of the base address lower register 22.

FIG. 3C shows the bit configuration of the channel control register 26. The upper 8 bits of all 16 bits are used for the memory 13 and the first to seventh bits.
End information T corresponding to the I / O devices 14a to 14g
E7 to TE0 are respectively used to hold transfer permission information DE7 to DE0 corresponding to the memory 13 and the first to seventh I / O devices 14a to 14g by using the lower 8 bits.

The indexed register is a set of data in which the source address SA indicating the transfer source address is 2 words, the destination address DA indicating the transfer destination address is 2 words, and the transfer count TC indicating the transfer count is 2 words. The transfer source address SA, the destination address DA, and the transfer count TC that are stored are prepared for each transfer channel.

In this embodiment, the transfer channel is 8 of the memory 13 and the first to seventh I / O devices 14a to 14g.
Therefore, the entire indexed register is composed of 6 [word] × 8 = 48 [word] (96 [byte]).

Now, the memory 13 and the first to seventh I / Os
The transfer channels corresponding to the O devices 14a to 14g are set to n (n
= 0 to 7), the transfer source address SA, the destination address DA and the transfer count TC corresponding to the transfer channel are SAn, DAn and T, respectively.
As represented by Cn, the head addresses of SAn, DAn, and TCn are defined by the following equation. That is, SAn = BA + 2 × n (1) DAn = BA + 2 × n + 2 (2) TCn = BA + 2 × n + 4 (3) FIG. 4 is a memory map of the indexed register described above. This indexed register is in a space on the memory 13 and has the other first to seventh I / Os.
It is necessary to set the base address BA so that it does not exist in the space of the O devices 14a to 14g.

For the sake of explanation, the priority of the transfer channel n (n = 0 to 7) corresponding to the memory 13 and the first to seventh I / O devices 14a to 14g is "0>1>2>...>". 7 "
Fixed.

Here, the transfer channel "0" is the memory 1
Used for data transfer from 3 to memory 13,
The other transfer channels "1" to "7" are assigned to the respective I / O devices 14a.
DMA request signals DREQ1 to DREQ7 from
While the transfer is started by asserting, the transfer is started when the transfer enable information DE0 of the channel control register 26 shown in FIG. 3C is set to "1" by the CPU 11. To do.

Next, the operation of the above embodiment will be described with reference to FIG. FIG. 5 shows a series of DMAs performed by the DMAC 12.
9 is a flowchart showing the processing contents of the operation. Initially, the indexed register in the memory 13, the base address upper register 21, the base address lower register 22, and the channel control register 26 are initialized (step S1).

Here, the indexed register defined by the base address upper register 21 and the base address lower register 22 as described above is the memory 1
It is necessary to set so that the contents of the indexed register are not rewritten due to the transfer of the transfer channel.

After the initial setting, it waits for a request for data transfer by DMA (step S2), and when the request occurs, the transfer permission information DEn of the channel control register 26 corresponding to the transfer request is "1". It is determined whether or not the condition that the transfer end information TEn is “0” is satisfied (step S3) is repeated.

Here, the data transfer request means the DMA request signal D from the first to seventh I / O devices 14a to 14g.
The case where REQ1 to DREQ7 are asserted or the case where the condition shown in the above step S3 is satisfied in the transfer channel "0" corresponding to the memory 13 is shown. DMA
A plurality of request signals DREQ1 to DREQ7 may be asserted at the same time.

When the DMA data transfer condition is satisfied and the request is recognized, the priority order is determined to handle a plurality of transfer requests (step S).
4). This is determined by the request priority control unit 30 according to the fixed priority order described above, and as a result, the channel number n for data transfer is determined by the priority register 30.
It is retained and set to a.

Further, in parallel with this processing, the activation control unit 2
9, the bus right release request signal BRE is sent to the CPU 11
When Q (e) is asserted and the bus release signal BACK (d) is asserted from the CPU 11 as a response, D
The MAC 12 gets the bus right.

Next, the activation controller 29 drives the register controller 28 and the bus interface 31 based on the base address BA of the indexed register determined by the contents of the base address upper register 21 and the base address lower register 22. Thus, the source address SAn, the destination address DAn, and the transfer count TCn according to the above equations (1) to (3) corresponding to the transfer channel number held in the priority register 30a of the request priority control unit 30 are transferred from the indexed register. Read, transfer source address register 23, transfer destination address register 24, and transfer count register 25, respectively
Are stored and held (step S5).

After that, it is confirmed that the content held in the transfer count register 25 is not "0" and that the data transfer of the set number of times has not been completed yet (step S
6), the activation control unit 29 drives the register control unit 28 and the bus interface 31, and the transfer source address register 2
In accordance with the address held in the memory 3, one word of data to be transferred is read from the corresponding address position of the memory 13 or the first to seventh I / O devices 14a to 14g, and the read data is stored in the transfer destination address register 24. The memory 13 or the first to the seventh according to the held address
The I / O devices 14a to 14g are written in the corresponding address positions (step S8).

After transferring one word of data in this manner, the count value of the transfer count register 25 is updated and set to "-1" to transfer the next data, and the transfer source address register 23 and the transfer destination address register 24 are set. The contents held in each are updated and set to "+1" (step S9), and the process from step S6 is repeated again.

In this way, the data transfer is executed by repeating the processing of steps S6, S8 and S9 the number of times set in the transfer count register 25 at the beginning.
When it is determined that the content held in the transfer count register 25 is "0" (step S6), it is determined that the data transfer is completed, and then the channel number n held in the priority register 30a is used. The transfer end information TEn of 26 is set to "1", the bus right is returned to the CPU 11 (step S7), and the DMA process is once ended.

In the above embodiment, the memory 13 and the first
It is described that the priority order of the seventh I / O devices 14a to 14g is fixed, but the priority order is not limited to this.
The priorities may be changed cyclically, or it is possible to count the number of times of waiting and give priority to the one having a constant count value over the others.

[0037]

As described above in detail, according to the present invention, the transfer rate from a large number of channels can be obtained without increasing the circuit scale and without requiring the software control from the CPU, so that the transfer speed is not lowered so much. It is possible to provide a direct memory access transfer method and method capable of executing data transfer in response to the request.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed circuit configuration in the direct memory access controller (DMAC) of FIG.

FIG. 3 is a diagram showing a partial register configuration of FIG.

FIG. 4 is a diagram showing a memory map of an indexed register provided in the memory of FIG.

FIG. 5 is a flowchart showing an operation content according to the embodiment.

[Explanation of symbols]

11 ... CPU 12 ... Direct memory access controller (DMA
C) 13 ... Memory 14a-14g ... I / O device 21 ... Base address upper register (BAHR) 22 ... Base address lower register (BALR) 23 ... Transfer source address register (SAR) 24 ... Transfer destination address register (DAR) 25 ... Transfer count register (TAR) 26 ... Channel control register (CHCR) 27 ... Number control unit 28 ... Register control unit 29 ... Startup control unit 30 ... Request priority control unit 30a ... Priority register (No.) 31 ... Bus interface

Claims (4)

[Claims] 1. A transfer source address of each of a plurality of channels,
It has an external memory that stores information including a transfer destination address and the number of transfers, and an internal register that holds information including a set of transfer source address, transfer destination address, and the number of transfers, from any of the above channels. And a direct memory access control circuit for reading the corresponding information from the external memory, setting the information in the internal register, and executing the direct memory access when the direct memory access request is received. method. 2. The direct memory access control circuit, when receiving direct memory access requests from the plurality of channels at the same time, sets a priority and selects one channel to execute the direct memory access. The direct memory access transfer method according to item 1. 3. A transfer source address of each of a plurality of channels,
Information including a transfer destination address and the number of times of transfer is stored in an external memory, and when a direct memory access request is received from any of the plurality of channels, the corresponding information is read from the external memory and a set of transfer source addresses is read. A direct memory access transfer method, wherein direct memory access is executed by setting in an internal register that holds information including a transfer destination address and the number of transfers. 4. When a direct memory access request is simultaneously received from the plurality of channels, a priority order is set to 1
4. The direct memory access transfer method according to claim 3, wherein one channel is selected and direct memory access is executed.