JP3752809B2 - Digital television receiving method and digital television receiving terminal device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention uses a digital television receiving method having a frame assembling apparatus that receives a fixed-length cell such as an ATM cell and assembles a variable-length frame on a main memory of the system by effectively using a common buffer, and the receiving method. The present invention relates to a digital television receiving terminal device.
[0002]
[Prior art]
In a frame assembling apparatus that receives a fixed-length cell such as an ATM cell and assembles a variable-length frame to be passed to an upper layer, there is a common buffer method as one of memory buffering methods for temporarily storing the fixed-length cell. In the common buffer method, when assembling frames with different connections, a buffer is not provided for each connection, but a buffer is shared by a plurality of connections.
[0003]
In the common buffer system, a memory such as a RAM for storing received fixed-length cells is logically divided into fixed-size buffers, and the start address of the divided buffer is set as an address indicating this buffer. There is a field for storing a pointer in the buffer, and this pointer indicates a buffer following the own buffer, thereby forming a necessary buffer string (in this specification, even when there is only one buffer, it may be referred to as a buffer string). is there).
[0004]
FIG. 11 is a diagram showing a conventional reception buffer management method disclosed in Japanese Patent Application Laid-Open No. 4-237238. 111-1 to 111-3 are empty reception buffers having a size (hereinafter referred to as “empty buffer”). 112-1 to 112-4 are empty buffers of size b (b <a). Reference numeral 113-1 denotes a reception buffer having a size b in which received packets are stored (hereinafter referred to as “received buffer”). Buffers 111-1 to 111-3, 112-1 to 112-4, and 113-1 are placed in a buffer unit 14 configured by a main memory or the like.
121 and 122 are empty buffer descriptors that store the pointers of the first empty buffer in the empty buffer string described later, and 123 is a received buffer descriptor that stores a pointer of the first empty buffer in the received buffer string described later.
[0005]
Next, the operation will be described. In FIG. 11, the free buffers 111-1 to 111-3 constitute a free buffer string (free buffer chain) for size a in which the free buffer 111-1 is the first buffer and the free buffer 111-3 is the final buffer. ing. The empty buffers 112-1 to 112-4 constitute a size b empty buffer sequence (empty buffer chain) in which the empty buffer 112-1 is the first buffer and the empty buffer 112-4 is the final buffer. .
[0006]
When a data packet of size L is received, the head 111-1 of the column of the empty buffer of size a is satisfied if a ≧ L> b, and the head buffer 112 of the column of the empty buffer of size b is satisfied if b ≧ L. -1 is removed from the corresponding empty buffer string, the next empty buffer 112-2 is the head of this empty buffer string, and fixed-length received data is sequentially stored in the buffer removed from the empty buffer string. . When all received data is stored in the buffer removed from the empty buffer string and a variable-length frame is assembled, the buffer is connected to the end of the received buffer string (received buffer chain), and the received packet storing process is completed.
[0007]
Although not described in the above conventional example, when the received buffer 113-1 is connected to the received buffer string, the upper layer management is performed in order to pass the variable length frame data of the received buffer 113-1 to the upper layer. Request the block to transfer data from the received buffer. Generally, the upper layer is managed by the CPU of the system, and data passed to the upper layer is transferred to the main memory of the system. The CPU requested to transfer data from the received buffer transfers the variable-length frame data in the received buffer 113-1 to the main memory of the system by DMA or the like. When the data transfer is completed, the received buffer 113-1 is removed from the received data buffer and returned to the empty buffer column again.
[0008]
[Problems to be solved by the invention]
In the conventional example, since the variable length frame is assembled in the common memory and then transferred to the upper layer, the buffer for receiving the fixed length cell such as an ATM cell and assembling the variable length frame is used as a buffer. Therefore, it is necessary to prepare a maximum length size of frame data that can be received so that all data of one variable length frame can be stored.
[0009]
Further, in the above-described conventional example, by providing a plurality of empty buffer columns having different sizes, there is an advantage that it is possible to prevent the received data having a small size from occupying a buffer having a large size and use the memory area effectively. The buffer of the maximum length of frame data that can still be received must be prepared.
Furthermore, since it is necessary to prepare a plurality of buffers corresponding to a plurality of connections that can be received at the same time, this has a problem that a burden is increased for a system that cannot afford a memory size.
[0010]
In addition, even if there is a buffer that can store the maximum length of data that can be received for the maximum number of connections that can be received simultaneously, the received data of the maximum number of simultaneous receptions that has the maximum reception data size can be stored. If received at the same time, all the empty buffers are removed from the empty buffer string, so there is no empty buffer remaining in the empty buffer string. At this time, when reception data of a plurality of connections is continuously received, a plurality of buffers are continuously received buffers, frame data is DMA-transferred from the received buffers to an upper layer, and the received buffers are again empty buffer strings. During the waiting time that occurs before switching to the vacant buffer, there will be no vacant buffer in the vacant buffer column, and if a new received cell is received continuously, there will be a problem that the data of this received cell is missed. .
[0011]
To solve this problem, it is sufficient to have more memory in the common memory than the maximum number of connections that can receive the maximum length of data that can be received at the same time. The burden is great for.
[0012]
In addition to the above-described conventional example, a method is conceived in which a large number of small reception buffers of a small size are chained and as many buffers as necessary are removed from the chain. This method also prevents small reception data from occupying a large reception buffer unnecessarily, and can effectively use the memory. However, as in the above-described conventional example, data is transferred to the upper layer after frame assembly is completed. Therefore, it is necessary to secure a total buffer size capable of storing all the data of the maximum length frame that can be received in the common memory.
[0013]
Further, when the buffer size is small and the data size of the frame assembled from the reception cell is large, the frame data is divided and stored in a plurality of buffers, and link information of the plurality of buffers is required. A memory area for storing the link information of the plurality of buffers is required, which increases the burden on a system that cannot afford a memory size.
[0014]
In a method of receiving a reception fixed-length cell, assembling a variable-length frame, and transferring variable-length frame data to a main memory of a system that is accessed by an upper layer, the frame assembly device does not use a local common memory. If the variable length frame is assembled using only the memory, the common memory becomes unnecessary and the memory can be saved.
However, in the above method, every time a received fixed-length cell is received, an overhead such as a data transfer request is generated in the main bus of the system. Therefore, a method of assembling a variable-length frame using only the main memory has the above overhead. Considering the main bus usage rate that is spent, it is not an appropriate method.
[0015]
The present invention has been made to solve the above-described problems, and is a small scale that efficiently uses a data buffer in a home digital television receiving terminal (STB) or the like that cannot afford a memory size. It is an object of the present invention to obtain a digital television reception method that realizes assembly of a reception variable length frame using a common memory and a main memory of a system, and a digital television reception terminal device using this reception method.
[0016]
[Means for Solving the Problems]
A receiving apparatus according to the present invention is a receiving apparatus that assembles frame data composed of cell data based on input cell data, the data buffer storing the cell data, and the data buffer Frame assembly means for controlling the storage of the cell data in the memory and the output of the cell data stored in the data buffer, storage means for storing the cell data output from the data buffer, and frame assembly means Control means for controlling the transfer of the cell data from the data buffer to the storage means according to the control, and the storage capacity of each data buffer in the plurality of data buffers is greater than the data size of the frame data Is also made small The frame assembly means stores means for storing the cell data in the data buffer based on predetermined information contained in the cell data, and means for outputting remaining amount end information indicating the end of the remaining amount of the data buffer. And means for outputting transfer information indicating that the cell data stored in the data buffer is output to the storage means according to the remaining amount end information, and the control means is responsive to the transfer information. After the cell data stored in the data buffer is transferred to the storage means, the frame data is assembled by transferring the cell data corresponding to the final data of the frame data to the storage means. The
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.
Embodiment 1 FIG.
FIG. 1 is a diagram showing a digital television receiving terminal apparatus according to Embodiment 1 of the present invention. In the figure, reference numeral 1 is a fixed-length receiving cell, 3 is a memory such as a RAM, which is logically divided into fixed-length buffers, for storing the received fixed-length cell 1 and assembling a variable-length frame 2 This is a common memory local to the frame assembling apparatus 12, which is composed of fixed-length data buffers 4 b to 4 f and an attribute information buffer 4 a to which attribute information of data stored in the data buffers 4 b to 4 f is written.
[0027]
Reference numeral 12 denotes a frame assembling apparatus, and reference numeral 5 denotes a reception fixed-length cell attribute management unit, which detects various attributes of the reception fixed-length cell and notifies that the reception fixed-length cell 1 has been received, Output the connection information 5d of the fixed length cell 1, the length information 5a for notifying the length of the variable length frame 2 assembled from the reception fixed length cell 1, and the start cell information 5c or the end cell information 5b of the reception fixed length cell 1. To do. A memory read control unit 6 receives a read address pointer 6c of the common memory 3 to be read from a DMA controller 15 (to be described later) and reads the read address data 6a and the read control in order to read data of the common memory 3 from a CPU 13 (to be described later). The pulse 6b is output.
[0028]
A memory write control unit 7 outputs address data 7a and a write control pulse 7b for writing data to the common memory 3. An empty buffer management unit 8 receives transfer end information 13a from a CPU 13 (to be described later) and empty buffer usage information 10d from an assembly frame management unit 10 (to be described later), and manages the empty buffers of the data buffers 4b to 4f. Information 8a is output.
[0029]
Reference numeral 10 denotes an assembly frame management unit which receives length information 5a, end cell information 5b, start cell information 5c, connection information 5d, cell reception notification 5e from the reception fixed length cell attribute management unit 5, and free buffer information 8a from the free buffer management unit 8. And the buffer remaining amount end information 11a from the assembly buffer management unit 11 described later, manages the frame length of the variable length frame 2 being assembled, and stores the received fixed length cell 1 in the address pointer of the common memory 3 10a, the attribute information 10b to be written to the attribute information buffer 4a of the common memory 3, and the remaining buffer capacity of the data buffers 4b to 4f of the common memory 3 when the assembly of the variable length frame 2 is completed or during the assembly of the variable length frame 2 The data end information 10c and the received data stored in an unused empty buffer And outputs the be free buffer usage information 10d.
[0030]
Reference numeral 11 denotes an assembly buffer management unit that manages the remaining buffer capacity of the data buffers 4b to 4f that are assembling the variable length frame 2, and outputs the remaining buffer end information 11a when the remaining buffer capacity is exhausted. A transfer buffer management unit 9 receives the buffer end information 11a, and transfers a data transfer request 9a for requesting the CPU 13 to transfer the data buffers 4b to 4f and the attribute information buffer 4a data to the main memory 14, and data to be transferred. The transfer buffer attribute information 9b indicating the attribute of the data stored in the buffers 4b to 4f is output to the CPU 13.
[0031]
A system CPU 13 receives the transfer request 9a and the transfer buffer attribute information 9b from the transfer buffer management unit 9 of the frame assembling apparatus 12, and transfers the variable-length frame data 2 from the common memory 3 according to the transfer buffer attribute information 9b. It has a function of managing DMA assembly completion of variable length frames on the main memory 14 by DMA transfer to the main memory 14. Reference numeral 15 denotes a DMA controller which is started when the CPU 13 DMA-transfers data from the common memory 3 to the main memory 14. Reference numeral 18 denotes a system main bus. The main memory 14, the CPU 13, the DMA controller 15, and the frame assembly apparatus 12 are the main bus 18. Send and receive data to and from each other.
[0032]
FIG. 2 is a diagram showing the configuration of the data buffer 4b and the attribute information buffer 4a. For one data buffer 4b, there is one attribute information buffer 4a in which attribute information of received data stored in the data buffer 4b is displayed. The data buffer 4b stores the received data of the fixed-length cell 1, the size of the data buffer 4b is the same as or larger than the data size of the fixed-length cell 1, and the variable-length frame assembled from the received fixed-length cell 1 The data size is equal to or smaller than the data size of 2.
[0033]
For example, in ATM communication, the data buffer 4b is 48 bytes or more. Attribute information 10b output from the assembly frame management unit 10 shown in FIG. 1 is written in the attribute information buffer 4a. The attribute information 10b includes connection information 4a-1, frame length information 4a-2, frame end information 4a-3, and the like. The connection information 4a-1 is an area for displaying the connection of the reception fixed length cell 1 stored in the data buffer 4b, and the frame length information 4a-2 is the byte length of the variable length frame 2 assembled by the data buffer 4b and the main memory 14. The display area, frame end information 4a-3 is an area for displaying frame end information when the end data of the variable length frame 2 assembled with the data of the reception fixed length cell 1 is stored in the data buffer 4b.
[0034]
3 to 7 show that when the reception fixed-length cells 1a to 1h are stored in the data buffers 4b to 4f of the common memory 13, and the data buffers 4b to 4f are filled, the data stored in the data buffers 4b to 4f is main. It is the figure which showed an example of a mode that it was transferred to the memory. Reception fixed length cells 1a, 1d, and 1e are the same connection, 1b and 1f are the same connection, 1g and 1h are the same connection cells, reception fixed length cells 1a, 1b, 1c, and 1g are start cells, and 1e is an end cell. It is. For example, the reception fixed-length cells 1a, 1d, and 1e of the same connection have 1a as a start cell and 1e as an end cell, and one variable-length frame 14a is assembled with the data of the three reception fixed-length cells 1a, 1d, and 1e. It is done.
[0035]
Operation Example 1
Next, an operation example 1 of the first embodiment will be described.
First, when the frame assembling apparatus 12 receives the reception fixed length cell 1, the reception fixed length cell attribute management unit 5 is the connection of the reception fixed length cell 1, and the reception fixed length cell 1 is the start cell of the variable length frame 2. Or the end cell, and the data length (data length) of the variable-length frame 2 assembled from the data of the reception fixed-length cell 1 shown in the reception fixed-length cell 1 is detected, and the cell reception notification 5e, connection information 5d, start The cell information 5c, end cell information 5b, and length information 5a are output to the assembly frame management unit 10.
[0036]
When the reception of the start cell of the variable length frame 2 is notified by the cell reception notification 5e and the start cell information 5c, the assembly frame management unit 10 refers to the empty buffer information 8a output by the empty buffer management unit 8 and One empty data buffer is selected from the data buffer row of the common memory 3 managed by the assembling apparatus 12, and this data buffer is registered as a data buffer for the frame of the connection notified by the connection information 5d. The address pointer 10a is output to the memory write control unit 7.
[0037]
The memory write controller 7 notified of the address pointer 10a outputs the address data 7a and the write control pulse 7b, and stores the data of the reception fixed length cell 1 in the data buffer 4b.
FIG. 3 shows how received fixed-length cells 1a, 1b, and 1c, which are start cells of different connections, are stored in empty buffers 4b, 4c, and 4d, respectively.
[0038]
Next, when the frame assembling apparatus 12 receives the reception fixed length cell 1 that is neither the start cell nor the end cell, the assembly frame management unit 10 refers to the connection information 5 d notified from the reception fixed length cell attribute management unit 5. In order to select the data buffer 4b in which previously received data of the same connection has already been stored and store the received data following the already stored data in the data buffer 4b, the address pointer 10a following the data buffer 4b is set. Output.
FIG. 4 shows how the received fixed-length cell 1d is stored in the data buffer 4b in which cell data of the same connection is already stored.
[0039]
If multiple reception fixed-length cells 1 of the same connection are stored in the data buffer 4b, and the data buffer 4b is filled with the reception data before reception of the end cell, that is, before completion of assembly of the variable-length frame 2, the data buffer 4b Is transferred to the main memory 14 as divided data of the variable length frame 2. The remaining amount of the data buffer 4b is managed by the assembly buffer management unit 11, and when the buffer of the data buffer 4b runs out, the remaining buffer end information 11a is notified from the assembly buffer management unit 11 to the assembly frame management unit 10. The
[0040]
When the buffer remaining amount end information 11a is received, the assembly frame management unit 10 outputs the address pointer 10a for writing the attribute information 10b of the data stored in the data buffer 4b and the attribute information 10b to the attribute information buffer 4a. The transfer buffer management unit 9 is notified of data end information 10c indicating that data storage in 4b has ended. When the data end information 10c is received, the transfer buffer management section 9 indicates information such as a transfer request 9a for requesting data transfer to the main memory 14, and an address pointer and connection of the data buffer 4b in which the data to be transferred is stored. The CPU 13 is notified of the transfer buffer attribute information 9b.
[0041]
When the transfer request 9a is received, the CPU 13 refers to the transfer buffer attribute information 9b to activate the DMA controller 15, and the DMA controller 15 transfers data from the common memory 3 to the main memory 14. At this time, the CPU 13 refers to the attribute information 4a-1 to 4a-3 and recognizes the attribute of the data stored in the data buffer 4b. In the above case, the CPU 13 refers to the frame end information 4a-3 to recognize that the transfer data does not include the end data of the variable length frame 2, and the transfer data is the divided data of the variable length frame as the main memory 14 Stored in FIG. 5 shows how data is transferred to the main memory 14 after the data buffer 4b is filled with data.
[0042]
As described above, when the end data of the variable length frame 2 is not included in the transfer data, the data of the reception fixed length cell 1 having the same connection as the transfer data received next by the frame assembling apparatus 12 is transferred. Is stored in the empty data buffer that is newly selected by the frame assembly management unit 10 with reference to the empty buffer information 8a.
FIG. 5 shows a state in which the received fixed-length cell 1e, which is a data cell following the data stored in the transferred data buffer 4b, is stored in the empty data buffer 4e.
[0043]
When the reception fixed length cell 1 is an end cell, reception of one variable length frame 2 is completed upon reception of the reception fixed length cell 1. When the frame assembling apparatus 12 receives the end cell, the reception fixed length cell attribute management unit 5 notifies the frame assembly management unit 10 of the end cell information 5c. When the end cell information 5c is received, the frame assembly management unit 10 stores the data of the reception fixed length cell 1 in the data buffer, and then notifies the transfer buffer management unit 9 of the data end information 10c indicating the end of reception of the variable length frame 2. . When the data end information 10c is received, the transfer buffer management unit 9 notifies the CPU 13 of a transfer request 9a for requesting data transfer and transfer buffer attribute information 9b.
[0044]
The CPU 13 refers to the connection information of the transfer data indicated in the transfer buffer attribute information 9b, and in the data string that has already been transferred to the main memory 14, the end data of the variable length frame with the same connection as the connection information is stored. When there is divided frame data not included, the data in the data buffer 4b is recognized as data subsequent to the divided frame data, and the DMA controller 15 is activated to perform DMA transfer to the main memory 14.
FIG. 6 shows how the received fixed-length cell 1 as an end cell is stored in the data buffer 4e and then transferred to the main memory 14.
[0045]
When the DMA transfer of data to the main memory 14 is completed, the CPU 13 notifies the transfer end information 13a to the empty buffer management unit 8, and the empty buffer management unit 8 sets the data buffer 4b in which the transfer data is stored as an empty buffer again. recognize. The next received data can be stored in the data buffer 4b which has become an empty buffer again. 6 and 7 show a state in which the buffer 4b to which data is transferred in FIG. 5 becomes an empty buffer again after the transfer is completed, and each data of the received fixed-length cells 1g and 1h to be subsequently received is stored. .
[0046]
Each time the CPU 13 receives the transfer request 9a, it transfers the data of the variable-length frame 2 divided into the size of the data buffer from the common memory 3 to the main memory 14 and receives the connection information of the data received from the frame assembly device 12 The assembly of the variable length frame 2 is completed on the main memory 14 with reference to the length information. The CPU 13 passes the data of the variable-length frame 2 that has been assembled to the upper layer, and the series of frame reception processing ends.
6 and 7 show that the data 14a of the reception fixed length cell 1a, 1d stored in the data buffer 4b and the data of the reception fixed length cell 1e stored in the data buffer 4e are transferred to the main memory 14. This shows how the variable length frame 2a is assembled.
[0047]
Next, the contents of control in which the CPU receives the data transfer request 9a and performs data transfer will be described with reference to the flowchart showing the control contents of the CPU when performing data transfer in FIG.
When the CPU 13 receives the data transfer request 9a from the frame assembling apparatus 12 (s1), it receives the transfer buffer attribute information 9b notified from the frame assembling apparatus 12 (s2), and the CPU 13 receives the common memory indicated by the transfer buffer attribute information 9b. The address of the main memory to which data is to be transferred and the size of the data to be transferred are calculated from the address pointer and transfer data connection information (s3).
[0048]
The CPU 13 sets the address pointer of the common memory 3, the address pointer of the main memory 14 and the size of data to be transferred to the DMA controller 15 (s 4), activates the DMA controller (s 5), and connects the common memory 3 and the main memory. Data DMA transfer is performed (s6). When the DMA transfer ends, the DMA controller 15 notifies the CPU of the end of the DMA transfer (s7), and the CPU 13 notifies the frame assembly device 12 of the data transfer end information 13a. Further, when the CPU 13 recognizes that the transfer data includes the frame end data by referring to the frame end information 4a-3 stored in the attribute information buffer 4a of the common memory 3 (s8), the variable length frame Data reception is notified to an upper layer that performs data processing of data (s9).
[0049]
As described above, as a procedure for assembling the variable-length frame 2 from the reception fixed-length cell 1, first, a plurality of variable-length frames are received by the data buffer 4b of the common memory 3 managed by the frame assembling apparatus 12 for each reception fixed-length cell data size. The divided variable-length frame data are DMA-transferred to the main memory of the system, and the assembly of the variable-length frame is completed in the main memory by repeating a plurality of DMA transfers. Therefore, when the size of the data buffer 4b is shorter than the data length of the variable length frame, it is not necessary to store all the data of one variable length frame in the common memory 3 when assembling the variable length frame.
[0050]
In addition, the area of the common memory 3 in which the transfer data is stored every time when the DMA transfer of the divided data 2 of the variable length frame to the main memory 14 is completed can be reused for storing the next received fixed length cell data. . Further, when the size of the data buffer 4b is equal to or larger than 2 reception fixed length cell size, the data in the common memory 3 is compared with the case where the data is transferred to the main memory every time the reception fixed length cell 1 is received. Since a plurality of received fixed-length cell data are collected in the buffer 4b and then transferred to the main memory 14, the overhead required for the DMA transfer procedure that occupies the main bus of the system can be reduced.
[0051]
Example of operation 2.
The data size of the reception variable-length frame that is mainly received by the system differs depending on the type of system and the type of data that is mainly received depending on what communication is performed and what data is mainly received. In this operation example 2, the CPU 13 manages the size of the data buffer size 4b in the common memory 3, and the size of the data buffer 4b is set according to the data size of the variable-length frame received mainly by the system. Set or change as desired.
[0052]
The CPU 13 calculates the optimum size for the data buffer 4b from information such as the expected value of the data length of the received frame and the memory size of the common memory 3, and sets the data buffer size in the frame assembling device 12. The assembly buffer management unit 11 of the frame assembly device 12 stores the received data having the set data size in the data buffer 4b storing the reception fixed-length cell 1 being received, and then stores the remaining buffer capacity in the assembly frame management unit 10. The end information 11a is notified. Subsequent operations are the same as those in the first operation example.
[0053]
For example, when the data size of a variable-length frame that is mainly received is small, the data buffer 4b is wasted by setting the data buffer size to a small size equivalent to the data size of the variable-length frame that is mainly received. It is available without.
Further, even in a system where the size of the common memory 3 is small, if the size of the data buffer 4b is set small, it can be used as a common memory for assembling variable length frames of a plurality of connections received simultaneously.
In a system in which the size of the common memory 3 can be increased, if the size of the data buffer is set to the maximum data size of a variable-length frame that can be received, one DMA transfer from the common memory 3 to the main memory 14 is performed. Thus, all data of one variable length frame can be transferred.
[0054]
In this operation example 2, the RAM constituting the common memory 3 can also be used as a memory for other functions such as a graphics function in the system, and is shared by a plurality of functions and a certain part is shared. It can be considered to be used as the memory 3. In such a case, the size allocated to the common memory 3 may be changed during operation in relation to the memory size required for other functions. If the size of the data buffer 4b existing in the common memory 3 can be arbitrarily changed, even if the size of the common memory 3 is changed during operation, the operation can be performed without reducing the number of reception connections.
[0055]
Operation Example 3
This operation example 3 is a case where there are a plurality of data buffer sizes set by the CPU 13 in the system of the above operation example 2.
The CPU 13 determines a plurality of sizes of the data buffer 4b from information such as the expected value of the data length of the received frame and the memory size of the common memory 3, and sets the data buffer 4b in the frame assembling device 12. When the assembly frame management unit 10 of the frame assembly device 12 receives the fixed-length cell 1, the assembly frame management unit 10 selects a data buffer from a plurality of sizes set by the CPU 13 in accordance with the size of the reception variable-length frame 2 assembled from the fixed-length cell data. Select the optimal data buffer size and store the received data. The assembly buffer management unit 11 notifies the assembly frame management unit 10 of the buffer remaining amount end information 11a when the received data having the data size set in each is stored in the data buffer 4b. Subsequent operations are the same as those in the first operation example.
[0056]
According to this operation example 3, by preparing a plurality of optimum buffer sizes based on the size of the variable-length frame that can be received and the number of connections, a small frame is stored in a small data buffer, and a large frame is stored in a large size. The size of the common memory 3 can be reduced while reducing the number of DAM transfers.
[0057]
Operation Example 4
This operation example 4 is a case where the CPU 13 can set the number of data buffers 4b in the system of the operation example 1.
The CPU 13 determines the number of data buffers 4 b in the common memory 3 from information such as the memory size of the common memory 3 and the maximum number of connections to be received, and sets the number of buffers in the empty buffer management unit 8 of the frame assembly device 12. The empty buffer management unit 8 creates empty buffer information 8 a according to the number of buffers set by the CPU 13 and notifies the assembly frame management unit 10 of the empty buffer information 8 a. Subsequent operations are the same as those in the first operation example.
[0058]
After the transfer of received data from the data buffer 4b of the common memory 3 to the main memory 14, the CPU 13 does not notify the empty buffer management unit 9 of the transfer end information 13a, so that the data buffer 4b in which the transfer data is stored is stored. It is also possible to use the memory area of the data buffer 4b as a memory area for other functions, for example, without returning to the empty buffer. Thus, the number of data buffers 4b can be adjusted by not making the transferred data buffer 4b empty.
[0059]
According to this operation example 4, by controlling the number of data buffers 4b in the common memory 3, it is possible to secure the minimum number of buffers required according to the status of received traffic. The size can be adjusted according to the situation. Further, when a certain area of the RAM constituting the common memory 3 is used by, for example, another function, the area of the common memory 3 is set to 1 when the memory size used by the other function is expected to increase. The control of removing the data buffer from the common memory area, using it for other functions, and returning to the common memory 3 area when this memory area becomes unnecessary for other functions can be easily realized.
[0060]
Example of operation 5.
In the above operation example 1, when one data buffer 4b of the common memory 3 is filled with the received data, the transfer request 9a is output. However, in this operation example 5, the transfer request is made until a plurality of data buffers 4b are filled with the received data. 9a is not output.
The same operation as in the operation example 1 is performed until the assembly frame management unit 10 of the frame assembly device 12 notifies the transfer buffer management unit 9 of the data end information 10c. After receiving the data end information 10c, the transfer buffer management unit 9 does not output the transfer request 9a until an arbitrary number of the data end information 10c is received or until a certain time elapses. When the above conditions are satisfied, the transfer buffer management unit 9 outputs a transfer request 9 a to the CPU 13. The transfer buffer attribute information 9b indicates the attributes of all data buffers waiting for transfer, and notifies the CPU 13 of the attributes. Subsequent operations are the same as those in the first operation example.
[0061]
According to the fifth operation example, the number of DMA transfers can be reduced by collecting the data in the plurality of data buffers 4b and outputting the transfer request 9a, thereby reducing the overhead associated with the DMA transfer.
[0062]
Embodiment 2. FIG.
In the first embodiment, the CPU 13 DMA-transfers the divided data of the variable length frame assembled in the data buffer 4b of the common memory 3 to the main memory 14 of the system, and the assembly of the variable length frame is completed in the main memory 14. However, according to the second embodiment, the divided data of the variable length frame assembled by the fixed length data buffer 4b of the common memory 3 with the frame assembly device 12 serving as the bus master of the main bus of the system is used as the main memory of the system. The variable length frame 10 is completed on the main memory 14, and the variable length frame data that has been assembled is passed to the upper layer.
[0063]
FIG. 9 is a diagram showing a digital television receiving terminal apparatus according to the second embodiment. The same reference numerals as those in FIG. 1 denote the same or corresponding parts. In the figure, reference numeral 16 denotes a bus master unit. When a transfer request 9a and transfer buffer attribute information 9b are received from the transfer buffer management unit 9, a bus request 16a for becoming the bus master of the main bus 18 of the system is output. And transfer data from the common memory 3 to the main memory 14. A bus arbitration unit 17 receives a bus request 16 a from the bus master unit 16, performs bus arbitration for determining the bus master of the main bus of the system, and returns a bus master permission signal 17 a to the bus master unit 16.
[0064]
Operation Example 1
Next, an operation example 1 of the second embodiment will be described. The frame assembling apparatus 12 receives the reception fixed-length cell 1 and assembles the divided data of the variable-length frame with the fixed-length data buffer 4b of the common memory 3, and the transfer buffer management unit 9 transfers the transfer request 9a and the transfer buffer attribute information 9b. The operation up to outputting is the same as in the first embodiment.
[0065]
The transfer request 9a and the transfer buffer attribute information 9b are output to the bus master unit 16 in the frame assembling apparatus 12, and the bus master unit 16 receiving the transfer request 9a and the transfer buffer attribute information 9b is connected to the main bus 18 of the system. In order to become a bus master for transferring data to the main memory 14, a bus request 16 a is output to the bus arbitration unit 17. The bus arbitration unit 17 receives a bus request from each block that becomes the bus master of the main bus 18 of the system, and determines a block to which the right of the bus master is given according to the bus master priority.
[0066]
When the bus master right is given to the bus master unit 16 of the frame assembling apparatus 12, a bus master permission signal 17a is notified to the bus master unit 16. When the bus master permission signal 17a is received, the bus master unit 16 refers to the transfer buffer attribute information 9b, outputs the address pointer of the common memory 3 to the memory read control unit 6, and has a variable length from the data buffer 4b of the common memory 3. Read the divided data 2 of the frame. The variable-length frame data 2 is output to the system main bus 18, and the bus master unit 16 outputs the write address 16 b of the main memory 14 to the main bus 8 in synchronization with the output timing of the variable-length frame data 2 from the common memory 3. Then, the variable-length frame division data 2 read from the common memory 3 is written into the main memory 14.
[0067]
When the data transfer is completed, the bus master unit 16 relinquishes the right of the bus master. Each time the bus master unit 16 receives the transfer request 9 a, the variable-length frame division data 2 is transferred from the common memory 3 to the main memory 14 while referring to the transfer buffer attribute information 9 b as described above. Complete long frame assembly. When the assembly of the variable length frame 2 is completed, the bus master unit 16 sends the variable length frame assembly information indicating information such as the address pointer of the main memory 13, the connection of the variable length frame, the length of the variable length frame to the CPU 13 which is the upper layer. 16d is notified.
[0068]
As described above, as a procedure for assembling the variable-length frame 2 from the reception fixed-length cell 1, first, a plurality of variable-length frames are received by the data buffer 4b of the common memory 3 managed by the frame assembling apparatus 12 for each reception fixed-length cell data size. Then, the frame assembly device 12 becomes the bus master and transfers the divided data of the variable length frame to the main memory 14 in the order of reception, so that the main memory 14 completes the assembly of the variable length frame. Therefore, it is not necessary to store all data of one variable length frame in the common memory 3 when assembling the variable length frame.
[0069]
Further, every time transfer of the divided data 2 of the variable length frame to the main memory 14 is completed, the area of the common memory 3 in which the transfer data is stored can be reused for storing the next received fixed length cell data.
Furthermore, compared with the case where data is transferred to the main memory every time one cell of the reception fixed length cell 1 is received, a plurality of reception fixed length cell data are transferred to the main memory 14 after being collected in the common memory. The overhead required for the transfer procedure that occupies the main bus can be reduced.
[0070]
Further, since the frame assembly device 12 manages the assembly information and completes the assembly of the variable length frame on the main memory 14, the load on the CPU 13 is reduced as compared with the first embodiment in which the CPU 13 is engaged in the assembly of the variable length frame. The
Further, when the DMA controller 15 transfers data, both the access to the common memory 3 and the access to the main memory 14 use the main bus, so that it is impossible to access both at the same time. After the data is read, the read data is written to the main memory 14, but when the frame assembling device 12 becomes a bus master, the access to the common memory 3 is performed on the bus local to the frame assembling device 12. The data in the common memory 3 can be read and written to the main memory 14 at the same time, and the time for occupying the main bus 18 is shortened compared to the DMA transfer.
[0071]
Embodiment 3 FIG.
In the first embodiment, when the variable-length frame 2 is received and the transfer request 9a is output from the frame assembling device 12, the CPU 13 activates the DMA controller 15 to transfer data from the common memory 3 to the main memory 14. However, if the data transfer start is delayed or the data transfer speed is slow due to the slow processing speed of the CPU 13 or other processing, the next transfer request is generated before the data transfer is completed. There may be multiple waiting data buffers.
In the third embodiment, when a plurality of data buffers waiting to be transferred are generated, the frame assembly device 12 transfers the data buffers waiting for transfer in the order in which the transfer requests are generated. Controls the output of attribute information 9b.
[0072]
FIG. 10 is a block diagram showing a digital television receiving terminal apparatus according to the third embodiment. The same reference numerals as those in FIG. 1 denote the same or corresponding parts, respectively. In the figure, reference numeral 19 denotes a transfer waiting management unit. As described above, when a plurality of data buffers waiting for transfer are generated, the transfer requests 9a and 19a are transferred in order to transfer the data buffers waiting for transfer in the order in which transfer requests are generated. The transfer data attribute information 9b for each transfer data buffer is managed. 19a is a transfer request notified by the transfer waiting management unit 19 to the CPU 13, 19b is transfer buffer attribute information, and 13b is transfer start information notified to the frame assembling apparatus 12 when the CPU 13 receiving the transfer request 19a starts DMA transfer. is there.
[0073]
Operation Example 1
Next, an operation example 1 of the third embodiment will be described. Whether the frame assembling apparatus 12 receives the reception fixed length cell 1 and stores the reception data in the data buffer 4b of the common memory 3, and whether the data buffer 4b is filled with the reception data or receives the end data of the variable length frame Then, the operation contents described in the first embodiment are the same until the assembly frame management unit 10 outputs the transfer request 9a.
[0074]
The transfer request management unit 19 receives the transfer request 9 a and the transfer buffer attribute information 9 b output from the assembly frame management unit 10. The transfer wait manager 19 writes the transfer request 9a and the transfer buffer attribute information 9b in a FIFO memory configured using a register controlled by the transfer wait manager 19. The CPU 13 is notified of the transfer request 19a and the transfer attribute information 19b which are the read data of the FIFO. In response to the transfer request 19a, the CPU 13 activates the DMA transfer, and notifies the transfer start management unit 19 of the frame assembling apparatus 12 of the transfer start information 13b.
[0075]
When the transfer start information 13b is received, the transfer waiting management unit 19 discards the transfer request data at the head of the FIFO and reads out the next transfer request data. At this time, if two or more transfer requests 9a are written in the FIFO, then the transfer request 19a is output to the CPU 13, but if only one transfer request 9a is written in the FIFO, At the time when the first data of the FIFO is discarded, the transfer request 19a to the CPU 13 stops. In synchronization with the transfer request 19a, the transfer buffer attribute information 19b is also sequentially output to the CPU 13 via the FIFO. The operation after the CPU 13 that has received the transfer request 19a starts the DMA transfer is the same as the operation of the first embodiment.
[0076]
Since the operation is performed as described above, the previous data transfer is performed after the frame assembly apparatus 12 outputs the transfer request 9a until the next transfer request 9a is generated due to a slow processing speed of the system. Even if a situation occurs such that the transfer request 9a and the transfer buffer attribute information 9b are not lost until the transfer start information 13b is received from the CPU 13, the transfer request is not lost. The data in the data buffer 4b can be DMA-transferred to the main memory 14 in the order in which the above occurred.
For this reason, when other functions need to use the main bus 18 frequently, data transfer from the common memory to the main memory can be made to wait, and the main bus can be effectively used as a whole system. become.
[0077]
Example of operation 2.
In this operation example 2, the FIFO memory for storing the transfer request 9 a and the transfer buffer attribute information 9 b in the transfer waiting management unit 19 is configured by using one area of the RAM constituting the common memory 3.
[0078]
According to this operation example 2, in a system in which a large number of transfer-waiting data buffers are expected to be generated, it is burdensome to hold the transfer buffer attribute information 9b with a plurality of sets of registers, but the RAM constituting the common memory 3 Is only a small size. In a system in which the frame assembling apparatus 12 cannot have many registers, a large number of registers can be expected to be reduced by using the RAM area.
[0079]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0080]
A common memory consisting of a small-sized data buffer array for storing received fixed-length cell data is provided. Every time one data buffer is filled with received data, the data stored in the data buffer is stored in the system main memory. Transfer, and repeating the data transfer from the data buffer to the main memory a plurality of times to complete the assembly of the variable length frame on the main memory, so when assembling the variable length frame, Since it is not necessary to store all the data in the common memory, the size of the common memory can be reduced.
In addition, each time the DMA transfer of the variable length frame divided data to the upper layer is completed, the data buffer area of the common memory in which the transfer data is stored can be reused for storing the next received fixed length cell data. Since the data buffer other than the data buffer storing data can be handled as an empty buffer, the common memory can be used more effectively, and the size of the common memory can be reduced.
Also, by transferring a plurality of received fixed-length cell data in a common memory to the main memory of the system, the overhead that occupies the main bus of the system can be reduced, and the processing capacity of the entire system can be increased. is there.
[0081]
In addition, the common memory can be used more effectively, and the size of the common memory can be reduced. In addition, since the load on the CPU can be reduced, the processing capacity of the CPU related to the entire system can be increased. Furthermore, the time for occupying the main bus of the system can be shortened, and the processing capacity of the entire system can be increased.
[0082]
In addition, the common memory can be reduced to an optimum size for the system.
[0083]
Further, efficient use of the common memory can be realized, and the common memory can be reduced.
[0084]
In addition, the common memory can be reduced to an optimum size for the system.
[0085]
In addition, overhead required for a DMA transfer request from the common memory to the main memory can be reduced, and the main bus can be used efficiently.
[0086]
Also, the overhead required for bus master arbitration for data transfer from the common memory to the main memory can be reduced, and the main bus can be used efficiently.
[0087]
In addition, after waiting for a time when the main bus is not used for other functions, data can be transferred from the common memory to the main memory, and the system main bus can be used effectively.
[0088]
In addition, data can be transferred from the common memory to the main memory after waiting until the main bus is not used for other blocks, and the main bus can be used effectively.
Further, the number of registers in the frame assembly device can be reduced.
[0089]
In addition, since the reception variable length frame can be assembled using the common memory and the main bus efficiently, even if only a small common memory is mounted, the processing capacity of the entire system does not deteriorate.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a digital television receiving terminal apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a diagram illustrating a configuration of a buffer existing in a common memory of the frame assembling apparatus according to the first embodiment.
3 is a diagram showing an example of how received data is stored in a data buffer existing in a common memory of the frame assembling apparatus of Embodiment 1. FIG.
4 is a diagram showing an example of how received data is stored in a data buffer existing in a common memory of the frame assembling apparatus of Embodiment 1. FIG.
FIG. 5 is a diagram showing an example of how received data is stored in a data buffer existing in a common memory of the frame assembling apparatus according to the first embodiment;
6 is a diagram showing an example of how received data is stored in a data buffer existing in a common memory of the frame assembling apparatus of Embodiment 1. FIG.
7 is a diagram showing an example of how received data is stored in a data buffer existing in a common memory of the frame assembling apparatus of Embodiment 1. FIG.
FIG. 8 is a flowchart illustrating control contents of a CPU that performs data transfer in the first embodiment.
FIG. 9 is a block diagram showing a digital television receiving terminal device according to a second embodiment of the present invention.
FIG. 10 is a block diagram showing a digital television receiving terminal apparatus according to Embodiment 3 of the present invention.
FIG. 11 is a diagram illustrating a reception buffer management method of a conventional frame assembling apparatus.
[Explanation of symbols]
1, 1a to 1h Receive fixed length cell, 2, 2a Variable length frame data, 3 Common memory, 4a Attribute information buffer, 4a-1 Connection information, 4a-2 Frame length information, 4a-3 Frame end information, 4b to 4f Data buffer, 5 reception fixed length cell attribute management unit, 5a length information, 5b end cell information, 5c start cell information, 5d connection information, 5e cell reception notification, 6 memory read control unit, 6a read address data, 6b read control pulse, 6c read address pointer, 7 memory write control unit, 7a write address data, 7b write control pulse, 8 free buffer management unit, 8a free buffer information, 9 transfer buffer management unit, 9a transfer request, 9b transfer buffer attribute information, 10 assembly Frame management unit, 10a add Les pointer, 10b attribute information, 10c data end information, 10d free buffer usage information, 11 assembly buffer management unit, 11a buffer remaining amount end information, 12 frame assembly device, 13 CPU, 13a transfer end information, 13b transfer start information, 14 Main memory, 14a-14b Variable length frame intermediate data, 15 DMA controller, 16 Bus master unit, 16a Bus request, 16b Write address, 16d Variable length frame assembly information, 17 Bus arbitration unit, 17a Bus master enable signal, 18 System main Bus, 111-1 to 111-3 Free buffer (size a), 112-1 to 112-4 Free buffer (size b), 121 to 122 Free buffer descriptor, 123 Received buffer descriptor.

Claims (8)

A receiving device that assembles frame data composed of the cell data based on the input cell data,
A plurality of data buffers for storing the cell data;
Frame assembly means for controlling the storage of the cell data in the data buffer and the output of the cell data stored in the data buffer;
Storage means for storing the cell data output from the data buffer;
Control means for controlling transfer of the cell data from the data buffer to the storage means in accordance with the control of the frame assembling means;
The storage capacity of each data buffer in the plurality of data buffers is configured to be smaller than the data size of the frame data ,
The frame assembling means is
Means for storing the cell data in the data buffer based on predetermined information contained in the cell data;
Means for outputting remaining amount end information indicating the end of the remaining amount of the data buffer;
Means for outputting transfer information indicating that the cell data stored in the data buffer is output to the storage means according to the remaining amount end information;
The control means transfers the cell data corresponding to the final data of the frame data to the storage means after transferring the cell data stored in the data buffer to the storage means according to the transfer information. A receiving apparatus configured to assemble the frame data by: 2. The receiving apparatus according to claim 1 , wherein the frame assembly means serves as a bus master in accordance with the transfer information to transfer the cell data. 3. The receiving apparatus according to claim 1, wherein the control unit is configured to change a storage capacity of the data buffer according to a data size of the frame data. In accordance with the data size of the frame data and the storage capacity of the storage means configured to include the data buffer, the control means includes the storage capacity of one data buffer and other data in the plurality of data buffers. receiving apparatus according to claim 1 or 2 is configured comprising to set such that the storage capacity and different storage capacity of the buffer. The said control means is comprised so that the number of the said data buffers may be set according to the size of the memory | storage means comprised including the said data buffer, and the number of the connections to which the said cell data are transmitted. The receiving apparatus according to 1 or 2 . 2. The receiving apparatus according to claim 1 , wherein the frame assembling unit is configured to output the transfer information when a predetermined number of remaining data buffers in the plurality of data buffers are completed. The frame assembling means is configured to become the bus master in accordance with the transfer information output when a predetermined number of the data buffers of the plurality of data buffers have ended. Item 3. The receiving device according to Item 2 . Further comprising transfer waiting management means for managing the transfer information,
The control means receives the transfer information indicating that cell data stored in one data buffer of the plurality of data buffers is transferred to the transfer waiting management means, and then transfers the one data buffer. Other transfer information indicating that cell data stored in another data buffer is to be transferred is input to the transfer waiting management means until the transfer of the cell data stored in the memory to the storage means is completed. If it is, in the order in which the forwarding information is generated, the receiving apparatus according to claim 1 configured to transfer the cell data corresponding to the transfer information.

Images