JPH02310649A - Reception frame transfer system and communication controller - Google Patents

Abstract

PURPOSE:To successively continue normal communication control even if it comes to a state where a data part is insufficient by storing the header part of a reception frame and the data part in reception buffer groups which are provided for plural sets by means of dividing them. CONSTITUTION:The length of the header part of the frame to be received is stored in the reception buffer length 803 of a buffer control register 81 and the maximum length of the data part in the buffer length of a register 82 as a condition before the transfer of the reception frame. When a DMA controller 2 receives a DMA start request from a frame reception circuit in a DMA stop state, it decides the free conditions of the buffer group 61. When the free buffer does not exist, a DMA action is terminated by assuming it to be the occurrence of the overrun of the reception buffer. When there is the free buffer, a descripter read pointer 802 is updated and the reception frame is DMA transferred to the free buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a data receiving device that, upon receiving a frame from a line, performs I) MA( Direct memory access) The control device automatically transfers the received frame to an empty buffer.
The present invention relates to a reception frame A transfer method for MA transfer and a communication control device using this transfer method.

[Conventional technology]

Conventionally, DM received frames from one communication line to main memory
As described in Japanese Unexamined Patent Publication No. 50-181862, the A transfer method includes a buffer specification queue for storing information specifying a reception buffer on the main storage device, and a queue management for managing this queue. There is a method in which a device is provided, information specifying an empty buffer is written in the queue, and when a DMA transfer request occurs, the empty buffer information is read from the queue by DMA control control and DMA transfer is automatically started.

This method sets buffer information in the DMA control device when a DMA transfer request occurs without the intervention of the main control device, so it has the advantage of shortening the time until DMA activation and being able to support high-speed lines. However, since the content of the received frame is not considered, the received frame t
It was necessary to prepare a receive buffer of a size that matched the maximum length of 1. Therefore, the above-mentioned reception buffer had to be applied also to the reception of short frames consisting only of the header portion.

[Problem to be solved by the invention]

Since the above-described conventional method does not take into account the contents of the frame to be received, it is necessary to receive an information frame including a data portion and a control frame not including a data portion using the same receiving buffer group.

Therefore, for example, if the empty receive buffer runs out as a result of continuously receiving information frames that contain data parts that cannot be released immediately, it becomes impossible to receive control frames that do not contain data parts. However, no consideration was given to the fact that normal flow control would no longer be possible.

In addition, when applying the above conventional method to a hierarchical communication control device, the communication control device only refers to the header part in the received frame as a processing target, so the header part and the data part are the same. In the above-mentioned method of storing information in a reception buffer, no consideration was given to the fact that the processing speed would be reduced if the reception buffer was a memory that could not be accessed quickly from the main controller.

SUMMARY OF THE INVENTION An object of the present invention is to provide a receive frame transfer method that allows reception of the header portion of a frame even when the receive buffer is busy.

Another object of the present invention is to provide a receiving and receiving frame transfer system that can speed up the processing of the header portion of a received frame.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a receiving buffer group and a means for accumulating information specifying an empty buffer in the buffer group. The DMA control device divides the received 11 frames into a header part and a data part and stores them in the empty buffers of each of the receive buffer groups based on the empty buffer information. .

In order to achieve the other objects mentioned above, one aspect of the present invention is to store a receive buffer group for storing a header portion of a received frame among a plurality of sets of receive buffer groups in a main memory that can be accessed at high speed from a main controller. A group of buffers provided on the device for storing data portions is provided in a separate storage device that is accessible from the host device.

More specific embodiments of the present invention include, for example.

These include:

That is, a frame receiving circuit for receiving frames sent from the 1 communication line 101, a main storage device for storing the received frames, and a DMA control device for transferring the received frames to the main storage device. and a main controller that processes received frames stored in the main storage device.
A receive frame transfer method in which a control device transfers a previous received frame to the main storage device, a first buffer group for storing a header part in the received frame;
a second group of buffers for storing data portions in the received frames; a first group of discretors for storing information specifying empty buffers in the first buffer group; 1) a second disk libter group for storing information specifying an empty buffer in the second buffer group on the main storage device; Start receiving 1
) When an M A transfer request is generated, the empty buffer information regarding the first buffer group is read from the first discriminator group, the header part of the received frame is transferred to the empty buffer by DMA, and the received If the frame includes a data portion, the empty buffer information regarding the second buffer group is read from the second discriminator group, and the data portion is DMA-transferred to the empty buffer.

〔　〕

Next, the operation of the present invention will be explained.

1) The MA control device first sends the header part of the received frame to the first
If a data portion still exists, the data portion is DMA-transferred to a second reception buffer group.

By doing this, even if frames containing data portions are continuously received and the second buffer group for storing the data portions runs out of space.

In this state, only the header part of the control frame consisting of the header part and the information frame including the data part can be received, so normal flow control can be continued between the communication control devices connected by one line. becomes 01 Noh. At this time, in the present invention, it is necessary that the number of buffers in the first buffer group be greater than the number of buffers in the second buffer group.

Furthermore, by providing the first buffer group for storing the header part on another storage device that can be accessed at high speed by the main controller, it is possible to improve the processing speed for the header part of the received frame. Embodiment] An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a communication control device to which an embodiment of the present invention is applied.

In the figure, [ is the main control device, 2 is the DMA control device, 23 is the main storage device, 4 is the frame receiving circuit, 5 is the communication line, 61
7 is a first buffer group including a plurality of buffers for storing the header portion of the received frame; 62 is a second buffer group including a plurality of buffers for storing the data portion of the received frame; ] is a first disk librator group in which one or more disk libters containing information specifying an empty buffer in the first buffer group 61 is chained by a pointer, and 72 is a second buffer group 6
A second disk libter group 81 in which one or more disk libters containing information specifying an empty buffer in 2 is chained by a pointer, 81 manages the first disk libter group 71 and the first buffer group 61. The first buffer management register 82 is a second buffer management register for storing information for managing the second discriminator group 72 and the second buffer group 62.

FIG. 2 is a diagram showing the contents of the first buffer management register 81 and the second buffer management register 82.

In the figure, 801 is the first disc ribtor group 71 or the second
a disc libter write pointer pointing to the position of the last disc libta in the disc libta group 72, 802;
is a disc libter successive pointer that points to the position of the first disc libta in the first disc libta group 71 or the second disc libta group 72; One of these is the receive buffer length, which indicates the size of the buffer.

In the above configuration, the DMA control device 2 transfers the received frame to the first buffer on the main storage device 3 in response to a DMA activation request generated when the frame receiving circuit 4 receives the frame from the communication S line 5. DMA transfer is performed to group 61 and second buffer group 62. Details of this operation in Part 3N5! The operation of the control device 2 will be explained according to the flowchart of the control device 2.

First, as a condition before transferring a received frame, the length of the header part of the frame to be received is set in the receive buffer length 803 of the first buffer management register 81, and the length of the header part of the received frame is set as the receive buffer length 80:3 of the second buffer management register 82. stores the maximum length of the data part of each received frame,
It is necessary that the number of buffers in the first receiving buffer group 61 is greater than the number of buffers in the second receiving buffer group 62.

When the DMA control device 2 receives a DMA activation request from the frame receiving circuit 4 in the DMA stopped state, it determines whether or not there is an empty buffer in the first buffer group 61. This determination is made by comparing the value of the disc libter write pointer 801 and the value of the disc libta read pointer 802 in the first buffer management register 81,
When both values become -L'ffi, the first buffer group 6
It is determined that there is no empty buffer in 1 (step 30
1).

If it is determined through this determination that there is no empty buffer in the first buffer group 61, it is determined that a reception buffer overrun has occurred, and the main controller 1 is notified by an interrupt or the like.
The DMA operation ends (step 302).

In step 301, if it is determined that there is an empty buffer in the first buffer group 61, the 7 of the disc libter read pointer 802 in the first buffer management register 81
Empty buffer information is retrieved from the pointed disc libter, and the disc libter read pointer 802 is updated to point to the next disc libter of the disc libter it points to (step 303), and the received frame is DMA to empty buffer
Transfer (step 304). If the received frame is large enough to be transferred in its entirety by the step controller 304, that is, if it is a control frame consisting only of a header section, 1) the M A operation is terminated (step 305). ).

Further, if the data portion of the frame continues, it is determined whether or not there is an empty buffer in the second buffer group 62. This determination is made by comparing the value of the disc libta write pointer 801 and the value of the disc libta continuation pointer 802 in the second buffer management register 82, and when the two values match, the second buffer It is determined that there is no empty buffer in group 62 (step 306).
.

In this determination, if it is determined that there is no empty buffer in the second reception buffer group 62, the remaining part of the reception frame is completely read and then the DMA operation is ended (step 307).

If it is determined in step 306 that there is an empty buffer in the second buffer group 62, it is indicated that the data portion continues to the second buffer group 62 in the descriptor that includes the information specifying the empty buffer used in step 304. Writes information (step 308) and writes the disc libter successive pointer 8 in the second buffer management register 82.
The empty buffer information is retrieved from the disc libter pointed to by 02, and the disc libter continuation pointer 802 is updated to point to the next disc libta of the disc libta pointed to by it (step 309), and the remaining part of the received frame, That is, the data portion is transferred by DMA to the empty buffer obtained in step 309 (
step 310).

If the length of the data part of the frame being received is shorter than the receive buffer length 803 in the second buffer management register 82 and fits into one empty buffer, it is sent to D M as is.
A: If the data does not fit in one empty buffer, all remaining data is discarded and the maximum received frame length is stored in the disc libter containing the information specifying the empty buffer used in step 304. Information indicating that an overflow has occurred is written, and the DMA operation is ended (step 312).

The above is a real example of DMA control! This is the second action.

On the other hand, the main controller 1 controls the distributor groups 7L and 72 including information specifying buffers in which received frames are stored in the first buffer group 61 and the second buffer group 62.
This main control device 1, which has means for storing the position of the first disc libter of The contents of the buffer in which the header part of the received frame is stored are analyzed, and when the processing is completed, the buffer targeted for processing is written after the disc libter pointed to by the disc libta write pointer 801 in the first buffer management register 81. , and releases an empty buffer in the first buffer group 61 by connecting a disc libter including information specifying the disc libter and rewriting the value of the disc libta write pointer 801 to a value pointing to the connected disc libta. There is a main continuation data part in the header part of the frame, and the second buffer group 62
After processing the buffer containing said data part of
After the disc libta pointed to by the disc libta write pointer 801 in the second buffer management register 82, a disc libta that includes information specifying the buffer to be processed is connected, and the value of the disc libta write pointer 801 is changed. Empty buffers in the second buffer group 62 are released by rewriting the value to point to the connected disc libter.

As described above, in this embodiment, the header part and the data part of a received frame are divided and stored in separate buffer groups, so that when there is a shortage of data part storage buffers due to continuous reception of information frames including the data part, etc. Even if the buffer is busy, it is possible to continue receiving only the header portions of control frames and information frames.

Next, a second embodiment of the present invention will be described using FIG. 4.

In the figure, 9 is an information processing device, 10 is a communication control device that is connected to the information processing device and provides a communication control function, and 11 is a communication device for receiving the data part of a received frame between the information processing device 9 and the communication control device 10. The shared memory for the transfer and other parts are the same as those indicated by the same numbers in FIG.

In the data receiving device in this embodiment, the header part of the received frame is processed by the communication control bag filo to control the communication protocol, etc., and the data part is stored in the shared memory 1.
1 to the information processing device 9 for processing.

The shared memory 11 has a larger storage capacity than the main storage device 3, and depending on the scale of the main control device 1 used, appropriate preprocessing may be required to refer to the shared memory 11. Therefore, if the conventional method that does not perform frame division is applied to the received frame transfer in this device, since the receive buffer is usually provided on the shared memory 11, the header part of the received frame will also be stored on the shared memory 11. Therefore, when the main control device 1 processes the header portion, a problem arises in that the processing speed decreases.

When the present invention is applied to this device, the first buffer group 61
, and the first and second disc libter groups 71 and 72 are provided on the main storage device 3, and only the second buffer group 62 is provided on the shared memory 11, so that the DMA control device 2 follows the flowchart in FIG. By operating, the header part of the received frame is stored in a storage area that can be accessed quickly by the main controller, and the data part is directly stored in the shared memory 1.
1 and can be transferred to the information processing device 9.

As described above, by dividing a received frame into a header portion and a data portion and storing the header portion in a memory area that can be accessed at high speed, 1. The processing time for the header portion can be shortened.

〔Effect of the invention〕

According to the present invention, since the header part and the data part of a received frame can be divided and stored in a plurality of reception buffer groups, even if the reception buffer is in a busy state where there is a shortage of buffers for the data part, It is possible to continue receiving the control phase frame and only the header part of the information frame, which has the effect of allowing normal communication control to continue.

Furthermore, since only the receive buffer for the header portion is used when receiving the control frame, there is an effect that the use efficiency of the receive buffer memory is improved.

Furthermore, by separately providing a reception buffer for the header portion on a memory that can be accessed at high speed, there is an effect of improving the processing speed for the header portion.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data receiving device of a communication control device to which the first embodiment of the present invention is applied, and FIG.
3 is a flowchart showing an overview of the operation of the DMA control device of FIG. 1, and FIG. 4 is an explanatory diagram showing the detailed contents of the buffer management register shown in FIG. FIG. 2 is a block diagram showing the configuration of a data receiving device. 1... Main control device, 2... DMA control device, 3...
・Main memory device, 4...Frame receiving circuit, 5...Communication line. 9... Information axis processing device, 10... Communication control device, 11
...Shared memory, 61.62...Buffer group, 71
゜72...Distributor group, 81.82...Buffer management register. Collection 2 Illustration 3 Illustration

Claims (1)

[Scope of Claims] 1. A reception frame transfer method in a data reception device in which a reception frame from a communication line is transferred to a main storage device and stored by a DMA control device, comprising a reception buffer group and a buffer group of the reception buffer group. a plurality of sets of means for accumulating information specifying empty buffers in the DM, one for the header part and the other for the data part of the received frame;
The A control device is characterized in that it is configured to divide a received frame into a header part and a data part based on the empty buffer information, and store the divided parts into the empty buffers of each of the receiving buffer groups. Received frame transfer method. 2. A frame receiving circuit for receiving frames sent from a communication line, a main storage device for storing the received frames, and a DMA control device for transferring the received frames to the main storage device. , and a main control device that processes received frames stored in the main storage device, the communication control device comprising a main control device that processes received frames stored in the main storage device, means for accumulating information specifying a receive buffer group and an empty buffer in the buffer group. A plurality of sets are provided for the header part and the data part of the received frame, and the DM
The A control device is characterized in that it is configured to divide a received frame into a header part and a data part based on the empty buffer information, and store the divided parts into the empty buffers of each of the receiving buffer groups. Communication control device. 3. The received frame according to claim 1, wherein, among the buffer group, those used for the header portion are provided on the main storage device, and those used for the data portion are provided on a storage device different from the main storage. Transfer method or claim 2
The communication control device described.