JPH0831877B2 - Packet switch - Google Patents

Description

TECHNICAL FIELD The present invention relates to a packet switch used for a packet switch or the like.

[Prior Art] As a conventional packet switch, there is a bus matrix switch.

FIG. 9 shows the structure of the bus matrix switch. The input packet transmitted through the lines 101 to 10n is subjected to predetermined processing by the input packet processing devices 301 to 30n. With this processing, the output packet processing devices 311 to 3
A header designating 1n is added and sent to the row-direction buses 201 to 20n. The crosspoint element (XE) 411 is located at the intersection of the row-direction buses 201 to 20n and the column-direction buses 211 to 21n.
~ 4nn are provided. Crosspoint element 4ij
Captures only the packet having the header destination j, that is, the packet destined for the output packet processing device 31j, and temporarily stores the packet in the buffer 400 in FIG.

When the packet is accumulated, the crosspoint element 4ij issues a bus use request for packet transmission to the column direction bus 21j. This use request is detected and controlled by the bus control circuits 321 to 32n for each column direction bus, and
The transmission right is given to the one crosspoint element 4ij, and the packet is transmitted.

FIG. 10 shows the structure of the crosspoint element 4ij. The header of the packet data input from the row-direction bus 20i is monitored by the control circuit 401, and only the data heading for the column-direction bus 21j is captured in the buffer 400. The buffer 400 outputs data in the order of input,
It is a so-called FIFO. The column bus 21j is the data bus 21j
-1 and a control bus 21j-2, the former transmits packets, and the latter transmits control signals such as request and permission.

[Problems to be Solved by the Invention] In the above-described conventional bus matrix switch, in order to realize an n × n switch having n inputs and n outputs, n ² cross points are required. Requires an element. Therefore, as n increases, the number of crosspoint elements remarkably increases, which has a drawback of impairing economic efficiency.

This invention was made under such a background,
The purpose is to economically construct a high-speed and large-capacity packet switch.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a plurality of input circuits connected to each of a plurality of packet-multiplexed input lines having different speeds, and the plurality of inputs. A first selection circuit for selecting any one of the circuits, a plurality of output circuits connected to each of the plurality of packet-multiplexed output lines, and any one of the plurality of output circuits. A second selection circuit for selection, a memory commonly used by the plurality of input circuits and the plurality of output circuits, and control means for controlling the memory, the plurality of input circuits and the plurality of output circuits Respectively have a first-in first-out memory, the memory has a plurality of buffers, and the packet data from the plurality of input lines are stored in the first input circuits of the corresponding input circuits. After being temporarily stored in an in-first-out memory, the first selection circuit controlled by the control means reads out from one of the first-in first-out memories of the input circuit and stores the memory. Of the output circuit specified in the second selection circuit and stored in the buffer of the output circuit designated by the second selection circuit. After being temporarily stored in the output circuit, it is transmitted from an output line corresponding to the output circuit.

[Operation] According to the above configuration, the packet data from the plurality of input lines are transferred to the corresponding first input first circuit.
Once stored in the first-out memory, the first-in, first-out
It is read from the memory and stored in the buffer of the memory. Further, under the control of the control means, the packet data is read from the buffer of the memory, temporarily stored in the first-in first-out memory of the designated output circuit, and then sent out from the output line corresponding to the output circuit. It

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a packet switch according to the first embodiment of the present invention. The input data from the n number of packet-multiplexed input lines 1101 to 110n are supplied to the input circuits 1201 to 120n. The outputs of the input circuits 1201 to 120n are supplied to the selection circuit 1301. Selection circuit 1301
Selects one circuit from the n input circuits 1201 to 120n. The data of the selected input circuit 120i is
It is written in the memory 1300 composed of RAM.

On the other hand, the packet data in the memory 1300 is stored in the selection circuit 13
Output line 1211 in which n packets are multiplexed via 02.
To 121n and sent to the output lines 1111 to 111n. As shown in FIG. 2, the memory 1300 has k buffers of length m, and the address in the memory 1300 is determined by the buffer number and the in-buffer address.

An address control circuit 1400 is also connected to the memory 1300. To the address control circuit 1400, n registers 1411 to 141n, a queue 1420, and a counter 1430 are connected.

Here, the registers 1411 to 141n have the configuration shown in FIG. That is, the registers 1411 to 141n correspond to the n input / output lines 1101 to 110n and 1111 to 111n, respectively, and manage the input side and the output side separately. That is, the registers 1411 to 141n are connected to the input lines 1101 to 11n.
The line status, the buffer number, and the in-buffer address are stored for each 0n, and the line status, the buffer number, the in-buffer address, and the buffer number of a packet waiting to be sent are stored for each of the output lines 1111 to 111n.

The queue 1420 is a queue that manages an empty buffer. The counter 1430 counts and divides the clock 1120 and causes the address control circuit 1400 to count addresses.

 Next, the operation of this embodiment will be described.

(1) Writing operation of the memory 1300.

The input data is sent to the address control circuit 1400 via the input circuit 120i / selection circuit 1301.

The address control circuit 1400 monitors the header of the input data and determines the presence / absence of a packet and the destination.

When the beginning of the packet is received, register 14 of the corresponding line
The input line status of 1i is set to "receiving".

The empty buffer is read from the queue 1420 and the buffer assigned to the packet is captured.

When the head of the packet is received, the address in the buffer is set to 0, and the address in the buffer is determined by this and the buffer number.

Write packet data to the buffer.

At the same time, the address in the buffer is incremented by "1" and written in the register 141i of the corresponding line together with the buffer number.

The destination of the packet is read from the header, and the buffer number of the captured buffer is written in the area of the register 141j corresponding to the destination output line 111j that stores the packet waiting for transmission.

During packet reception, the buffer number and the in-buffer address are read from the register 141i, the write address of the memory 1300 is determined, and the data is written to this address. Also, the address in the buffer is incremented and the register 141i
Write in.

When the end of the packet is received, the data is written to the memory 1300 and the line status of the register 141i is set to "idle".

When the packet receiving operation is completed in this way, the packet sending operation is started.

(2) Read operation of the memory 1300.

At the start of packet transmission, the address control circuit 1400
Reads the register 141j of the corresponding line and searches for a packet waiting to be sent. If there is a packet waiting to be sent, the data is read from the memory address designated by the buffer number and the in-buffer address 0.

This data is sent to the output circuit 121j via the selection circuit 1302 and sent from the output line 111j.

The address in the buffer is incremented by "1". Also, the output side line state of the register 141j is set to "transmitting", and the buffer number is written.

During packet transmission, the address control circuit 1400
Read on to the output side line status of 141j. Then, if the data is being sent, the data is read from the memory address indicated by the buffer number and the address in the buffer stored in the register 141j, and this data is sent to the output circuit 121j via the selection circuit 1302. , From the output line 111j.

At the same time, the address in the buffer is incremented and the register 141j
To memorize.

When sending the end of the packet, send data in the same way as. This buffer number is then queued to release the buffer used to send the packet.
Write to 20.

The write and read operations to the memory 1300 described above are
As shown in FIG. 4, writing and reading are performed alternately. FIG. 4 shows the case where the number of lines is 2, and the sequence is as follows: writing of line 1 → reading of line 1 → writing of line 2 → reading of line 2. Even when the number of lines is n, the data of lines 1 to n are similarly time-divisionally performed.

By the operation described above, a packet switch using the RAM as a buffer can be configured. This buffer is
It can be commonly used by the n input / output lines 1101 to 110n and 1111 to 111n.

In the first embodiment described above, the case where one packet is stored in one buffer has been described, but it is also possible to store one long packet by using n buffers. Further, if serial-parallel conversion and parallel-serial conversion are performed by the input / output circuits 1201 to 120n and 1211 to 121n, writing and reading to and from the memory can be performed in m-bit parallel.

FIG. 5 is a block diagram showing the structure of a packet switch according to the second embodiment of the present invention.

This packet switch differs from the packet switch shown in FIG. 1 in the following points.

A point in which a first-in first-out memory (hereinafter referred to as a FIFO) for speed conversion is added to the input circuits 1201 to 120n and the output circuits 1211 to 121n.

Between the input circuits 1201 to 120n and the address control circuit 1400,
A signal line 20 for displaying whether or not data can be transmitted / received between the output circuits 1211 to 121n and the address control circuit 1400.
Addition of 01-200n and 2011-201n.

FIG. 6 shows the operation of the second embodiment.
In this figure, the input line 1 and the input line 2 have different transmission rates, and the former is slower than the latter. Then, writing to the memory 1300 is alternately performed on the input lines 1 and 2, and its cycle is equal to the input cycle of the line 2 on the high speed side. Therefore, in the case of the line 1 on the low speed side, invalid access may occur, such as between 2B and 2C in FIG. 6 (C). This is the data 1C that should be written when accessing
This is because there is no

Therefore, the address control circuit 1400 needs to recognize whether or not the data to be written in the memory 1300 has arrived at the FIFOs of the input circuits 1201 to 120n. Signal line 2001-200n
Is for this. That is, the address control circuit 1400 checks whether or not data has arrived through the signal lines 2001 to 200n, and if the data has arrived, writes the data in the memory 1300 as in the first embodiment. On the other hand, if the data has not arrived, neither writing to the memory 1300 nor updating the register 141j is performed.

The same applies to the reading side. That is, the output circuit 121j
Whether the FIFO can receive data depends on the signal line 2011 to 201n.
Is transmitted to the address control circuit 1400. As a result, the address control circuit 1400 determines whether or not the data should be read from the memory 1300 and transferred to the output circuits 1211 to 121n. That is, if the FIFOs of the output circuits 1211 to 121n are empty and data can be transferred, the data is read from the memory 1300 in the same manner as in the first embodiment, and if the data cannot be transferred, the data read operation from the memory 1300 is performed. And register
141j is not updated.

The following relationship is required between the writing / reading speed V0 to / from the memory 1300 and the data speed Vi (i = 1, 2 ..., N) of the input / output line.

V0 ≧ n × max (Vi) According to the second embodiment described above, packets can be exchanged on lines with different speeds. That is, the packet switch can be economically configured without using the speed conversion device.

FIG. 7 is a block diagram showing the structure of a packet switch according to the third embodiment of the present invention. The third embodiment is characterized in that the access to the memory 1300 is dynamically assigned to each line. For this purpose, a priority determination circuit 1431 that detects a processing request from the input circuits 1201 to 120n and performs priority determination is inserted between the input circuits 1201 to 120n and the address control circuit 1400, and the output circuits 1211 to A priority determination circuit 1432 that detects a processing request from the output circuits 1211 to 121n and performs priority determination is inserted between the 121n and the address control circuit 1400.

The input circuits 1201 to 120n and the output circuits 1211 to 12
Having a FIFO in 1n is the same as in the second embodiment.

FIG. 8 shows the access timing to the memory 1300 in the third embodiment. As shown in this figure, writing to the memory 1300 is sequentially performed in the order in which the input occurs. Note that the writing / reading speed V0 to the memory 1300 and the data speed Vi (i = 1,2 ...
The following relation is required between the ... and n).

V0 ≧ V1 + V2 + ... + Vn According to the third embodiment, not only the packets can be exchanged between the lines having different speeds, but also there is no invalid access to the memory 1300 as in the second embodiment. Can be reduced, or if the access speed is the same, a higher speed line can be accommodated.

[Effects of the Invention] As described above, according to the present invention, data of a plurality of lines is written into and read from one memory, so that a large-capacity packet switch can be economically constructed.

Since the input / output circuit is provided with the first-in first-out memory, packets can be exchanged between the lines having different speeds.

Furthermore, a first priority determination circuit that detects processing requests from a plurality of input circuits and controls the writing order to the buffer,
Since the second priority determination circuit for detecting the processing request from the plurality of output circuits and controlling the reading order from the buffer is provided, the access to the memory can be dynamically assigned. For this reason, not only is it possible to exchange packets on lines with different speeds, but it is also possible to access the memory extremely efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of the first embodiment of the present invention, FIG. 2 is a conceptual diagram showing the relationship between the structure of the buffer in the memory 1300 of the embodiment and the memory address, and FIG. 3 is the same embodiment. FIG. 4 is a conceptual diagram showing the configuration of the registers 1411 to 141n of the example, FIG. 4 is a time chart for explaining the operation of the same embodiment, and FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention.
FIG. 6 is a time chart for explaining the operation of the same embodiment, FIG. 7 is a block diagram showing the configuration of the third embodiment of the present invention, and FIG. 8 is a time chart for explaining the operation of the same embodiment. A chart, FIG. 9 is a block diagram showing a configuration of a conventional bus matrix switch, and FIG. 10 is a block diagram showing a configuration of a crosspoint element used in the bus matrix switch. 1101 to 110n …… input line, 1110… 111n …… output line, 1201 to 120n …… input circuit, 1211 to 121n …… output circuit, 1300 …… memory, 1431 …… first priority judgment circuit, 1432 …… Second priority determination circuit, 2001-200n ... first signal line, 2011-201n ... second signal line.

Front page continuation (72) Inventor Naoaki Yamanaka 3-9-11 Midoricho, Musashino City, Tokyo Inside Nippon Telegraph and Telephone Corporation, Communication Network 1st Laboratory (72) Inventor Mune Sakakibara 3-9-11 Midoricho, Musashino City, Tokyo No. 54 (Reference) JP-A-57-192151 (JP, A) ISS84session32Cpaper 2 "ASYCHRONOUS TIME-DIVISION TECHNIQUE MATERNON EXPERIMENTATION CONTINUE CONTINUE CONTINUE CONTINUE CONTINK LOGIN CONTINKING NETWORK LOGIN WORKING" ． et al

Claims (2)

[Claims] 1. A plurality of input circuits connected to each of a plurality of packet-multiplexed input lines having different speeds, and a first selection circuit for selecting any one of the plurality of input circuits. A plurality of output circuits connected to each of the plurality of packet-multiplexed output lines, a second selection circuit that selects one of the plurality of output circuits, the plurality of input circuits, and the plurality of output circuits And a control means for controlling the memory, wherein the plurality of input circuits and the plurality of output circuits each have a first-in first-out memory, and the memory is , Having a plurality of buffers, the packet data from the plurality of input lines, once accumulated in the first-in first-out memory of the corresponding input circuit, The first selection circuit controlled by the control means reads out from one of the first-in first-out memories of the input circuit and accumulates in the buffer of the memory. Repeated every time, further read from the buffer of the memory, once stored in the first-in first-out memory of the output circuit designated by the second selection circuit, and then correspond to the output circuit. A packet switch characterized by being transmitted from an output line. 2. A first priority determination circuit for detecting processing requests from the plurality of input circuits and controlling a writing order to the buffer, and a processing request from the plurality of output circuits for detecting the processing requests from the plurality of output circuits. And a second priority determination circuit for controlling the reading order from the packet switch according to claim 1.