JPH01270431A - High-speed packet exchange switch - Google Patents

Abstract

PURPOSE:To simplify the input/output control of packets to improve the reliability by dividing a buffer memory to areas corresponding to respective outgoing lines and storing packet signals in corresponding areas in the time-division multiplex system and reading out them and performing the switching operation. CONSTITUTION:Inputted packets are multiplexed in time division by a multiplexing circuit 102 and are stored in areas corresponding to respective outgoing lines of a buffer memory circuit 103 in the input order. At the time of this input, a head discriminating circuit 105 in a write control circuit 104 discriminates the outgoing line, to which a pertinent packet should be outputted, from header information of the packet and a selecting circuit 106 selects one write pointer corresponding to this outgoing line from write pointers 107 and 108 provided for respective outgoing lines. This packet is stored in the address indicated by the write pointer in the area corresponding to the pertinent outgoing line of the buffer memory 103.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to high-speed packet switching for collectively exchanging voice, data, images, etc., and particularly to a method of configuring the switch.

(Prior Art) An asynchronous time-division multiplex transmission method is available as a method for multiplexing circuit-switched signals and packet-switched signals efficiently and with high flexibility. This method was discussed at the 1984 International Switching Symposium by Thomas N.
National Switching Sympos
[Asynchronous Time Division Technique: An Experimental Packet Network Inchrating Video Communications (Asyn 1984)]
chronous time divisiontec
hnique: an experimental
packet network integration
Video communication is described in the month. As shown in Figure 7, this method divides continuous communication signals such as audio and video and burst communication signals such as data and still images into fixed-length data blocks, and then identifies the communication. It adds a label or header for the transmission, multiplexes it into a fixed length time slot on the transmission path, and transmits it. Since the terminal and the transmission path can be asynchronous, and the speed of the terminal and the speed of the transmission path can be independent, it is possible to cope with any type of terminal that appears in the future, and it is possible to operate the transmission path independently of the terminal. It is very convenient because it can be developed.

Asynchronous time division multiplexing switches or high-speed packet switching switches compatible with this multiplexing method have been proposed. An example is shown in FIG. 8 (see the above reference). In FIG. 8, packets (also referred to as cells) that arrive on a plurality of incoming lines 200 and 201 after being asynchronously time-division multiplexed are time-division multiplexed in a multiplexing circuit 202 and input to a buffer memory circuit 203. . When inputting to the buffer memory circuit, the header identification circuit 204 identifies the outgoing line to which the packet is to be output, takes out one address from the free address queue 205 that stores addresses in free areas, and inputs the address to that address. A read address queue 206 that stores packets and is provided for each outgoing line.
．． The storage address is registered in the queue corresponding to the outgoing line of the packet out of 207 via the distribution circuit 208.

On the other hand, on the read side, a selection circuit 210 sequentially searches read address queues 206 and 207 according to the output of a counter circuit 209 that instructs outgoing lines in order, and selects an address in which a packet to be output to the outgoing line is stored. The packet stored at that address is read from the buffer memory circuit 203. The address number that has been read and becomes empty is stored in the empty address queue 20.
It is stored in 5. If the read address queue for the outgoing line is empty, the dummy packet generation circuit 211 outputs a dummy packet indicating vacancy, and the process moves on to read processing for the next outgoing line. The packet signal read from the buffer memory 203 is converted into an asynchronous time division multiplexed signal corresponding to each output line 213 and 214 by a demultiplexing circuit 212 and output. By the above operation, the packet signal on the incoming line is output to the desired outgoing line, and the switching operation is realized.

(Problems to be Solved by the Invention) In the high-speed packet exchange switch described above, the buffer memory is shared by a plurality of outgoing lines, so the buffer memory capacity may be small, but the control for sharing becomes complicated. In other words, it is necessary to prepare a queue for storing addresses of free areas and a queue for storing addresses of packets waiting to be sent for each outgoing line, and each time a packet is written to or read from the buffer memory, the free address queue and Processing for exchanging addresses with the address queue during output is required. Also, if a certain address disappears due to noise or some kind of malfunction, or if a situation occurs where a duplicate address exists, an unusable area will occur in the buffer memory, or the buffer memory will be overwritten and the packet will disappear. Otherwise, the packet may be sent to the wrong outgoing line. Furthermore, it is not easy to detect the occurrence of such a situation, and the processing for this becomes complicated. The present invention solves the problems of the prior art, has simple control, high reliability, and LS
The objective is to obtain a high-speed packet switching switch that is compatible with future developments in I technology and the like.

(Means for Solving the Problems) In order to achieve the above object, the first aspect of the present invention is to provide a time division multiplexing circuit that time division multiplexes packet signals on all incoming lines; a buffer memory circuit that temporarily stores the packet signal in areas divided into areas corresponding to outgoing lines to which the packet is to be output; and an outgoing line to which the packet is to be output based on header information of the time-division multiplexed packet signal; a write control circuit that determines the packet signal and controls writing of the packet to an area corresponding to the outgoing line of the buffer memory; and a time division multiplexing format for the packet signals accumulated in the buffer memory circuit for each outgoing line. A high-speed packet switching switch is constituted by a readout control circuit that reads out the data, and a demultiplexing circuit that time-division multiplexes and demultiplexes the readout packet signal in the time division multiplex format and converts it into a packet signal corresponding to each outgoing line. It is. In addition, in order to achieve the above object, the second aspect of the present invention is to provide a time division multiplexing circuit that time division multiplexes packet signals on all incoming lines, and a time division multiplexing circuit that time division multiplexes the packet signals on all incoming lines, and a time division multiplexing circuit that processes the time division multiplexed packet signals for each outgoing line. an address filter circuit for identifying and receiving packets to be output to the outgoing line based on header information of each packet from the distributed packets; and a packet received by the address filter circuit. A buffer memory circuit corresponding to each output line that temporarily stores signals, and a write/read control corresponding to each output line that controls writing of received packets to the buffer memory circuit and reading of packet signals stored in the buffer memory circuit. The circuit constitutes a high-speed packet switching switch.

Furthermore, in order to achieve the above object, a third aspect of the present invention provides a bus in which packet signals on all incoming lines are time-division multiplexed, and a bus in which packet signals on each incoming line are multiplexed at a periodic timing determined for each incoming line. A bus transmission circuit corresponding to each incoming line that sends out onto the bus, and a packet signal to be output to each outgoing line by monitoring the packet signals on the bus and using the header information of each packet.

An address filter circuit corresponding to each outgoing line that identifies and receives the packet signal, a buffer memory circuit corresponding to each outgoing line that temporarily stores the packet signal received by the address filter circuit, and writing of the received packet to the buffer memory circuit and A high-speed packet exchange switch is constituted by a write/read control circuit corresponding to each output line that controls reading of packet signals stored in the buffer memory circuit.

The fourth aspect of the present invention is to provide a loop in which packet signals on all incoming lines are time-division multiplexed, and a loop in which packet signals on each incoming line are multiplexed at periodic timing determined for each incoming line. A loop transmission circuit corresponding to each incoming line that sends out to the top, and an address corresponding to each outgoing line that monitors the packet signal on the loop and identifies and receives the packet signal to be output to each outgoing line based on the header information of each packet. a filter circuit, a buffer memory circuit corresponding to each outgoing line that temporarily stores the packet signal received by the address filter circuit, and a buffer memory circuit for writing the received packet to the buffer memory circuit and writing the packet signal stored in the buffer memory circuit. Writing for each output line that controls reading
The read control circuit constitutes a high-speed packet switching switch.

(Function) In the first aspect of the present invention, the buffer memory is divided into areas corresponding to each outgoing line, and the time-division multiplexed packet signals on all incoming lines are identified by the header to identify the outgoing line to be output. The packets are stored in the area corresponding to the outgoing line in the buffer memory, and the packets stored in the area corresponding to each outgoing line in the buffer memory are periodically read out one by one for each outgoing line in a time division multiplexed format. This realizes the exchange operation. Since the buffer memory area is divided according to outgoing lines, packet input/output control is extremely simple, and a highly reliable high-speed packet switching switch can be obtained.

Further, in the second aspect of the present invention, a plurality of buffer memories are provided for each outgoing line, and from the time-division multiplexed packet signals on all incoming lines, an address filter also provided for each outgoing line is used to output the packet signals to the outgoing line. The exchange operation is realized by taking in the packet signals to be received, storing them in the buffer memory, and then sequentially sending them out to the outgoing line. After all, since the buffer memory is separate for each outgoing line, packet input/output control becomes extremely simple.

The third aspect of the present invention is to realize the function of time-division multiplexing the packet signals on all incoming lines in the second aspect of the present invention using a time-division bus and a bus transmission circuit provided for each incoming line. .

The fourth aspect of the present invention is to realize the function of time division multiplexing the packet signals on all incoming lines in the second aspect of the present invention using a time division loop and a loop transmission circuit provided for each incoming line. .

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first high speed packet switching switch configuration according to the present invention. In FIG. 1, packets arriving on a plurality of incoming lines 100, 101 after being asynchronously time-division multiplexed are further time-division multiplexed in a multiplexing circuit 102 and input to a buffer memory circuit 103. The buffer memory circuit 103 is divided into areas corresponding to each outgoing line,
Furthermore, each area is assigned a -dimensional address and operates as a cyclic buffer. That is, the packets are continuously accumulated in the order in which they were input for each outgoing line corresponding area. When inputting a packet to the buffer memory circuit, the header identification circuit 105 in the write control circuit 104
identifies the outgoing line to which the packet is to be output from the header information of each packet, and selects by the selection circuit 106 the one corresponding to the outgoing line from among the write pointers 107 and 108 provided for each outgoing line. The write pointers 107 and 108 hold a value obtained by adding 1 to the final address of the packets that are successively stored in the area corresponding to each outgoing line in the buffer memory circuit 103. The packet is stored at the address indicated by the write pointer in the area corresponding to the outgoing line in the buffer memory circuit 103. Further, the value of the write pointer is incremented by 1 by distributing the increment clock 119 through the distribution circuit 109.

On the read side, on the other hand, a selection circuit 111 sequentially searches read pointers 112 and 113 in accordance with the output of a counter circuit 110 that sequentially instructs outgoing lines. The read pointers 112 and 113 indicate the start addresses of packets that are successively stored in areas corresponding to each outgoing line in the buffer memory circuit 103. The packet stored at that address is read from the buffer memory circuit 103, and the value of the read pointer is transferred to the distribution circuit 103.
14 by one.

When no packet is stored in the area corresponding to a certain outgoing line of the buffer memory circuit 103, the read pointer corresponding to that outgoing line is displayed as buffer idle. When the read pointer selected by the selection circuit 111 is displayed, the dummy packet generation circuit 115 outputs a dummy packet indicating vacancy. Further, when the area corresponding to a certain outgoing line in the buffer memory circuit 103 is full, the write pointer corresponding to that outgoing line is displayed as buffer busy. When the write pointer selected by the selection circuit 106 is displayed, no packet is written to the buffer memory circuit 103;
The packet is discarded. Idle and busy buffers are detected by comparing the values of read and write pointers with each other.

The packet signals read out from the buffer memory 103 in this way are sent to each output line by a demultiplexing circuit 116.
17.118 compatible asynchronous time division multiplexed signal,
Output. By the above operation, the packet signal on the incoming line is output to the desired outgoing line, and the switching operation is realized.

In the high-speed packet switching switch with this configuration, since a buffer memory circuit is provided for the outgoing line,
Control is extremely simple as it is only necessary to operate the write/read pointers corresponding to each outgoing line. Furthermore, even if an error occurs in the pointer value due to noise or other factors, the effect will be limited to the relevant outgoing line, and although incorrect packets may be output from time to time, if the pointer operates correctly thereafter, the situation will be normal. The state can be automatically returned to.

FIG. 2 shows a second high speed packet switching switch configuration according to the present invention. In FIG. 2, packets arriving on multiple incoming lines 100, 101 after being asynchronously time-division multiplexed are further time-division multiplexed in a multiplexing circuit 102, and an address filter circuit 1 provided for each outgoing line.
20.121. Address filter circuit 12
0.121 identifies the packet to be output to the corresponding outgoing line from the header information of each time-division multiplexed packet, and writes the packet into buffer memory circuits 122 and 123 provided for each outgoing line. Buffer memory circuit 1
22 and 123 are each given a -dimensional address and operate as a cyclic buffer. That is, the packets are continuously stored in each buffer memory circuit in the order in which they are input. Buffer memory circuit 122.12
When inputting a packet to 3, the write pointer 126.12 in the write/read control circuit 124°125
7 holds a value obtained by adding 1 to the final address of the packets continuously stored in the buffer memory circuits 122 and 123. The packet addressed to the outgoing line identified by the address filter is sent to the buffer memory circuit 122.12.
The data is stored at the address indicated by the write pointer in No. 3, and the value of the write pointer is incremented by one.

On the other hand, on the read side, the write/read control circuit 12
4. Read address pointer in 125 128°12
9, packets addressed to the outgoing line that are not stored in the buffer memory circuits 122 and 123 are sequentially output. The read pointers 128 and 129 are connected to the buffer memory circuit 122.
, 123 indicates the start address of the packets stored consecutively. The packet stored at that address is read out from the buffer memory circuits 122 and 123, and the value of the read pointer is incremented by one. In this way, the buffer memory 122
．． The packet signal read from 123 is transmitted to each outgoing line 13.
2.133 as an asynchronous time division multiplexed signal.

By the above operation, the packet signal on the incoming line is output to the desired outgoing line, and the switching operation is realized.

When no packet is stored in a certain buffer memory circuit, the read pointer corresponding to the outgoing line is caused to display buffer idle. When this is displayed on the read pointer, the dummy packet generation circuits 130 and 131 output a dummy packet indicating vacancy.

Further, when a certain buffer memory circuit is full, the write pointer corresponding to that outgoing line is caused to display a buffer busy state. When this is displayed on the write pointer, the packet is not written to the buffer memory circuit and the packet is discarded. Idle and busy buffers are detected by comparing the values of read and write pointers with each other.

Even in the high-speed packet switching switch with this configuration, since a buffer memory circuit is provided for the outgoing line,
As with the configuration shown in FIG. 1, control is extremely simple. Furthermore, even if an error occurs in the value of the pointer due to noise or other factors, the effect of the error is minimized and a highly reliable switch can be obtained.

FIG. 3 shows a third high speed packet switching switch configuration according to the present invention. In FIG. 3, bus transmission circuits 140 and 141 provided for each incoming line once buffer packets on the incoming line, and then transmit the packets to the bus 142 in order at periodic timing determined for each incoming line. If the number of incoming lines is N, the bus speed will be N times the speed of each incoming line. In this way, the packets on the input lines 100 and 101 are time-division multiplexed on the bus 142, and the time-division multiplexed packet signals are sent to the address filter 12.
0.121 is input.

Address filter circuit 120, 121, buffer memory circuit 122, 123, write/read control circuit 12
4°125, write pointer 126.127, read pointer 128.129, dummy packet generation circuit 1
The structure and operation of 30 and 131 are exactly the same as the structure and operation of the corresponding part in FIG.

In this configuration as well, high reliability can be achieved with simple control, similar to the configurations shown in FIGS. 1 and 2. Furthermore, in this configuration, the circuit block 143 shown in FIG.
144, it is possible to have exactly the same circuit configuration for each combination of incoming lines and outgoing lines, and by arranging the required number of them, the entire switch can be constructed.

Therefore, it is suitable for LSI implementation, and as a result, it is possible to obtain a high-speed packet exchange switch that is economical and has a large degree of flexibility in switch scale.

FIG. 4 shows a fourth high speed packet switching switch configuration according to the present invention. In Fig. 4.

Loop transmission circuits 150 and 151 provided for incoming lines once buffer packets on each incoming line, and then transmit the packets to the loop 152 via selection circuits 153 and 154 at periodic timing determined for each incoming line. . At times other than the timing assigned to each incoming line, the selection circuit selects the signal from the previous incoming line. The signal from the input line at the previous stage is temporarily stored in the temporary storage circuits 155 and 156, and then inputted to the selection circuits 153 and 154. Therefore, −
The time memory circuits 155 and 156 constitute a circular shift register over all input lines. When the number of incoming lines is N, the speed of the loop is N times the speed of each incoming line. In this way, packets on the input lines 100.101 are time-division multiplexed onto the loop 152, and the time-division multiplexed packet signals are input to the address filters 120.121.

Address filter circuit 120, 121, buffer memory circuit 122, 123, write/read control circuit 12
4°125, write pointer 126.127, read pointer 128.129, dummy packet generation circuit 1
The configuration and operation of 30.131 are exactly the same as those of the corresponding parts in FIGS. 2 and 3.

In this configuration as well, high reliability can be achieved with simple control, similar to the configurations shown in FIGS. 1, 2, and 3. Furthermore, similarly to the configuration in FIG. 3, the circuit block 15 in FIG.
7.158, the circuit configuration can be completely the same. Therefore, it is possible to obtain a high-speed packet exchange switch that is suitable for LSI implementation, is economical, and has a large degree of flexibility in switch scale.

In the above explanation, whether the input/output lines such as input lines, output lines, buses, loops, or buffer memories are serial,
Although no particular mention was made as to whether it was parallel or not, the present invention is equally applicable in either case.

Note that, as is well known, by combining a plurality of the above-described high-speed packet switching switches, it is possible to configure an even larger scale switch. For example, as shown in Fig. 5, incoming line double connection (Fig. 5(a)),
There is a method of combining the two, such as the outgoing line dual connection (see (b) in the same figure), or as shown in (e) in the same figure. In the case of multiple outgoing line connections, a function for controlling outgoing line contention is usually required as shown in FIG. 5(b). Further, as shown in FIG. 6, a large-scale switch can be easily constructed by connecting switches in multiple stages.

(Effects of the Invention) As described above, in the high-speed packet switching switch according to the present invention, since a buffer memory circuit is provided for each outgoing line, control is extremely simple. Furthermore, even if an error occurs due to noise or other factors, the influence thereof is minimized, and a highly reliable switch can be obtained. Furthermore, in the third and fourth configurations of the present invention, it is possible to have exactly the same circuit configuration for each set or multiple combinations of incoming and outgoing lines, and by arranging the required number of them, the entire This switch is suitable for LSI integration, and as a result, it is possible to obtain a high-speed packet switching switch that is economical and has a large degree of flexibility in switch scale.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a first high-speed packet switching switch configuration based on the present invention, FIG. 2 is an explanatory diagram showing a second high-speed packet switching switch configuration based on the present invention, and FIG. 3 is an explanatory diagram showing a second high-speed packet switching switch configuration based on the present invention. An explanatory diagram showing a third high-speed packet switching switch configuration, FIG. 4 is an explanatory diagram showing a fourth high-speed packet switching switch configuration based on the present invention, and FIGS. An explanatory diagram showing a method of configuring a large-scale switch using switches, Fig. 7 is an explanatory diagram showing the principle of asynchronous time division multiplexing, and Fig. 8 is an explanatory diagram showing the configuration of a conventional high-speed packet switching switch. be. In the figure, 102... multiplexing circuit, 103.122.123...
・Buffer memory circuit, 104... Write control circuit, 120° 121... Address filter circuit, 124
．． 125...Write/read control circuit, 130.
131...Dummy packet generation circuit, 140.141
. . . bus transmission circuit, 150, 151 . . . loop transmission circuit, respectively.

Claims (4)

[Claims] (1) In a high-speed packet switching switch having multiple incoming lines and multiple outgoing lines, a time division multiplexing circuit that time-division multiplexes packet signals on all incoming lines, and a time-division multiplexing circuit that time-division multiplexes the packet signals on all incoming lines; A buffer memory circuit temporarily stores the packet in an area divided into areas corresponding to the outgoing lines to which the packet is to be output, and determines the outgoing line to which the packet is to be output based on the header information of the time-division multiplexed packet signal; a write control circuit that controls writing of the packet to an area of the buffer memory corresponding to the outgoing line; and a read control circuit that reads out the packet signal stored in the buffer memory circuit in a time division multiplexed format corresponding to each outgoing line. and a demultiplexing circuit that time-division multiplexes and demultiplexes read packet signals in a time division multiplex format and converts them into packet signals corresponding to each outgoing line. (2) In a high-speed packet switching switch having multiple incoming lines and multiple outgoing lines, a time division multiplexing circuit that time-division multiplexes packet signals on all incoming lines, and a time-division multiplexing circuit that time-division multiplexes the packet signals on all incoming lines; means for distributing packets to address filter circuits corresponding to outgoing lines; an address filter circuit for identifying and receiving packets to be output to the outgoing lines from the distributed packets based on header information of each packet; and receiving by the address filter circuits. a buffer memory circuit corresponding to each outgoing line for temporarily accumulating the received packet signal; and a writing/writing/writing circuit corresponding to each outgoing line that controls writing of received packets to the buffer memory circuit and reading of the packet signal accumulated in the buffer memory circuit. A high-speed packet switching switch comprising a readout control circuit. (3) In a high-speed packet switching switch that has multiple incoming lines and multiple outgoing lines, a bus in which packet signals on all incoming lines are time-division multiplexed, and packet signals on each incoming line at periodic timing determined for each incoming line. a bus transmission circuit corresponding to each incoming line that sends out the packet signal onto the bus, and each outgoing line that monitors the packet signal on the bus and identifies and receives the packet signal to be output to each outgoing line based on the header information of each packet. a corresponding address filter circuit, a buffer memory circuit corresponding to each outgoing line that temporarily stores the packet signal received by the address filter circuit, and a buffer memory circuit for writing the received packet to the buffer memory circuit and storing the packet signal in the buffer memory circuit. A high-speed packet switching switch comprising a write/read control circuit corresponding to each outgoing line for controlling readout of packet signals. (4) In a high-speed packet switching switch that has multiple incoming lines and multiple outgoing lines, a loop in which packet signals on all incoming lines are time-division multiplexed, and packet signals on each incoming line at periodic timing determined for each incoming line. a loop transmission circuit corresponding to each incoming line that sends out the packet signal onto the loop, and each outgoing line that monitors the packet signal on the loop and identifies and receives the packet signal to be output to each outgoing line based on the header information of each packet. a corresponding address filter circuit, a buffer memory circuit corresponding to each outgoing line that temporarily stores the packet signal received by the address filter circuit, and a buffer memory circuit for writing the received packet to the buffer memory circuit and storing the packet signal in the buffer memory circuit. A high-speed packet switching switch comprising a write/read control circuit corresponding to each outgoing line for controlling readout of packet signals.