JP2755402B2 - Self-routing switching system and asynchronous transfer mode switching system - Google Patents

Description

Description: TECHNICAL FIELD The present invention has N (N is a natural number; the same applies hereinafter) incoming lines and N or M outgoing lines, and is used for high-speed packet switching, asynchronous transfer mode switching, and the like. A preferred N × N or N × M self-routing switching system and an asynchronous transfer mode switching system.

In telephone switching (circuit switching), once a communication path is set, the communication path is maintained until the end of the call. In the case of multiplex transmission, each call (channel) is switched at high speed.
Since the position of each call on the frame is constant, simple sequential switching is sufficient. On the other hand, in packet switching, each packet has its own destination, and the destination of each packet viewed in chronological order varies, so the above two methods cannot be adopted. The method of distributing to the line (memory exchange) has been adopted. However, this memory exchange takes time, and is not suitable when high-speed exchange is required.

The self-routing communication path divides transmission information (voice, image, data, etc.) of a call requested to be transmitted into packets or cells (asynchronous transfer mode blocks), particularly in high-speed packet exchange and asynchronous transfer mode exchange. When high-speed switching to a different outgoing line for each packet or cell is required when transmitting data, and when it is not desirable for high-speed call processing to centrally control the communication path from outside using software. Is preferred.

2. Description of the Related Art A high-speed packet switch for transmitting transmission information (voice, image, data, etc.) of a call for which transmission has been requested by dividing it into a plurality of packets and exchanging such packets at a high speed is disclosed in, for example, Japanese Patent Application Publication No. It is known as shown in -501038. Banyan type self-routing channels suitable for such high-speed packet switches have already been proposed (for example, international Zurich seminer on digita).
l communications1986, D4.1, RMWuise et al (AT & T
Bell Laboratory) “expariments in wideband packet
technology "P.135to P.139).

FIG. 1 is a circuit diagram showing a conventional banyan type self-routing communication channel. This is constructed by connecting the 2 × 2 unit self-routing switches S _ij (ij is 11, 12,...) In a reverse shuffle connection as shown in the figure (8 × 8B in this example).
anyan) is shown, and each packet on the incoming line has outgoing line control information (in this example, the outgoing line number in binary display)
The transmission information (INF) is sent to the designated outgoing line by operating each switch using the control information. For example, the control information is "010", this packet is to enter into IN1 of S _11, MSB of the first stage (i = 1) switch control information
The packet because There is a "0" is sent to its "0" output, S ₂₁ In response to this sends a look at the following bit of the MSB which is the "1" output from a 1, Following this, S ₃₂ is LSB
Since this is "0", it is sent to the "0" output, and the packet is sent to the target outgoing line 010.

FIG. 2 is a diagram showing a configuration when the scale of the communication channel of FIG. 1 is expanded. In the above-mentioned self-routing communication channel of the Banyan type, to increase the number of input / output lines, for example, 16 × 16
To make it a Banyan, look like Figure 2. That is, 4 × 4 Banya
n are arranged, and two 2 × 2 unit switches are arranged on the output side, and wired as shown to form an 8 × 8 Banyan. Similarly, two 8 × 8 Banyans are arranged, and a 2 × 2 Banyan is arranged on the output side. 4x2 2-unit switches, connect as shown, 16x16Banyan
To A 32 × 32 Banyan or the like can be similarly configured. In general, if N × N Banyan, 2 × 2 unit switch is log ₂ N
The transmission information can be transmitted to a target outgoing line by cascade connection. In the unit switch, the output terminal has twice the operation speed of the input terminal to avoid congestion.

As described above, since the self-routing communication path of the Banyan type is configured based on the principle of the bisection method, the scale expansion is performed by combining two N × N switches and N 2 × 2 switches to 2N × It is performed in the same way as making a 2N switch, and it is difficult to take a module configuration with the unit of extension being doubled.

In the self-routing communication path of the Banyan Type, the unit switches _Sij are connected in multiple _stages, but are not connected in multiple stages. Path formed between the incoming lines and outgoing lines are only one example, if the transmission information entered in S ₁₁ of FIG. 1 is to leave the 111 th outgoing line, one route 1 of S ₁₁ → S ₂₂ → S ₃₄ Only, S
₁₁ → other routes, such as the S ₂₃ → S ₃₄ does not exist.

DISCLOSURE OF THE INVENTION The present invention has been made to solve the above problems, and provides a self-routing switching system and an asynchronous transfer mode switching system in which a module configuration is easy and a plurality of routes to the same outgoing line can be formed.

Another object of the present invention is to provide a specific configuration of a switch module constituting a self-routing switching system and an asynchronous transfer mode switching system.

BRIEF DESCRIPTION OF THE DRAWINGS Hereinafter, the present invention will be described through embodiments with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a conventional Banyan type self-routing communication channel, FIG. 2 is a diagram showing a configuration in which the scale of the communication channel shown in FIG. 1 is expanded, and FIG. FIG. 4 is a block diagram showing a first embodiment of a communication path in a self-routing (asynchronous transfer mode) switching system, FIG. 4 is a diagram showing a first example of a format of information appearing on the incoming line, and FIG. FIG. 6 is a diagram showing a second example of the format of FIG. 3, FIG. 6 is a diagram showing a specific example of the communication path according to the first embodiment shown in FIG. 3, and FIG. 7 is a self-routing switch module (SRM).
FIG. 8A is a block diagram showing an outline of a self-routing (asynchronous transfer mode) switching system according to the present invention, FIG. 8B is a diagram showing a packet switching network, and FIG. FIG. 10 is a diagram showing a configuration example of such a self-routing (asynchronous transfer mode) switching system. FIG. 10 is a diagram showing a first example of the format of information appearing at the output of the route setting means. FIG. 11 is appearing at the output of the route setting means. FIG. 12 is a diagram showing a second example of the information format, FIG. 12 is a circuit diagram showing a specific example of the route setting means, FIG. 13 is a diagram specifically showing control information, and FIG. A circuit diagram showing an example, FIG. 15 is a conceptual diagram of a self-routing (asynchronous transfer mode) switching system capable of performing priority processing, and FIG. 16 is a circuit diagram showing a specific example of a self-routing switch module for performing priority processing. FIG. 17 is a circuit diagram showing an example of a selector control circuit for performing priority processing. FIG. 18 is a block diagram showing the principle of the second embodiment of the self-routing switch module. FIG. 9 is a circuit diagram showing a specific example for realizing the second embodiment.

FIG. 3 is a block diagram showing a first embodiment of a communication path in a self-routing (asynchronous transfer mode) switching system according to the present invention. Self-routing communication channel of the first embodiment
30 comprises one or more basic switching units. In this figure, a communication path 30 including one basic switching unit is shown. This basic switching unit consists of an input stage self-routing switch module (SRM) 31,
Interstage self-routing switch module (SRM) 32
And output stage self-routing switch module (SRM) 3
3 Thus, in the present invention, the SRM _ij is connected in a multi-stage link as shown.

Even in the Banyan type, the unit switches _Sij are connected in multiple _stages, but this is not a multistage link connection. Incoming lines, the path formed between outgoing line is only one, if for example to transmission information which entered the S ₁₁ of FIG. 1 exits to # 111 outgoing _{line, S 11 → S 22 → S} 34
And there is no other route such as S ₁₁ → S ₂₃ → S ₃₄ . In this regard, in the multi-stage link connection of the present invention,
In addition to SRM ₁₁ → SRM ₂₁ → SRM ₃₁ there are other paths such as SRM ₁₁ → S ₂ m → SRM ₃₁ .

For input lines N, switches SRM _{11 to} SRM of input stage SRM _{11
1N / n} is _n for input, m for output, and N / n
And the modules SRM _{21 to} SRM _2m of the intermediate stage SRM 32 are respectively
The input stage is N / n, the output end is N / n, and the number is m.
Each of the modules SRM _{31 to} SRM _{3n / N of the} SRM 33 has an input terminal m, an output terminal n, and a number N / n. L _ij is a primary link and M _ij is a secondary link.

Connect input stage module (31) SRM ₁₁ ~SRM input of _{1N / n} is the incoming lines, an output terminal is connected to an input of each module of the intermediate-stage SRM 32, m pieces of output terminals of the SRM ₁₁ is the m Intermediate stage SRM
Module SRM _{21 to} SRM _2m . Similarly, connect SRM _{1N / n,} etc., and connect each N / n output terminal of the middle stage module to N / n modules SRM ₃₁ on the outgoing line side.
Connect to one of each m input terminals of ~ SRM _{3N / n} .

In this example, the switch module SRM _ij has a three-stage configuration including an input stage, an intermediate stage, and an output stage.
It may be configured with three stages as shown in the figure, and may have a total of five stages (the number of basic switching units is two). The total number of input terminals of the input stage switch modules SRM _{11 to} SRM _{1N / n} is N and equal to the number of input lines, and the total output terminals of the output stage switch modules SRM _{31 to} SRM _{3N / n} are N and outgoing lines. And the middle stage switch modules SRM _{21 to} SRM
In this example, the input fraction of the RM _2m is mN / n, which is equal to the output fraction of the input stage switch module, and the output fraction is also mN / n, which is equal to the input fraction of the output stage switch module, and there is no space. May be left empty. In particular, when expansion is anticipated, it is preferable to install many (as many as required) intermediate stage switch modules and install a small number of input / output stage switch modules.

FIG. 4 is a diagram showing a first example of a format of information appearing on the input side of the self-routing switch path, and FIG. 5 is a diagram showing a second example of a format of information appearing on the input side of the self-routing switch path.

As shown in FIGS. 4 and 5, control information (C.
INF) RH _1, RH _2, advance to have a ...... RH _n. This may be in series with the transmission information (T · INF) as shown in FIG. 4 or in parallel as shown in FIG. In the latter case, of course, a dedicated line for control information is required. The control information RH ₁ , RH ₂ ,... Indicate the number of the i-th link, that is, the output terminal number of the first-stage switch module. To the output end of.

In the self-routing speech path 30, the intermediate stage switch module SRM ₂₁ ~SRM _2m a required number (m pieces) provided, the input and output stage switch modules previously installed less than installable number (N / n pieces) For the expansion, input and output stage switch modules may be simply added, and connection to the input and output stage switch modules may be performed. At this time, there is no need to make any changes to the existing switch module and its wiring.

In the self-routing communication path 30, there are a plurality of types of paths between the incoming line and the outgoing line.
Compared to only one route such as ype, there is a great advantage in processing when traffic is congested. That is, in the synchronous transfer mode switching such as packet switching or cell switching, especially when data is transmitted, the amount of generated data often changes greatly with time, so that the transmission delay is reduced in a single path. It fluctuates greatly. However, if there are a plurality of paths as in the present invention, the load can be distributed, and another route can be taken at the time of congestion, so that the transmission delay can be reduced.

FIG. 6 is a diagram showing a specific example of the communication path according to the first embodiment shown in FIG. 3, and shows an example in a case where N9, n = m = 3. The 3 × 3 SRM _ij has three input stages, three intermediate stages, and three output stages.
Number Yes, primary link L _11, L _12, L ₁₃ connects the three output terminals of the input stage switch modules SRM ₁₁ to each first uppermost input of the intermediate stage switch module SRM ₂₁ ~SRM _23, 1
The following link _{L 21 ~L 23, L 31 ~L} 33 is also equivalent thereto. Secondary link M ₁₁ ~M ₁₃ includes three switch modules SRM ₃₁ three outputs output stage of the intermediate stage switch modules SRM ₂₁ to S
Connected to each first input terminal of the RM _33, 2 primary link M ₂₁ ~
M _23, M ₃₁ ~M ₃₃ is also equivalent thereto.

In this self-routing channel, SRM ₁₁ , SRM ₂₁ to SRM
If RM ₂₃ and SRM ₃₁ are installed, SRM ₁₂ and SRM ₃₂ , SRM ₁₃ and SR
Installation of M ₃₃ without changing any of the existing parts, simply L ₂₁
LL ₂₃ , L ₃₁ ML _33, M ₂₁ MM ₂₃ , and M ₃₁ MM ₃₃ are simply connected as shown.

For example, the path leading incoming line # 9 to outgoing line # 3 is SRM ₁₃ → S
RM ₂₁ → SRM ₃₁ , SRM ₁₃ → SRM ₂₃ → SRM ₃₁ , SRM ₁₃ → SRM ₂₃ → SRM
There are ₃₁ paths, SR traffic between SRM ₁₃ and SRM ₃₁
M ₂₁ ~SRM ₂₃ is to it can be distributed to, SRM if further SRM ₂₁ to, such as traffic comes out is late have focused
_By changing to the path via ₂₂ or SRM ₂₃ , the delay can be reduced.

Fig. 7 shows a self-routing switch module (SRM)
FIG. 3 is a circuit diagram showing a specific example of the SRM, and shows a 3 × 3 SRM as an example. I _i is a control information detecting circuit, _Di is a transmission information delay circuit, DM _i is a demultiplexer, DEC _i is a control information decoding circuit, FM _ij is a buffer memory, for example, First-IN Firs
t-Out (FIFO) memory, SEL _i selectors, SC _i the selector SEL _i in response to the request signal R _ij of memory FM _ij of FIFO
Is a selector control circuit that performs the above control.

The signals entering the input terminals # 1 to # 3 (i) are in the form of the aforementioned transmission information + control information (T.INF + C.INF),
I _i extracts this control information and sends it to the decoding circuit DEC _i .
If the self-routing communication path 10 has a three-stage configuration, the control information includes the first-stage (input stage) routing header RH ₁ , the second-stage (intermediate stage) RH ₂ , and the third-stage (output stage) RH ₃ because there three, depending on whether the detection circuit I _i is the self-routing switch module SRM is the what stage the appropriate control information RH
Is extracted. If the decode circuitry DEC _i in which control information input indicates an output terminal j, and sends the transmission information to the FIFO memory FM _ij operates the demultiplexer DM _i. For example, if the control information of the input terminal # 1 indicates the output terminal # 2, the DEC _i operates the DM ₁ to input the information of the input terminal # 1 to the FM ₂₁ . The selector control circuit SC ₁ is a FIFO memory FM _{11 to} FM ₁₃
When transmission information enters, by operating the selector SEL ₁ sends the said transmission information to the output # 1. Others are the same.

The selector control circuit SC _j, for example FIFO has scanned all times the request signal R _ij from the memory FM _ij, the request signal R _ij is detected, the content of the FIFO memory FM so as to output through the selector SEL _i Operate. Alternatively, R _ij is input to SC _j as an interrupt input, and when an interrupt occurs,
SC _j outputs the contents of the FIFO memory FM through the selector SEL.

If the FIFO memory _FMij has a capacity of a plurality of packets or cells, a buffer function can be obtained, which can sufficiently cope with a case where transmission data temporarily increases.

Self-routing switch module SRM _ij has input terminal 3
The number of output terminals is not limited to three, and generally n input terminals, m output terminals, where n> m, n = m, or n <m. When n> m, a plurality of input terminals sharing the same output terminal are generated. However, if a call (channel) has a small transmission amount, this can be sufficiently processed. When n <m, it is possible to divide one input into two outputs and to deal with the case of high speed on the input side and low speed on the output side. Of course, the excess may be used as play.

For the same reason, the use of the 3 × 3 self-routing switch module in FIG. 6 does not necessarily mean that the number of intermediate-stage switch modules SRM _{21 to} SRM ₂₃ is three, but may be two or four. The number of stages is not limited to three. For example, the entire stage shown in FIG. 6 or FIG. 3 is set as an intermediate stage, and an input stage and an output stage switch module are added to the intermediate stage to form a total of five stages. It may be. However, generally, three stages are appropriate.

The control information C • INF is added in series or in parallel to the call (packet or cell) on the input side as performed in the Banyan type or the like. At the time of originating a call, if control information for a call is determined by call processing, the VCN (Virtual c
hannel number) and the control information are registered in a table, and the control information is added to the incoming call by referring to the table. The control information is added because it is necessary while going through the switch module group having the multi-stage link configuration, but is unnecessary because it is unnecessary when it goes out the line.

As described above, according to the configurations of FIGS. 3 to 7,
The number of incoming and outgoing lines can be increased or decreased without changing the existing wiring.
The amount of increase / decrease is not limited to a multiple of 2, but can be increased / decreased in units of the number of input / output terminals of the switch module.

It is preferable to provide more intermediate stage switch modules than the number of switch modules on the incoming and outgoing lines in preparation for the expansion of incoming and outgoing lines. However, it is also possible to reduce the number of incoming and outgoing switches by multiplexing.

In addition, since the self-routing communication path 30 has a plurality of paths connecting the incoming and outgoing lines, the delay is small even at the time of congestion.

FIG. 8A is a block diagram showing an outline of a self-routing (asynchronous transfer mode) switching system according to the present invention, in which 10 is a route setting means, and 20 is a self-routing speech path (SRSP). path). The route setting means 10 receives information input from each of the plurality of incoming lines # 1, # 2, #N. This information consists of a pair of original transmission information (voice information, facsimile data, etc. divided into packets or cells) T.INF and identification information I.INF. The identification information is an identification number (such as a virtual channel number (VCN)) assigned to each cell under the asynchronous transfer mode exchange described above. This is an identification number assigned to the packet. The identification number (VCN) will be described with reference to FIG. 8B. FIG. 8B shows a packet switching network. In FIG. 8B, switches 0 to n are packet switching systems,
_{0 to} CP _n are call processing units for switches _{0 to n} , X is a calling terminal belonging to switch 0, Y is a receiving terminal belonging to switch n, and VCN _{0 to} VCN _n are identifications for link 0 to link n. Number. When CP ₀ detects the occurrence of a call from terminal X and recognizes the destination of the call (terminal Y), it performs a call setup phase. Assigning the communication between the call processor CP _0, CP ₁ ~CP _n, the transmission path is set, the call processing unit identification number VCN ₀ ~VCN _n for each link, respectively. And
The correspondence between pairs of identification numbers such as VCN ₀ / VCN ₁ , VCN ₁ / VCN ₂ ... VCN _n-1 / VCN _n is stored. Thereafter, each call processing unit generates a packet transmission phase. In this packet transmission phase, CP ₀ controls switch 0 to connect terminal X to link 0, and adds identification number VCN ₀ to the header of the packet from terminal X. CP ₁ has its identification number VCN
Upon detecting ₀ , the CP ₁ receives the packet from the terminal X and recognizes the destination of the packet. The CP ₁ controls the switch 1 to connect the link 0 to the link ₁ , converts the VCN ₀ to the VCN ₁ , and adds the identification number VCN ₁ to the packet. The other operations of CP ₂ to CP _n-1 are the same as those of CP ₁ described above.
Is exactly the same as

When CP _n detects the identification number VCN _n , it recognizes the reception of the packet to the terminal Y, and controls the switch n to transfer the received packet to the terminal Y.

In FIG. 8A, the route setting means 10 performs the above-described call setting phase, but the call transfer phase is automatically executed without control of the route setting means 10, ie, the self-routing switch.

The route setting means 10 monitors the identification information from the information of the incoming line, and generates control information C.INF according to the identification information.

The self-routing communication path (SRSP) 20 sends out the transmission information of the incoming line from the outgoing line based on the control information C.INF thus generated. In this case, the SRSP 20 forms a multipath therein. Conventional SRSP (Fig. 1, 2
In the figure, there is only one path from one incoming line to one outgoing line, but in the SRSP20 of the present invention, there are a plurality of paths from one incoming line to one outgoing line, forming a multipath. I do. The route setting means 10 determines which path to select.

Further, the SRSP 20 of the present invention also has a built-in buffer memory means for temporarily storing at least transmission information (both transmission information and control information if necessary), so that time adjustment for information transfer within the SRSP 20 is possible. Can be added.

FIG. 9 is a diagram showing an example of the configuration of a self-routing (asynchronous transfer mode) switching system according to the present invention. As the self-routing communication path (SRSP) 20 in the system, the SRSP 30 of FIG. ) Is shown.

The control information C.INF is added by the control of the call processing unit 12 in the control information adding circuits 11-1 to 11-N provided on each incoming line side.

As described in FIG. 8B, the call processing unit 12 sets the correspondence between the incoming line and the outgoing line for the pair of identification numbers, and determines the transfer path in the self-routing communication path 30 for each identification number of the input packet. I do.

As described in FIG. 6, the transfer path includes the control information C • INF.
The call processing unit sets the correspondence of the pair of identification numbers in the table of each additional circuit based on the control information C · INF. That is, identification information I.INF, for example, VCN, in the header of the input information is extracted. The additional circuit searches the table based on the extracted identification numbers to find the corresponding identification numbers and control information, and adds the searched control information and identification numbers to the input information in the additional circuits 11-1 to 11-N.

FIG. 10 is a diagram showing a first example of the format of information appearing at the output of the route setting means, and FIG. 11 is a diagram showing a second example of the format of information appearing at the output of the route setting means. 4 and FIG. In FIG. 10, transmission information T · INF as input information and identification information I
11 shows that control information C.INF is further added to the series with respect to the INF pair, and in FIG. 11, T.INF + I.INF
Shows a state in which C.INF is added in parallel to the pair of. Note that I.INF in FIG. 10 and I.INF in FIG. 11 are equivalent.

FIG. 12 is a circuit diagram showing a specific example of the route setting means. In the figure, how the route setting means 10 adds control information C.INF will be described by taking a case where packet information is input information as an example. First, the transmission source of the packet information executes a call setting phase for notifying the call processing unit 12 of the packet transfer destination before transmitting the packet. Microprocessor (MPU) 1 of call processing unit 12
5 sets the path of the communication path through which the packet should pass based on the notified transfer destination and transmission source, and also determines the identification number for the next link. Then, control information C.INF, which is switching information of each switch module to which this packet is input, that is, RH ₁ , RH ₂ , RH ₃ and an identification number for the next link are used as identification information (VCN) indicating a transfer destination. Store at the corresponding address.

Next, the packet is actually transmitted in the packet transfer phase. This packet is composed of transmission information and a header section made up of identification information (VCN ₀ ) added to the head of the transmission information. The synchronization circuit 17 synchronizes with the input packet using the synchronization pattern in the header section. The packet transferred to the communication path is stored in the buffer 13 of the additional circuit 11-1, and the identification information portion I.INF is input to the decoder 19 via the register 18 under the control of the synchronization circuit 17. You. Upon receiving the input packet identification information (identification number VCN ₀ ), the decoder 19 accesses the table 16 using the identification information VCN ₀ as an address. The table 16 identification information indicating a packet in the control information and the next link in the identification information VCN ₀ corresponds as previously described (VCN ₁₎ is stored. Then, the control information read from the table 16 is sent to the selector (SEL) 14 in order to add the control information and VCN ₁ to the head of the packet. The synchronization circuit 17 controls the switching of the selector 14, first sends out the control information C · INF and the new identification information VCN ₁ , then reads out the transmission information part of the packet from the buffer 13, and sends it to the communication path SRSP 30 via the selector 14. Send out.

As described above, the control information and the identification information for the next transmission path are added to the head of each packet on the input side of the communication path 30. As is apparent from the above description, the packet transfer control is performed not by the microprocessor 15 but by hardware.

FIG. 13 is a diagram specifically showing control information, and schematically shows how different routing headers RH select different paths. The number in the right block of RH is
The output lines of SRM ₁₁ , SRM ₁₂ , SRM ₁₃ are shown, the numbers in the center block of RH indicate the output lines of SRM ₂₁ , SRM ₂₂ , SRM ₂₃ , and the numbers in the left block of RH are SRM ₃₁ , SRM ₃₂ , SRM _{Shows 33} output lines. That is, the numbers in each block are L ₁₁ , L ₁₂ , L ₁₃ … M ₁₁
.. Are numbers corresponding to the right sub-index of the line symbol.

In order to operate the self-routing (asynchronous transfer mode) switching system of the present invention shown in FIG.
It is desirable that the information transfer can be performed according to the attribute of the information and the congestion state of the input information. That is, if the switching system of FIG. 9 is not devised, there are two disadvantages as follows.

First, since all are uniformly treated as packets or cells without considering information attributes, processing of data (eg, audio, video, etc.) packets or cells that require immediacy (real time) is not prioritized, A time delay occurs in each self-routing switch module SRM in the exchange.

Second, when the traffic bias causes an information transfer overload condition and it is necessary to control this, the routing header RH is rewritten. In this case, the packet generated by dividing the information of the same call is generated. Alternatively, if the cell is stagnant in another buffer FM, the transfer order of the packet or the cell may be reversed (overtake).

FIG. 15 is a conceptual diagram of a self-routing (Asynchronous Transfer Mode) switching system which is capable of the preferential treatment, each self-routing switch module SRM ₁₁ ~SRM _{3N / n} Upon receiving the priority processing request from the call processing section 12 The input information of the incoming line requiring the priority processing is preferentially selected and transmitted.

Therefore, at the time of call setting, if the attribute of the information requires priority processing (audio, video, etc.), the priority processing is assigned from the call processing unit 12 to each of the modules SRM _{11 to} SRM _{3N / n} . If the overload state of the input information can be detected in each of the modules SRM _{11 to} SRM _{3N / n} , the call processing unit 12 can also avoid the congestion of the information.
To M ₁₁ ~SRM _{3N / n} can perform the allocation of priority processing.

FIG. 16 is a circuit diagram showing a specific example of a self-routing switch module for performing priority processing. This SRM
Is basically completely equivalent to the SRM in FIG. In FIG. 16, a signal distributor SD for transmitting / receiving a signal to / from the MPU 15 (FIG. 12) of the call processing unit via a control bus 96 is provided in a self-routing switch module SRM, and a selector control circuit (SC) is provided. 97 has a configuration slightly different from the SC shown in FIG. Note that the circuit SC shown in FIG. 14 can be used as a specific example of the SC in FIG.

FIG. 14 is a circuit diagram showing a specific example of the selector control circuit (SC). In this figure, the transfer requests (* 1, * 2,... * N-1, * n) from the FIFO memory 85 are shifted one by one and input to the respective selectors (SEL) 90. Based on this, it is sent to an adder (ADD) 94 via a fixed priority circuit 92 and an encoder 93. In the adder 94, the transfer request number (* 1,
* 2,... * N-1, * n) to generate the number of the FIFO memory and send it to the selector (SEL) 86 in FIG. The command value to the selector (SEL) 86 is returned to the controller (CNT) 95 and transferred to the FIFO memory 85 that has requested the transfer.
Outputs OK signal. Then, the signal whose transfer has been completed is
Upon receiving the signal from the FIFO memory 85, a signal for increasing the count value of the counter 91 is sent to the counter 91.

Thus, the selection signal of the selector 90 is raised by, for example, “1”.

In this case, when two or more transfer requests overlap,
The fixed priority circuit 92 sends a transfer request signal to the encoder 93 in a predetermined priority order (for example, from the top in the drawing).

In this way, a plurality of self-routing modules SR
M switches autonomously to transfer information packets.

FIG. 17 is a diagram showing a circuit example of a selector control circuit for performing priority processing, and the selector control circuit SC shown in FIG.
And a circuit for priority processing is added a little. In FIG. 17, the controller (CNT) 105
The information storage status of each memory of the FIFO memory 85 in FIG. 16 is constantly monitored, and the monitoring signal is reported to the microprocessor MPU15 (FIG. 12) via the signal distributor SD101. That is, instead of sending the monitoring signal directly to the processor MPU15, the signal distributor SD101 collects the monitoring information as master information and sends the master information to the processor MPU to control the signal distribution. In addition, the controller 105 sends to the selector (SEL) 106 a priority instruction signal for preferentially transferring information in the predetermined FIFO memory 85 in accordance with a command from the processor MPU.
The selector 106 selects either the priority information according to a command from the processor MPU or the output of the counter 91. Other configurations are the same as those in FIG.

Next, the priority processing operation corresponding to the information attribute will be described with reference to FIGS.

First, the microprocessor MPU15 determines a priority transfer path in advance, and sets priority information in each module SRM. As an example, of the modules SRM _{31 to} SRM _{3N / n} , priority information is set so that information from the module SRM ₂₁ is preferentially processed.

Next, at the time of call setup, the terminal device (connected to the additional circuit in FIG. 15) is connected to the terminal device via the processor MPU 15 based on the virtual channel number (VCN) in the identification information I.INF from the terminal device. A routing header (RH) to a predetermined outgoing path is set in the additional circuit (described above). At this time, when the call attribute is checked and a call requiring immediacy such as voice and video is detected. Priority processing is performed in advance on the routing header so that the input information packet of the call is preferentially transferred through the module SRM ₂₁ .

Then, an additional circuit sends the example module SRM ₁₁ in the input stage adds the routing header to the input information.

In the module SRM ₁₁ , the routing header is transferred to the module SRM ₂₁ in the middle stage after seeing the routing header.

Next, in the modules SRM _{31 to} SRM _{3N / n} in the output stage, the priority transfer destination is previously set to the module SRM ₂₁ by the processor MPU, for example.
Since it is set to be the (most which may have been decided what priority transfer route in advance), the input information packets via the selector SEL84 in FIG. 16 FIF
It is stored in a predetermined FIFO memory 85 of the O memory 85 (for example, the FIFO memory in the uppermost column in the figure). On the other hand, processor
When a priority transfer processing request signal is input from the MPU 15 to the controller 105 shown in FIG. 17 via the signal distributor SD101, this signal is sent to the selector 106 as the switching signal SWS. This is different from the case where the selection number of the selector 90 changes sequentially according to the output of the counter 91 in FIG.
In FIG. 17, since the fixed priority information is output from the selector 106, the selector 90
The FO memory is selected to perform data transfer. In this example, the selector 90 (HIGH) at the top of FIG. 17 is selected.

Then, the data is sent to the selector SEL86 shown in FIG. 16 via the fixed priority circuit 92, the encoder 93, and the adder (ADD) 94. The selector SEL86 selects the memory in the uppermost column of the FIFO memory 85, and Transfer to each output terminal of SRM _{31 to} SRM _{3N / n} .

In this way, for a call requiring immediacy, a priority route is designated and control is performed so that it can be easily transferred within each module.

Next, priority transfer processing when the FIFO memory as a buffer in each module exhibits an overloaded state will be described. The selector control circuit SC97 in FIG. 16 receives transfer requests (* 1 to ** n) (same as R in FIG. 7) from the FIFO memory 85, but the storage status of each FIFO memory 85 is also excessive. These are input as load signals ## 1 to ## n. This overload signal can be set on the basis of when the FIFO memory 85 stores information of a certain value or more. Therefore, the controller 105 shown in FIG. 17 receives the overload signals ## 1 to ## n and sends them as master information to the processor MPU via the signal distributor SD101. Since the processor MPU to read detailed information via a further signal splitter SD to analyze this master information (Δ1~Δn), for discharging the information from the FIFO memory 85 in the overload state preferentially, the control signal S _c To control the selectors 106 and 90.

Therefore, assuming that, for example, the FIFO memory in the uppermost column of the FIFO memories 85 in FIG. 16 is overloaded, each of the selectors 90 in FIG. 17 is controlled so that the transfer request * 1 is selected. It will be. When there are a plurality of FIFO memories in the overload state, the FIFO memory is selected by the fixed priority circuit 92.

In this case, even if an overload condition occurs, the processor MPU1
Rewriting of the routing header by 5 and the additional circuit (11) is not performed. This is to prevent the order of the flow of each packet from being reversed.

In this way, the packet information stored in the overloaded FIFO memory 85 is preferentially sent out from each module SRM without changing the route.

Next, a specific configuration example for improving the memory use efficiency in the self-routing switch module (SRM) in FIG. 8A will be described.

FIG. 18 is a principle block diagram of a second embodiment of the self-routing communication channel. The self-routing switch module SRM shown in FIG. 7 includes a FIFO memory for avoiding packet collision in which transfer information, for example, packets are concentrated at the same output terminal. For example, when the number of input terminals and the number of output terminals are N, respectively. , This FIFO memory needs N ² pieces. Therefore, as the number of incoming and outgoing lines increases, the number of required FIFO memories will increase exponentially. The content stored in the FIFO memory is the entire packet, and the FIFO memory is capable of storing multiple packets in order to have a buffer function.
Considering setting the storage capacity of FO memory, FIFO
A memory having a large storage capacity is required. However, even if the storage capacity of the FIFO memory is set to be large in this way, the probability of occurrence of packet collision is not high.
In other words, the probability that packets to be output to the same outgoing line arrive at each incoming line at the same time is not high, so that not all of the FIFO memory storage area for packet queuing is normally used, and the memory usage efficiency is not high. Is not high.

Therefore, the second embodiment provides a self-routing communication path that can cope with an increase in the number of incoming and outgoing lines without greatly increasing the number of memory means, and that can use the memory means with high efficiency. In FIG. 18,
A plurality of incoming lines # 1 to #N and a plurality of outgoing lines # 1 to #N,
A self-routing communication path that autonomously switches transmission information added with a routing header input to each incoming line to an outgoing line specified based on the routing header, and is input in parallel from a plurality of incoming lines. Converting means 111 for converting the transmission information into a time serial form; converting means 111
Transmission information storage means 112 for sequentially storing the transmission information T · INF sequentially transmitted from the storage means, and a write address for storing an address for accessing the transmission information storage means 112 and sequentially giving the transmission information storage means 112 as a write address An output unit 113, a plurality of read address storage units 114 (1) to 114 (M) respectively provided for a plurality of outgoing lines, and an address for accessing the unit 112, which is sent from the write address output unit 113. The routing header of the transmission information
Based on the RH, the read address storage means 114 corresponding to the outgoing line specified by the routing header stores, as a read address, an address distribution means 115 for storing the read address and a plurality of read address storage means 114 (1) to 114 (M). Addresses are sequentially selected, and the storage addresses are given to the transmission information storage means 112 as read addresses and stored in the write address output means 113, and the transmission information storage means 112 is selected by the address selection means 116.
And distribution means 117 for distributing the transmission information sequentially read out from the read lines to the outgoing lines corresponding to the selected read address storage means 114.

Transmission information such as packets input to a plurality of incoming lines is converted into a serial data format by the conversion unit 111 and stored in the transmission information storage unit 112 sequentially. At this time, the address designation to the transmission information storage means 112 is based on the address given from the write address output means 113. At the same time as the address designation, the address from the write address output means 113 is transferred by the address distribution means 115 to the read address storage means 114 corresponding to the outgoing line specified by the routing header RH of the transmission information written at the address position. Is stored. In this way, the transmission information storage unit 112 stores each transmission information. Further, an address for reading the transmission information is stored in the read address storage means 114 corresponding to the transmission destination and outgoing line of the transmission information stored in the transmission information storage means 112.

The address selection means 116 is a read address storage means 114
The stored read addresses are sequentially read from (1) to 114 (M), and are used by using the read information.
The transmission information is read from 2 and the read transmission information is distributed by the distribution means 117 to the outgoing line corresponding to the transmission destination of the transmission information. Read address storage means 114 (1) -114
The read address read from (M) is stored again in the write address output means 113 and is used for address designation of the transmission information storage means 112.

FIG. 19 is a circuit diagram showing a concrete example for realizing the second embodiment of FIG. 18, and the time division multiplexing unit (MUX) 121 has N input lines #.
1 to #N, and time-division multiplexes the packets P (1) to P (N) input in parallel to each of the incoming lines # 1 to #N to form a time-sequential form. To send to. The input highway HW1 is connected to a data input terminal DI of a random access memory (RAM) 122,
The packets on the incoming highway HW1 are sequentially stored in M122. The address specification for the RAM 122 is performed using the address stored in the free address memory 124. The free address memory 124 is constituted by a FIFO memory, and has a capacity capable of storing a number of addresses corresponding to the number of addresses of the RAM 122.

The address output from the free address memory 124 is RAM
122 write address input terminal WA and address distribution unit (D
S) Guided to the input of 126. The address distribution unit 126 is switched and controlled by a routing header copy unit (RHC) 128 to store the input address in a FIFO memory 125 for an output terminal.
(1) to 125 (M). FIFO memory 125
(1) to 125 (M) are provided corresponding to the M outgoing lines # 1 to #M accommodated in the time division multiplexing / demultiplexing section 123, respectively, and the outgoing lines # 1 to #M are provided. Has a capacity capable of storing a plurality of addresses for avoiding a packet collision. The routing header copy unit 128 is connected to the incoming highway HW1 and is configured to read the routing header RH of the packet on the incoming highway HW1 and supply it to the address distribution unit 126.

The contents of the FIFO memories 125 (1) to 125 (M) are sequentially selected and read by an address selection unit (SEL) 127,
It is sent to the read address input terminal RA of the RAM 122 and the input terminal of the free address memory 124. Data output terminal D of RAM122
The packet information read from O is sequentially sent to the outgoing highway HW2. The packet information on the outgoing highway HW2 is input to the time division multiplexing / demultiplexing section 123, where it is sequentially distributed to outgoing lines # 1 to #M. The time division multiplexing unit 121, the address selection unit 127, and the time division multiplexing / demultiplexing unit (DMX) 123 are operated at the timing of the clock from the clock source (CLK) 129.

The operation of the second embodiment will be described below. Now, packets P (1) are input to incoming lines # 1 to #N of the time division multiplexing unit 121, respectively.
~ P (N) has been input. Each packet P
(1) to P (N) consist of transmission information T.INF and a routing header RH. The time division multiplexing unit 121
(1) to P (N) are time-division multiplexed, rearranged into a serial data sequence in time, and transmitted to the incoming highway HW1. Therefore, the data speed on incoming highway HW1 is
N times the data rate on N.

These packets P (1) to P (N) are sequentially stored in the RAM 122. At this time, the address specification for the RAM 122 is performed by using addresses sequentially read from the free address memory 124 as write addresses.
The address read from the free address memory 124 is RAM
122, and at the same time,
It is stored in one of the FO memories 125 (1) to 125 (M).

That is, the routing header copy unit 128 reads the routing header RH of each of the packets P (1) to P (N) on the incoming highway HW1, and outputs the packet to any of the outgoing lines # 1 to #M according to the routing header RH. Identify what should be done. The switching control of the address distribution unit 126 is performed by using the routing header RH, and the address transmitted from the free address memory 124 is stored in the FIFO corresponding to the outgoing line to which the packet stored in the corresponding address position of the RAM 122 is to be transmitted. It is stored in the memory 125.

For example, when the destination of the packet P (1) input to the incoming line # 1 is the outgoing line # 2, the packet P (1) is designated by the RAM 122 specified by the address from the free address memory 124.
At the same time, the address is distributed to the FIFO memory 125 (2) corresponding to the outgoing line # 2 to which the packet P (1) is transmitted under the control of the routing header copy unit 128 and the address distribution unit 126. Stored. If a plurality of packets to be sent to the outgoing line # 2 exist at the same time and a collision occurs, the FIFO memory 12
5 (2) stores the plurality of addresses.

In this way, the packet P
(1) to P (N) are sequentially stored, and at the same time, the address information of the RAM 122 in which these packets P (1) to P (N) are stored is determined by the address information of each packet P (1) to P (N). The outgoing line address corresponding to the outgoing line of the transmission destination is stored in the FIFO memory 125.

The reading of the packets P (1) to P (N) stored in the RAM 122 is performed by the address selecting unit 127 at the timing according to the clock from the clock source 129, and the FIFO memories 125 (1) to 125 (
(M) is sequentially selected in that order, the address stored therein is read, and the read address is given to the RAM 122 as a read address. As a result, packets are sequentially transmitted from the RAM 122 to the time division demultiplexing unit 123 via the highway HW2. This address selector
The address selected at 127 is simultaneously sent to and stored in the free address memory 124, and is used again as a write address of a packet to the RAM 122.

The time division multiplexing / demultiplexing unit 123 is, for example, a FIFO memory 125 (1).
The packet read at the address from
Packets read at addresses from the FO memory 125 (2) go to the outgoing line # 2, packets read at addresses from the FIFO memory 125 (k) go to the outgoing line #k, and so on. To the outgoing lines # 1 to #M. As a result, the packets P (1) to P (N) input to the input lines # 1 to #N are sent to the destination output lines specified by the respective routing headers RH.

Thus, according to FIGS. 18 and 19, the memory means required to configure the self-routing communication path includes a memory such as a RAM for storing packets, and a free address memory for storing a free address of the RAM. In this case, the output address memories 125 for the number of output lines for storing the read addresses of the RAM may be used. As a result, even if the number of incoming lines and outgoing lines of the self-routing communication path increases, the number of necessary memory means can be significantly reduced. This effect becomes more remarkable as the number of incoming lines and outgoing lines increases. Also, an empty address memory 124 and an outgoing line address memory 125
Can be configured with a small capacity enough to store the address of the RAM 122. RAM 122 for storing packet information
Can be used more efficiently. When the capacity of the RAM is very large, the free address memory 124 is unnecessary.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-routing (asynchronous transfer mode) switching system for a network (high-speed packet switching network or asynchronous transfer mode switching network) for transmitting packets such as voice, facsimile data, computer data, etc. in packets or cells. Available to

 ──────────────────────────────────────────────────続 き Continued on front page (31) Priority claim number Japanese Patent Application No. 62-63555 (32) Priority date March 18, 1987 (33) (33) Priority claim country Japan (JP) (31) Priority Claim number Japanese Patent Application No. 62-120296 (32) Priority date May 19, 1987 (33) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 62-121054 (32) Priority Date 1987 May 20 (1987) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 62-176466 (32) Priority date July 62 (1987) July 15 (33) ) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 62-175950 (32) Priority date July 16, 1987 July 16, (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 62-231816 (32) Priority date September 16, 1987 (1987) (33) Country claiming priority Japan (JP) (31) Priority claim number Japanese Patent Application No. 62-231817 (32) ) The other day 1987 September 16 (1987) Priority Japan (JP) (72) Inventor Shunji Abe 1-10-9 Kamiooka Nishi, Konan-ku, Yokohama-shi, Kanagawa Prefecture New Perth Kamiooka 606 (72) Inventor Tetsuo Nishino 8-13 Yashiro Nakamachi, Shinjonakamachi, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 303 (72) Inventor Toshimasa Fukui 1885-3, Kitsuki-Sumiyoshicho-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 3-3, 32-32 Kitsuki Sumiyoshi Danchi 3-72 (72) Inventor, Osamu Isono 452 Mizonokuso, Takatsu-ku, Kawasaki-city, Kanagawa Prefecture (72) Tetsuo Tachibana Inventor 1-4-39 Kamishinjo, Nakahara-ku, Kawasaki-shi, Kanagawa 1-41 First Shinshiro dormitory (72) Inventor Eisuke Iwabuchi 2-Rokuura, Kanazawa-ku, Yokohama-shi, Kanagawa 4-14 (72) Inventor Shichiro Hayami 4-9-6 Hodgaya Mansion 408, Nagatsuda, Midori-ku, Yokohama-shi, Kanagawa Prefecture (56) References JP-A-61-84945 (JP, A) JP-A-61-72448 ( JP, A) JP-A-57-164642 (JP, A) JP-A-59-135994 (JP, A) JP-A-58-222640 (JP, A) JP-A-61-127250 (JP, A) JP-A-62-11344 (JP, A) IEEE J. J. on Selected Areas in Communications, SAC-4 [8] (1986) p. 1373-1380, The 6th Annual Symposium on Computer Architecture (1979), IEEE, p. 202-215 International Journal of Electronics, 56 [6] (1984) p. 815-822 International Publication No. 86102512 Pumplet (1986) IEEE Trans. on Com puters, C-34 [2] (1985) p. 180-186 IEEE Globecom'84, (1984) "Starlite: A Wide Digital Switch" p. 121-125 IEICE Technical Report 86 [290] (1986-12-19) [Exchange] SE86-115, P.A. 1-6 IEICE Technical Report 86 [243] (1986-11-28) [Exchange] SE86-105, p. 31-36

Claims (2)

(57) [Claims] 1. An information processing apparatus, comprising: transmitting transmission information including identification information input from an input line to an output line specified by the identification information, based on control information indicating a path from the input line to the output line; In a self-routing switching system for transmitting transmission information from the incoming line to the outgoing line, a transmission information storing means for sequentially storing the transmission information from the incoming line which is sequentially input in a time serial form; Write address output means for outputting a write address for storing information in the transmission information storage means; and output from the write address output means. A read address storage unit for storing a write address of the transmission information storage unit as a read address to the transmission information storage unit in correspondence with the outgoing line specified by the control information; and a storage address in the read address storage unit. Means for giving the read address corresponding to the outgoing line to the transmission information storage means, and transmitting the transmission information read from the transmission information storage means to the outgoing line corresponding to the read address, The self-routing exchange system, wherein the write address output means uses the read address output to the transmission information storage means as a write address to be provided to the transmission information storage means. 2. A method for transmitting a cell containing identification information input from an incoming line to an outgoing line specified by the identifying information, based on control information indicating a path from the incoming line to the outgoing line. An asynchronous transfer mode switching system for transmitting cells from the incoming line to the outgoing line, wherein the multiplexing means outputs the cells from the incoming line in a time-serial format; and Storage means for storing cells; write address output means for providing a write address for storing the cells in the storage means; write address of the storage means output from the write address output means; Read address storage means for storing as a read address to the storage means, corresponding to the outgoing line designated by the following, and a storage address in the read address storage means. Address selecting means for giving the read address corresponding to the outgoing line to the storing means, and distributing means for distributing the cells read from the storing means to the outgoing line corresponding to the read address, The asynchronous transfer mode switching system according to claim 1, wherein said write address output means uses said read address output from said address selection means as a write address given to said storage means.