JPH04180433A - Cell exchange device - Google Patents

Abstract

PURPOSE:To improve the buffer operating efficiency by managing a storage address to a cell buffer memory by each output port so as to prevent the cell from being in excess of the capacity of an output port when the cell is read from the buffer memory. CONSTITUTION:When a cell is inputted to an incoming line 1, a header processing circuit 10 detects an output port and outgoing line from a cell header part. A buffer control circuit 15 references the circuit 16 to give a command of connecting the circuit 10 receiving a cell and a selected buffer memory 11 to a cell write circuit 13. The circuit 15 sends a stored address to a storage circuit 12 corresponding to a relevant memory 11 and gives a command of connection of the memory 11 and the outgoing line 2 individually to a cell read circuit 14. In this case, the cell is read in matching with a speed of the output port to prevent the capacity of the output port from being exceeded. The circuit 14 connects the memory 11 and the outgoing line 2 in this time slot. The cell read from the memory 11 is outputted to the outgoing line 2 of the designated destination output port.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a method for dividing various information such as voice, data, and images into blocks called cells and transmitting and exchanging them at high speed in the information and communication field. ATM
This invention relates to a cell switching device in ous Transfer Mode) communication.

[Prior art] ATM (Asyn
In chronous transfer mode) communication, a unit called a cell is used in which multimedia information is divided into blocks and a header including destination information is added. This cell has a fixed length determined according to international standards. On the other hand, the interface speed in the ATM communication system is basically 155.52 Mb/s, and some speeds that are integral multiples of 155.52 Mb/s, such as 622.
08Mb/s etc. are becoming an international standard.

In ATM switches that directly refer to and exchange cell header information using hardware, cell multiplexing/demultiplexing circuits are sometimes used at the input/output sections of the ATM switch in order to accommodate interfaces different from the switch interface. many. Figure 9 shows Hayami et al.'Broadband l5DN
"ATM Switching System", Technical Research Report of the Institute of Electronics, Information and Communication Engineers.

Vol, 90 No, 158, 5SE90-40. pp
, 13-18.1990 is a configuration diagram of a prototype system. In addition, FIGS. 10, 11, and 12 show the ATM switch module, cell multiplex circuit, and
FIG. 2 is a configuration diagram of a cell separation circuit. In the figure, (1) is the incoming line, (2) is the outgoing line, (3) is the ATM switch, (4) is the cell multiplexing circuit, (5) is the cell separation circuit, (6) is the input port, and (7) is the Rokaport, (8) is a cell exchange device, (
31) is an ATM switch module, (32) is a buffer, and (33) is a highway.

Next, the operation will be explained.

Figure 9 shows the configuration of a prototype system. The example shown here integrates the basic components of a broadband I5DN: a broadband home network, a broadband remote concentrator, and a broadband local exchange. Now, the broadband remote concentrator will be explained. The communication path of the device is composed of an ATM switch (3), a cell multiplexing circuit (4), and a cell separation circuit (5) in addition to the interface section. Information generated in the house is divided into blocks of a certain length to form cells, which arrive at the broadband remote concentrator through optical subscriber lines, and are first input to the input port (6) of the cell multiplexing circuit (4). do. The interface speed of this optical subscriber line is 1, which is the international standard.
It is 55.52 Mb/s. On the other hand, ATM switch (3
) has an interface speed of 1.2 Gb/s, and although it cannot directly accommodate optical subscriber lines, it has a capacity that can accommodate eight optical subscriber lines.

Therefore, the cell multiplex circuit (4) shown in FIG.
55.52 Mb/s input ports (6) are multiplexed in cell units and connected to AT as one 1.2 Gb/s interface.
Output to input line (1) of M switch (3). The cell multiplex circuit (4) is composed of ATM switch modules (31) corresponding to the number of input ports. Cell multiplexing involves storing cells in a buffer (32) within an ATM switch module (31), and coordinating with other ATM switch modules (31) to prevent cell collisions on the incoming line (1). Cell multiplexing is performed by reading cells at a high speed from the buffer (32) to avoid this problem.

Next, referring to FIG. 10, the operation of the ATM switch module will be explained. The ATM communication path consists of arranging the ATM switch modules (31) in a grid pattern with one
．． The network is connected by a 2Gb/s highway (33). The ATM switch module (31) with 1.2 Gb/s interface is capable of 8x8 exchange. In the ATM communication system, cells are multiplexed aperiodically and are input from multiple incoming lines aiming at one outgoing line.
Collisions of cells on lines can occur. To avoid this,
A function is required to temporarily wait for cells using a buffer. Each ATM switch module (31) is
It is connected to other ATM switch modules (31) by an output highway (33), and each ATM switch module (31) is provided with a buffer (32). ATM
When a cell is input to the switch module (31), it is determined whether to perform switching by comparing the routing information added to the cell with the output highway number set in each ATM switch module (31). If the routing information and the set highway number match, the cell is stored in the buffer (32). Also, when reading and comparing cells from the buffer (32), each ATM
Arbitration is required between the switch modules (31), and this multiplex control is performed by circulating tokens. In addition, the highway (33) that accommodates cells output from all ATM switch modules (31) is connected to the outgoing line (
2) and input to the cell separation circuit (5).

Next, referring to FIG. 12, the operation of the cell separation circuit will be explained. The cell separation circuit (5) has a function of separating cells into a plurality of output ports (7) for one output line (2). The cell flow arriving at the outgoing line (2) is statistically cell-multiplexed, and the cells destined for each output port do not arrive regularly, but the rate varies over time. Therefore, the cell separation circuit (5) requires a large number of buffers to absorb the fluctuations, so in the figure, a plurality of ATM switch modules (31) are provided for one output port (7). ing. In the figure, when a cell is output from the output line (2) of the ATM switch (3) and arrives at the cell separation circuit (5), each ATM switch module (31) determines the output port by checking the cell destination. If (7) matches, the cell is written to the buffer (32). The speed of reading 1M in this buffer (32) is 1.2
Gb/s, but reading is 155.52 Mb/s, so if a large number of writing cells arrive in succession, the amount of the buffer (32) is finite, so the buffer (32) overflows and cells are discarded.

[Problems to be Solved by the Invention] Since the conventional cell switching device is configured as described above, a sufficient number of When preparing buffers (32), it is necessary to install a large number of buffers (32) corresponding to each output port (7), and as a result, a large number of buffers are installed with poor usage efficiency in the entire system. There was a problem that it became difficult to implement.

This invention was made in order to solve the above-mentioned problems.When reading cells from an ATM switch to a cell separation circuit, the capacity of each output port is taken into account and the capacity is not exceeded. ATM
By absorbing this with the buffer of the switch, the buffer in the ATM switch is shared between each output port, and the purpose is to increase buffer usage efficiency and reduce the total buffer amount of the entire system.

[Means for Solving the Problems] A cell switching device according to the present invention has a plurality of incoming lines into which a cell consisting of a data part and a header part including destination information is input, and a cell that is input from the incoming line is connected to the cell. A to output to the outgoing line that accommodates the output port specified in the header of
a TM switch, a cell multiplexing circuit that multiplexes cells in a plurality of input ports into which the cells are input, cell by cell, and outputs the cell to the input line; The ATM switch has a cell separation circuit that selects and outputs an output port that is input from an input line, and the ATM switch includes a header processing circuit that detects a destination output port from the header part of a cell input from an input line, and a cell separation circuit that selects and outputs an output port. One or more buffer memories into which the cell can be written by specifying an address and which can be read out irrespective of the writing order by specifying an address; A cell write circuit connects the buffer memory to a predetermined output line to write cells into the buffer memory, a cell read circuit connects the buffer memory to a predetermined output line and reads cells from the buffer memory, and controls the cell write circuit to write cells into the buffer memory. In addition to selecting the buffer memory to be written, the address of the written cell in the buffer memory is managed for each destination output port of the cell, and the cell reading circuit is controlled based on the address managed for each destination to send the cell to the output port. The buffer control circuit reads the cells according to the speed of the buffer and outputs the read cells in a predetermined order to the outgoing line that accommodates the output port specified by the header.

[Function] The cell switching device according to the present invention manages storage addresses of cells in a buffer memory in an ATM switch for each output port, and prevents cells from exceeding the capacity of the output port when reading cells from the buffer memory. AT eliminates cell waste in the separation circuit and absorbs cell fluctuations
By using the buffer memory in the M switch, the buffer memory can be shared by all output ports.

A lower cell discard rate can be achieved with a smaller number of buffer memories in the entire system.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram showing a cell switching device according to this embodiment. This cell switching equipment W (8) has 32 input ports (6) of 155.52 ab/s through which cells input and 32 output ports (7) of 155.52 ab/s that output cells. ) to exchange cells between them. Also,
This cell switching device (8) connects a 155.52 ab/s input port (6) to one 622.08 ab/s incoming line (
1), 8 cell multiplexing circuits (4) for cell multiplexing, and 6
22.08 AB/s interface with 8 incoming lines (1)
And 8 out, i! (2) ATM switch (
3) and one 622.08ab/s outgoing line (2) to 4
The 155.52 Mb/S output port (7) is equipped with eight cell separation circuits (5) for separating cells.

FIG. 2 shows an embodiment of the ATM switch (3). In the same figure, (1) is a cell multiplexed with n (n≧2) input ports into which a cell consisting of a header section including an output port number as destination information and a data section is input.
The input line (2) is m that accommodates the output port to which the cell should be output according to the destination specified in its header.
There are (m≧2) outgoing lines, which are equivalent to the conventional one. A header processing circuit (10) is provided corresponding to each of the input lines (1) and detects the destination output port (7) from the header part of the cell input from the input line (1). In addition, (11) stores the cells at a specified address, and by specifying the address, the stored cells can be read out regardless of the order in which they are written. It is buffer memory.

(12) is provided corresponding to each of the buffer memories (11), and manages free addresses using, for example, a FIFO type memory, and writes read addresses and write addresses to the associated buffer memories (11). This is a memory control circuit that provides (13) is a cell write circuit that selectively connects the header processing circuit (10) to a predetermined buffer memory (11), which is realized by a space switch in this embodiment. (14) is a cell readout circuit that selectively connects each buffer memory (11) to a predetermined output line (2), and in this embodiment is realized by a space switch. (1
5) controls the switching of the cell write circuit (13) to select the buffer memory (11) in which cells are stored, and also selects the buffer memory (11) for storing the stored cells.
11) The above address is managed for each output port of each cell, and the switching of the cell readout circuit (14) is controlled based on the address managed for each destination, and the cell is This is a buffer control circuit that causes output lines (2) that accommodate output ports (7) to output in a predetermined order.

Further, in the buffer control circuit (15), (1
6) When a cell arrives at the incoming line (1).

A header processing circuit (
10) receives the outgoing line number of the cell detected by
A write buffer selection circuit controls switching of the cell write circuit (13) in order to select a buffer memory (11) for storing the cell and connect it to a corresponding header processing circuit (10). (17) refers to the output port number detected by the write buffer selection circuit (16), sorts the arriving cells by destination output port, and stores the cells in the buffer memory (11) into which the cells are written.
This is an address exchange circuit that obtains the above write address from a storage control circuit (12) corresponding to the buffer memory (11) and writes it to an address queue to be described later.

The address queue (18) is constituted by a FIFO type memory and is provided corresponding to the output port accommodated by each of the output lines (2).

In this address queue (18), for each output port to which it is associated, write addresses on the buffer memory (11) in which cells destined for that output port are stored are stored in the address queue (18) in the order in which they arrive. Written by the switching circuit (17). (19) refers to this address queue (18) to determine the cell to be read from the buffer memory (11), and uses the address read from the address queue (18) as a read address to the corresponding buffer memory (11). Associated storage control circuit (1
2) and controls the switching of the cell read circuit (14) to connect the buffer memory (11) to the corresponding output line (2).

Figure 3 is an example of the internal circuit of a cell multiplexing circuit, in which four 155.52 Mb/s input ports (6) in Figure 1 are cell multiplexed to one 622.08 Mb/s input line (1). It is. In the figure, one FI corresponds to input port (6)
A cell speed adjustment buffer (21) consisting of FO type memory is used, and the write speed is 155.52 Mb/s.
, read out sequentially at 622.08 Mb/s.

Figure 5 is an example of the internal circuit of the cell separation circuit, in which one 622.08 Mb/s output line (2) in Figure 1 is replaced with four 15
This is an example of cell separation into 5.52 Mb/s output port (7). In the figure, one FI corresponds to the output port (7).
A cell speed adjustment buffer (23) and address filter (22) composed of FO type memory are used, and the writing speed is 622.08 Mb/s and the reading speed is 155.52 Mb/s.
It runs at Mb/s. Cell speed adjustment buffer (21)
, (23) is intended only for speed adjustment and does not expect the statistical multiplexing effect of cells, so its capacity is sufficient for at most two cells.

Next, the operation of the cell multiplexing circuit will be explained.

The cell length handled here is a fixed length and is input randomly, and the cell input phase is adjusted before inputting to the input port (6) so that the cell input from all lines is supplied with the same phase. shall be FIG. 4 is a timing diagram of this circuit example, in which the input port (6) in FIG. 3 is designated as A, the input line (1) is designated as B, and each cell is shown. A
In the TM communication system, a significant cell may appear in a certain time slot, and an idle cell (empty cell) having no information may appear in a certain time slot. In the figure, significant cells are indicated by "cells", etc., and idle cells (empty cells) are clearly indicated as "idle cells". The transfer time for one cell at 622.08 Mb/s is one quarter of that at 155.52 Mb/s, and all cells input from the input port (6) are transferred to the input line (1
) has the capacity to accommodate. Here, 155.52Mb
622.08 Mb in units of 1 cell time at /s
A system is adopted in which input ports (6) are fixedly assigned to four cells of /s at their temporal positions. For example, a cell input from input port #1 (6) is 6 at position #1 in the diagram.
The output speed is set to 22.08 Mb/s.

Next, the operation of the ATM switch will be explained with reference to FIG. Here, it is assumed that the input phase of the cell at each incoming line (1) input to the switch is adjusted and is the same. Incoming line (1
), the header processing circuit (10) provided corresponding to each input line (1) detects the output port and the output line number that accommodates it from the header section of the input cell. The write buffer selection circuit (16) in the buffer control circuit (15) refers to the header processing circuit (10) and sends the cell to the cell write circuit (13) and the header processing circuit (10) where the cell has arrived. Instructs to individually connect the buffer memories (11) selected for storage. The write address used at this time can be obtained by referring to the storage control circuit (12). This write address is sent to the address exchange circuit (17), and each incoming line (
1) according to the destination output port (7) of the cell arriving at the cell. An address queue (18) is provided for each output port, and the write address and buffer memory number of the cell are written at the end thereof. The read buffer selection circuit (19) selects these address queues (18).
Then, the memory control circuit (11) corresponding to the corresponding buffer memory (11) extracts the address stored there.
12), and also instructs the cell readout circuit (14) to connect the buffer memory (11) and the output line (2) individually. In general, the capacity of the outgoing line (2) and the capacity of the output port (7) are different, but the address queue (1
Since the reading in 8) is performed for each output port, the reading is compared in accordance with the speed of the output port so as not to exceed the capacity of the output port (7). The cell readout circuit (14) reads the buffer 7 memory (
11) and the outgoing line (2). Each storage control circuit (12
) sends the received address to the associated buffer memory (11) as a read address, and thereafter manages that address as a free address. The cells read from each buffer memory (11) are output to the outgoing line (2) that accommodates the destination capacity port (7) specified in the respective header section.

Here, FIGS. 7 and 8 are examples showing in detail the reading of the address queue (18) regarding the outgoing line #1 (2). Output line #1 (2) accommodates output ports #1 to #4 (7) of 155.52 Mb/s, so 622
．． It has a speed of 0.08Mb/s. FIG. 7 is an example of the address queue (18) corresponding to output ports #1 to #4 (7) in a certain time slot, where 'cell 11' etc. indicate the cell. The stored buffer memory number and address are written. Figure 8 shows the read rule for the address queue (18) in the present invention. The figure shows the timing in the outgoing line (2). This differs from the conventional method in that cells destined for output ports #1 to #4 (7) are fixedly assigned to each 4-cell unit.For example, in the figure, time slots 1 to 4 are assigned to output ports, respectively. It is assigned to #1 to #4 (7) and is repeated.Therefore, the cell separation circuit (5) only needs to periodically adjust the speed, and the cell separation circuit (5) is allocated to No cell discard occurs.For example, in FIG. 7, cell 41 is currently waiting to be output to output port #1, cell 11.#2, cell 21.#4.

Therefore, they are read out regularly in time slots 1°2.4. In timeslot 3, output port #
Since the cell addressed to No. 3 has not arrived, an idle cell (indicated as "empty cell" in the figure) is sent. In an example of the invention:
The address queue (18) is provided corresponding to the output port (7), but in the conventional example there is one large queue for the outgoing line (2). If this is applied, other significant cells will be output in time slot 3, so no empty cells will be output, and output port #1. #2. Any one of #4 will be duplicated, and it will be necessary to buffer it in the cell separation circuit (5). That is, in the conventional example, statistical fluctuation occurs in the arrival of cells to one output port (7), and a large amount of buffer is required in the cell separation circuit (5).

Next, the operation of the cell separation circuit will be explained.

FIG. 6 is a timing diagram in this circuit example, and the fifth
The output line (2) in the figure is C1, and the output port (7) is D, and each cell is shown. In the figure, as in Fig. 4, significant cells are indicated by "cell ■", etc., and idle cells (empty cells) are clearly indicated as "idle cells".622゜08M
The transfer time for one cell at b/s is 155.52 Mb/s.
It is one quarter of that of s. The outgoing line (2) transmitted from the ATM switch (3) is 622.08 Mb/s, but one cell time at 155.52 Mb/s is taken as a unit, and the temporal position of 4 cells of 622.08 Mb/s is Since the output port (7) is fixedly assigned in the cell separation circuit (5), the cell input to the cell separation circuit (5) is guaranteed to have the output port (7) and time slot to which it will be output, and no buffer overflow will occur here. It looks like this. Cell separation circuit (
Cells input to 5) are first broadcast to the address filter (22) provided corresponding to the output port (7), and are then broadcast to the address filter (22) provided corresponding to the corresponding output port (7).
22) only allows the cell to pass through the rate adjustment buffer (22).
Write in 3). Another address filter (22) discards the cell. The cell speed adjustment buffer (23) is
Writing is performed at 622.08Mb/s, reading speed is 1
The speed is adjusted by performing it at 55.52 Mb/s. The cell speed adjustment buffer (23) is for speed adjustment only;
Since statistical multiplexing effects of cells are not expected, the capacity is sufficient for two cells at most.

In the above embodiment, a single cell switching device is shown, but the cell switching device may be linked and sequentially connected in multiple stages for expansion.

In addition, as the destination information in the cell header section, it was assumed that the output port number was directly given in correspondence with the output port of the cell switching device, but some conversion processing, such as giving a coded number to the destination information in the header section, was applied. You may go.

Furthermore, in the above embodiment, a case was explained in which one cell is output to only one output port, but it is also possible to output to multiple output ports depending on how the address is specified. It is also possible to add functions.

Alternatively, the header section and the data section may be structurally separated and transmitted using circuits with different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Furthermore, in the above embodiment, the incoming link speed is the same, but traffic can be concentrated by making the reading speed from the buffer memory faster than the incoming link speed, and vice versa. It is also possible to increase the speed.

Furthermore, when the cell switching devices are linked together, by making the speed between the stages higher than the incoming line speed, the cell discard rate between the stages of the cell switching device can be further reduced.

In the above embodiment, one address queue is provided for each output port of the cell switching device, but a plurality of address queues are provided for each output port on the priority side, and the header section of the cell is It is also possible to read cells with a high priority from the buffer memory first based on a code indicating priority added to the cell other than the destination line.

Furthermore, if operating speed restrictions are required, serial/parallel conversion circuits are installed before and after this switch.

A parallel/serial conversion circuit may be added to process the signals as parallel signals.

[Effects of the Invention] As described above, according to the present invention, a plurality of cells inputted from a plurality of input ports are multiplexed by a cell multiplexing circuit, and A
When exchanging cells with the TM switch and outputting the cells to the outgoing line, the time slot in which the cells are output is fixedly assigned to the output port, thereby eliminating cell discard due to buffer overflow in the cell separation circuit. When outputting cells from the ATM switch to the cell separation circuit, it is now possible to ensure that the capacity of each output port is not exceeded.
By absorbing temporal fluctuations in cell arrival with the buffer of the ATM switch, the buffer in the ATM switch can be shared among each output port, increasing buffer usage efficiency and reducing the total amount of buffer in the entire system. This has the effect of providing a cell switching device that can realize the discard rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire cell switching device according to an embodiment of the present invention, FIG. 2 is a block diagram showing its ATM switch, FIG. 3 is a diagram showing an example of the internal circuit of a cell multiplexing circuit, and FIG. 5 is a timing diagram of each part, FIG. 5 is a diagram showing an example of the internal circuit of the cell separation circuit, FIG. 6 is a timing diagram of each part, FIG. 7 is a diagram showing an example of an address queue in an ATM switch, Figure 8 is a timing diagram of the outgoing line, Figure 9 is a system configuration diagram using a conventional cell switching device, Figure 10 is a block diagram showing the configuration of an ATM switch module in a conventional example, and Figure 11 is a diagram showing the configuration of an ATM switch module in a conventional example. A block diagram showing the configuration of a cell multiplexing circuit, and FIG. 12 is a block diagram showing the configuration of a conventional cell separation circuit. (1) is the incoming line, (2) is the outgoing line, (3) is the ATM switch, (4) is the cell multiplexing circuit, (5) is the cell separating circuit, (6
) is an input port, (7) is an output port, (8) is a cell switching device, (10) is a header processing circuit, (11) is a buffer memory, (12) is a storage control circuit, and (13) is a cell writing circuit. , (14) is a cell read circuit, (15) is a buffer control circuit, (16) is a write buffer selection circuit, and (17) is an address exchange circuit. (18) is an address queue, (19) is a read buffer selection circuit, (21) and (23) are cell speed adjustment buffers, and (22) is an address filter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Patent Attorney Jun Miyazono - Figure 10 Output Line 411 De Accommodation T9 Nagi Kaport 1 to 14 Corresponding Ar゛FIFO Quit 7 Somojichi Exchange 3 Incision 2 (11-+ Cut 22 Hanging 211 Nanayama #Pl/ s Otsuro t Le output trimmer (see Figure 7, No. 7)? J Shaise χ Non-rainbow anastomosis fitting head slot + 234567 )-12 versus Kei〉 By output "-)-113 Ribiki〉 Output wide-toe I4 kite

Claims (1)

[Claims] A cell consisting of a data part and a header part containing destination information has a plurality of input lines, and the cell input from the input lines is accommodated in the output port specified in the header part of the cell. an ATM switch that outputs to the outgoing line, a cell multiplexing circuit that multiplexes cells in a plurality of input ports to which the cells are inputted in cell units, and outputs the cells to the incoming line; A cell switching device having a cell separation circuit that selects and outputs an output port specified by the header section, the ATM switch having a cell separation circuit that selects and outputs an output port specified by the header section, the ATM switch detecting a destination output port from the header section of the cell input from the incoming line. a processing circuit, one or more buffer memories in which the cells can be written to by specifying an address, and read from the cells by specifying an address regardless of the order of the writes; and the header processing; a cell write circuit that connects a circuit to a predetermined buffer memory and writes cells into the buffer memory; a cell read circuit that connects the buffer memory to a predetermined output line and reads cells from the buffer memory; and the cell write circuit. controls to select the buffer memory into which the cell is written, and also manages the address of the written cell in the buffer memory for each destination output port of the cell, and controls the cell readout circuit based on the address managed for each destination. and a buffer control circuit that reads the cells according to the speed of the output port and outputs the read cells in a predetermined order to the outgoing line that accommodates the output port specified by the header section. cell switching device.