JP2773757B2 - ATM cell multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchroous Transfer Mode) system for realizing a broadband ISDN, which multiplexes ATM cells.
The present invention relates to a TM cell multiplexing apparatus, and more particularly to an AT configured to use an ATM cell multiplexing apparatus for connection conversion in ATM cell units.
Regarding the M switch.

[0002]

2. Description of the Related Art Such an ATM cell multiplexing apparatus is described in, for example, Suzuki et al., "Method of Configuring Output Buffer ATM Switch", IEICE Technical Report SSE88-17.
2, pages 37 to 42 (hereinafter referred to as Reference 1).

[0003] Referring to FIG. 6, a conventional ATM cell multiplexer includes a rate V (for example, 622.times.) Representing a continuous ATM cell divided into valid cells and empty cells (invalid cells).
The first to N-th input lines 11-1 to 11-N to which the first to N-th (N is an integer of 2 or more) input signals having the input signal levels of 08 Mb / s) and the output line 120, respectively. Have.

The first to N-th S / P (serial / parallel) converters 12-1 to 12-N are connected to the first to N-th input lines 11 (subscripts are omitted), and Is converted into first to Nth parallel signals having, for example, 11.52 Mb / s, and the processing speed of the multiplexing unit 13 is reduced. The multiplexing unit 13 includes the first to Nth S / P conversion units 12
(Subscript omitted), and outputs a time-division multiplexed signal having the speed V × N and including the first to N-th multiplexed cells (multiplexed components). The first to N-th multiplexed cells are obtained from the first to N-th input signals, respectively. Assuming that N is 8, the speed V × N is 49
76.64 Mb / s.

[0005] FIFO using single port RAM
A (first-in first-out) memory 15 is connected to the multiplexing unit 13 via a time division bus 14 for the speed V × N. The control unit 16 controls the time-division bus 14 and the F
The first memory is connected to the IFO memory 15 as shown in FIG.
To N-th multiplexed cells are successively written to the FIFO memory 15 as cells written at a writing speed equal to the speed 2 × V × N, and one of the written cells is FIFO-written. The data is read out from the memory 15 as a read signal in the order of arrival according to a first-in first-out rule at a read speed equal to 2 × V × N.

In the example shown in FIG. 7, N is equal to eight.
That is, the number of input lines is eight. Single port RA
Since the write operation and the read operation cannot be performed simultaneously in the FIFO memory 15 using M, the write and read speeds are each twice the speed V × N, and the write and read operations are performed in a time-division manner. ing. The write timing appears eight times in the time of each one ATM cell of the input signal of the speed V. Assuming that the first to Nth input signals represent valid cells at a certain point in time, the FIFO memory 15
Can sequentially output the first to Nth (eighth) valid cells within the time of each one ATM cell of the input signal.
It is stored as the (eighth) written cell. The read timing appears once within the time of each one ATM cell of the input signal of the speed V. As a result, the first written cell is read from FIFO memory 15 as a first read cell according to a first-in first-out rule within the time of one ATM cell of each of the input signals. The second written cell is read from FIFO memory 15 as a second read cell within the time of each next ATM cell of the input signal. Similarly, the Nth (ie, eighth) written cell is read from FIFO memory 15 as an eighth read cell. The first to eighth read cells constitute the read signal.

In FIG. 6, a P / S (parallel / serial) conversion unit 17 includes a FIFO memory 15 and an output line 1.
20, converts the read signal into a time-division multiplexed output signal having a speed V, and outputs the converted signal to an output line 120.

As described above, the S / P converter 12 and the multiplexer 1
3, time division bus 14, FIFO memory 15, control unit 1
6 and the P / S converter 17 are connected to the first to Nth input lines 11 and the output line 120, and the first to Nth
To a time-division multiplexed output signal having a speed V, and serves as a processing unit for sending the time-division multiplexed output signal to the output line 120. In addition, the S / P conversion unit 12, the multiplexing unit 1
3, and the time division bus 14 functions as a time division multiplexing unit that time division multiplexes the first to Nth input signals and outputs a time division multiplexed signal having a speed V × N.

Next, the details of the ATM cell multiplexer shown in FIG. 6 will be described with reference to FIG. 1st to Nth input lines 1
1-1 to 11-N receive first to Nth input signals, each representing a continuous ATM cell. One of the ATM cells is shown in FIG. In FIG. 9A, the illustrated A
The TM cell has first to 54th bytes, each byte consisting of 8 bits (generally Q bits). The first byte has first to eighth bits. The second byte has ninth through sixteenth bits. The 54th byte has 425th through 432th bits.

In FIG. 8 and FIG. 9A, S / P converters 121-1 to 121-N are connected to first to N-th input lines 11-1 to 11-N, respectively, and input signals are sent to first to Nth input lines 11-1 to 11-N. The first to eighth (Q) th sliced cells are converted.
The first sliced cell has the first, ninth, ..., and 425th bits. The eighth sliced cell has eighth, sixteenth, ..., and 432th bits. Such a cell slice is described in the above-mentioned reference 1.

In FIG. 8, first to Qth (eighth) L
The SI chips # 1 to #Q (# 8) are connected to the S / P converter 121-
1 to 121-N. The first LSI chip # 1 receives the first sliced cell from the S / P converters 121-1 to 121-N, and the Qth (eighth) LSI chip #Q (# 8) receives the Qth ( Eighth) receive the sliced cell. First to Qth (eighth) LSI chips # 1 to #
Since Q (# 8) is similar in structure and operation to each other, here, only the first LSI chip # 1 will be described.

The first LSI chip # 1 has S / P converters 122-1 to 122-N connected to S / P converters 121-1 to 121-N, respectively. S / P converter 1
22-1 receives the first sliced cell from the S / P converter 121-1, and the S / P converter 122-N receives the first sliced cell from the S / P converter 121-N. . Each of the S / P converters 122-1 to 22-N has a first
Is converted into the parallel signal shown in FIG. 9B. S / P conversion section 121-1 and first LS
S / P converter 122-1 of I chip # 1 and remaining LSI
A similar S / P converter of the chip acts as the first S / P converter 12-1 in FIG. Similarly, S / P converter 1
21-N and S / P Converter 12 of First LSI Chip # 1
2-N and similar S / P converters of the remaining LSI chips
It functions as the N-th S / P converter 12-N in FIG.

In FIG. 8, a multiplexer 131 receives parallel signals from S / P converters 122-1 to 122-N, time-division multiplexes the parallel signals, and outputs a multiplexed signal. FIG.
As shown in (c), the multiplexed signal includes first to eighth signals.
First to eighth components # 1 to # 8 (#N) obtained respectively from the first sliced cells of the (Nth) input signal
have. Similarly, the similar multiplexing unit of the Q-th LSI chip #Q includes the first to eighth components obtained from the Q-th sliced cells of the first to eighth (N-th) input signals, respectively. A multiplex signal having # 1 to # 8 (#N) is output. The multiplexing unit 131 of the first LSI chip # 1 and a similar multiplexing unit of the remaining LSI chips function as the multiplexing unit 13 in FIG.

In FIG. 8, a FIFO memory 151 is connected to a multiplexing unit 131 via a time division bus 141. The time division bus 141 and the similar time division bus of the remaining LSI chips act as the time division bus 14 in FIG. Assuming that the first to N-th input signals represent valid cells at a certain point in time, the control unit 16 determines the first to eighth signals obtained from the first sliced cells as described with reference to FIG. (No. N)
Components # 1 to # 8 (#N) are continuously written to the FIFO memory 151, and the first component # 1 is written to the FIFO memory 151.
Read from Such a write and read operation for the first LSI chip # 1 is performed in synchronization with a write and read operation for the remaining LSI chips. First L
FIFO memory 151 of SI chip # 1 and remaining LSI
A similar FIFO memory in the chip acts as FIFO memory 15 in FIG.

P / S converter 1 of first LSI chip # 1
The P / S converter 71 and the P / S converter 172 of the remaining LSI chips function as the P / S converter 17 of FIG.

[0016]

As described above, in the ATM cell multiplexer shown in FIG. 6, the FIFO memory 15 is realized by using a single port RAM in an LSI chip. At this time, since the write operation and the read operation for the single port RAM cannot be performed at the same time, as described with reference to FIG.
A method is adopted in which the write operation and the read operation are performed in a time-division manner by setting N times twice. Therefore, when a high-speed and large-scale ATM cell multiplexing device is realized, there is a disadvantage that the access time to the FIFO memory 15 tends to be a bottleneck in realizing the device.

An object of the present invention is to provide an ATM switch suitable for realizing a high-speed and large-scale ATM switch capable of reducing the access speed (write and read speed) to a FIFO memory.
An object of the present invention is to provide a TM cell multiplexer.

[0018]

According to one aspect of the present invention, first to N-th (N is an integer greater than one) with a speed V representing consecutive ATM cells divided into valid cells and empty cells. First to Nth input lines to which the input signals are respectively supplied, at least one output line,
To the Nth input line and the at least one output line, processing the first to Nth input signals into a time division multiplexed output signal having the speed V, An ATM cell multiplexing device having processing means for sending to said at least one output line, said processing means comprising: one dummy input line supplied with a dummy input signal having said speed V, representing continuous empty cells; , Connected to the first to Nth input lines and the dummy input line, time-division multiplexing the first to Nth input signals and the dummy input signal, and having a speed V × (N + 1); And a time division multiplexed signal including first to Nth multiplexed cells and dummy multiplexed cells obtained from the first to Nth input signals and the dummy input signal, respectively. A time-division multiplexing means for outputting, a first-in first-out memory connected to the time-division multiplexing means, and the first to N-th multiplexing means connected to the time-division multiplexing means and the first-in first-out memory Writing the valid cells of the cells into the first-in first-out memory in the write period determined by the first to N-th multiplexed cells;
× (N + 1) continuously written as cells written at a write speed equal to (N + 1), and one of the written cells is read from the first-in first-out memory from the first-in first-out memory for a read period determined by the dummy multiplexed cell, V ×
At the read speed equal to (N + 1), the signals are read as read signals in the order of arrival in accordance with the first-in first-out rule.
Control means for controlling the read-out signal at a speed of V × (N + 1) and connected to the first-in-first-out memory and the at least one output line. , And a conversion unit for outputting the data to the at least one output line.

Further, according to another aspect of the present invention,
First to N-th (N is an integer of 2 or more) having a speed V, representing continuous ATM cells divided into valid cells and empty cells
1 to N-th input lines to which the input signals are respectively supplied, first to M-th (M is an integer of 2 or more) output lines having different output line numbers, and continuous empty cells. One dummy input line to which the dummy input signal having the speed V is supplied, the first to the Nth input lines and the dummy input line,
The first to Nth input signals and the dummy input signal are time-division multiplexed, have a speed V × (N + 1), and
Time-division multiplexing means for outputting a time-division multiplexed signal, including first to Nth multiplexed cells and dummy multiplexed cells obtained from the first to Nth input signals and the dummy input signal, respectively; An output line number of the corresponding output line is provided as a storage address, provided corresponding to the first to M-th output lines, and receives the time division multiplex signal and includes the output line number in the time division multiplex signal. Connected to the first to Mth cell passing means for passing the valid cell only when the output line address associated with the valid cell coincides with the storage address, and respectively connected to the first to Mth cell passing means. Connected to the first to Mth first-in first-out memories, the time-division multiplexing means, and the first to M-th first-in first-out memories. The effective cell which has passed through the cell passing means of the first to the second M, the corresponding first-in-first-out memory, the first to write period determined by the multiplexing cells of the first N, the velocity V × (N +
The cells are continuously written as cells written at a writing speed equal to 1), and one of the written cells is determined by the dummy multiplexed cell from the first to Mth first-in first-out memories. Control means for reading as a read signal in the order of arrival according to a first-in first-out rule at a read speed equal to the speed V × (N + 1) during the read period, and controlling a time ratio between the write period and the read period to N: 1; The first to Mth first-in first-out memories and the first
To the M-th output line,
Converting the read signal read from the first to Mth first-in first-out memories at the speed V × (N + 1) into a time-division multiplexed output signal at the speed V; 1st output to output line
To an M-th conversion means.

[0020]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, the ATM cell multiplexer according to the first embodiment of the present invention is the same as the ATM cell multiplexer of FIG. 6, except as described below. Real AT
The M-cell multiplexing device has a dummy input line 20 supplied with a dummy input signal having a speed V, which represents a continuous empty cell (invalid cell). In each of the empty cells, all bits are logic "0". The multiplexing unit 13 'is connected to the first to N-th S / P converters 12-1 to 12-N and the dummy input line 20, and multiplexes the first to N-th parallel signals and the dummy input signal. , A time-division multiplexed signal having a speed V × (N + 1) and including first to N-th multiplexed cells (multiplexed components) and dummy multiplexed cells. The first to Nth multiplexed cells and the dummy multiplexed cells are obtained from the first to Nth input signals and the dummy input signal, respectively. Assuming that N is 8, the speed V × (N + 1)
Is 5598.72 Mb / s.

The FIFO memory 15 has a speed V × (N +
It is connected to the multiplexing unit 13 'via a time division bus 14' for 1). The control unit 16 'is connected to the time division bus 14' and the FIFO memory 15, and as shown in FIG.
Effective cells of the first to N-th multiplexed cells are written into the FIFO memory 15 at a write period equal to the speed V × (N + 1) during a write period determined by the first to N-th multiplex cells. One of the written cells is sequentially read from the FIFO memory 15 in the order of arrival according to the first-in first-out rule at a read speed equal to the speed V × (N + 1) during a read period determined by the dummy multiplex cell. Reading is performed as a signal, and the time ratio between the writing period and the reading period is controlled to N: 1.

In the example shown in FIG. 2, N is equal to eight.
The write period is determined by the first to N-th multiplexed cells, as shown by the write timing in FIG. The read period is determined by the dummy multiplex cell as shown by the read timing in FIG. Write timing is
Each V input signal of rate V appears N (ie, 8) times in the time of one ATM cell. The read timing is the speed V
Appear once within the time of one ATM cell of each of the input signals. At this time, each of the write and read speeds is V ×
(N + 1). The FIFO memory 15 stores up to eight (N) valid cells continuously as written cells within the time of one ATM cell of each of the input signals, and stores one of the written cells. Are sent to the P / S converter 17 according to the first-in first-out rule.
In the present invention, the access speed (i.e., the write and read speed) is reduced from 2 * N * V (FIG. 6) to V * (N + 1), which is the conventional (N + 1) / (2 * N). it can.

In FIG. 1, a P / S converter 17 converts a read signal of speed V × (N + 1) into a time-division multiplexed output signal of speed V, and outputs it to an output line 120.

Next, the details of the ATM cell multiplexer shown in FIG. 1 will be described with reference to FIG. The ATM cell multiplexer of FIG. 3 is the same as the ATM cell multiplexer of FIG. 8 except as described below. Since the first to Qth (eighth) LSI chips # 1 to #Q (# 8) are similar in structure and operation to each other, only the first LSI chip # 1 will be described here. The first LSI chip # 1 has a multiplexing unit 131 'and a time division bus 141' instead of the multiplexing unit 131 and the time division bus 141 of FIG. Multiplexer 1
31 'receives parallel signals from the S / P converters 122-1 to 122-N, receives a dummy input signal from the dummy input line 20, time-division multiplexes the parallel signal and the dummy input signal, and outputs a multiplexed signal. . As shown in FIG. 9C, the multiplex signal has first to eighth components # 1 to # 1.
# 8 and a dummy component indicated by a virtual line. The dummy component is obtained from the dummy input signal and has 54 bits.

In FIG. 3, a multiplexing section 131 'of the first LSI chip # 1 and a similar multiplexing section of the remaining LSI chips function as the multiplexing section 13 of FIG. The FIFO memory 151 is connected to the multiplexing unit 131 via the time division bus 141 '. The time division bus 141 'and the same time division bus of the remaining LSI chips function as the time division bus 14' of FIG. Assuming that the first to N-th input signals represent a valid cell at a certain point in time, the control unit 16 ′ performs the first to eighth (N-th) components # 1 to # 8
(#N) is continuously written into the FIFO memory 151, and the first component # 1 is read from the FIFO memory 151. Such a write and read operation for the first LSI chip # 1 is performed in synchronization with a write and read operation for the remaining LSI chips. The P / S conversion section 171 of the first LSI chip # 1 has the same P / S
The S converter and the P / S converter 172 function as the P / S converter 17 in FIG.

Referring to FIG. 4, the ATM cell multiplexer according to the second embodiment of the present invention functions as an ATM switch for performing connection conversion on an ATM cell basis. This ATM cell multiplexer is the same as the ATM cell multiplexer of FIG. 1 except as described below.

The ATM cell multiplexer has first to M-th (M is an integer of 2 or more) output lines 120-1 to 120-M having different output line numbers. First to Mth address filters (cell passing means) 35-
1-35-M are the first through M-th output lines 120-1.
, And the output line number of the corresponding output line is stored as a storage address.
Upon receiving the time division multiplex signal from the time division bus 14 ', it passes the valid cell only when the output line address associated with the valid cell included in the time division multiplex signal matches the storage address. First to M-th FIFO memories 15-1 to 15-1
5-M is the first to Mth address filters 35-1 to 35-1.
35-M.

The control unit 16 "includes the time division bus 14 'and the first
To the M-th FIFO memories 15-1 to 15-M, and the first to M-th address filters 35-1 to 35-35.
-M successively write valid cells that have passed through the corresponding FIFO memory as cells written at a write speed equal to the speed V × (N + 1) for a write period determined by the first to N-th multiplexed cells. , First to M-th FIFOs
From the memories 15-1 to 15-M, one of the written cells is read at a speed V, which is determined by a dummy multiplex cell.
At the read speed equal to × (N + 1), the read signals are read in the order of arrival according to the first-in first-out rule, and the time ratio between the write period and the read period is controlled to N: 1.

First to Mth P / S converters 17-1 to 17-1
7-M are connected between the first to M-th FIFO memories and the first to M-th output lines 120-1 to 120-M, respectively.
× (N + 1) is converted into a time-division multiplexed output signal of the speed V, and the first to Mth output lines 12
0-1 to 120-M.

Referring to FIG. 5, a modification of the ATM cell multiplexer shown in FIG. 4 will be described. The ATM cell multiplexer of FIG.
The operation is substantially the same as that of the ATM cell multiplexer shown in FIG. 4, and differs from the ATM cell multiplexer shown in FIG. 3 in the following points. The present ATM cell multiplexer includes first to Mth
The first to M-th output lines 120-1 to 120-M having the output line addresses (output line numbers) and the first to N-th address signals having the speed V, which continuously represent the output line addresses. It has first to Nth address lines 31-1 to 31-N, respectively. On this occasion,
The first address signal is output line 120 to which successive ATM cells represented by the first input signal are to be sent.
The output line addresses (subscripts omitted) are continuously shown. Similarly, the Nth address signal continuously represents the output line address of output line 120 to which the consecutive ATM cells represented by the Nth input signal are to be sent.

First to Nth S / P converters 32-1 to 32-3
2-N is connected to the first to Nth address lines 31 (subscripts omitted), and converts the first to Nth address signals into first to Nth parallel address signals. Dummy address line 20 'receives a dummy address signal having speed V. The dummy address signal continuously indicates an address in which all bits are logic “0”. Multiplexing unit 33
Is connected to the first to N-th S / P converters 32 (subscripts omitted) and the dummy address line 20 ′, time-division multiplexes the first to N-th parallel address signals and the dummy address signal, and × (N + 1), and outputs a time division multiplexed signal including the first to Nth multiplexed addresses and the dummy multiplexed address. The first to N-th multiplexed addresses and the dummy multiplexed addresses are obtained from the first to N-th parallel address signals and the dummy address signals, respectively.

First to Mth address filters 35-1
To 35-M are connected to the multiplexing unit 33 via the time division bus 34 for the speed V × (N + 1). The first to M-th address filters 35-1 to 35 -M preliminarily set the first to N-th output line addresses of the first to M-th output lines 120-1 to 120 -M, respectively. N is stored as the stored address. In each of the first to Mth address filters 35 (subscripts omitted), each of the output line addresses represented by the first to Nth multiplexed addresses is stored in each of the first to Mth address filters 35. A match pulse is generated each time the address matches. First to M-th up / down counters 36-1 to 36-1
36-M are first to M-th address filters 35-1
To 35-M. Each of the first to M-th up / down counters 36 (subscripts omitted) counts up the initial count (equal to zero) to the increment count each time a coincidence pulse is received. When the increment count is 1 or more, each of the up / down counters 36 outputs a read timing signal, and counts down the increment count to the decrement count each time the read timing signal is output.

First to Qth (eighth) LSI chips # 1
Let's focus on #Q (# 8). The first to Qth (eighth) LSI chips # 1 to #Q (# 8) are similar in structure and operation to each other, so the first LSI chip # 1 will be mainly described. The first LSI chip # 1 is commonly connected to the time-division bus 141 ′, and the first to Mth
To M-th FIFO memories 151-1 to 15-15 respectively connected to the address filters 35-1 to 35-M
1-M. Each of the FIFO memories 151 (subscripts omitted) receives a match signal from the corresponding address filter 35,
When received as a write timing signal, the multiplexing unit 131 '
Is stored as a stored signal, and up /
Upon receiving the read timing signal from the down counter 36, the stored signal is output according to a first-in first-out rule.

If the first to Nth input signals are to be sent to the first output line 120-1, then
The first address filter 35-1 and the first up / down counter 36-1 function as the control unit 16 'in FIGS. 1 and 3.

The first to M-th P / S converters 171-1 to 171-1
171-M are first to M-th FIFO memories 151-1
To 151-M. 1st to Mth P
/ S converters 172-1 to 172-M are the first to M-th P
/ S converters 171-1 to 171-M, respectively. First to M-th output lines 120-1 to 120-M
Are the first to M-th P / S converters 172-1 to 172-M
Connected to each other. First P / S converter 171-1
And 172-1 are the P / S converters 171 and 172 in FIG.
And the M-th P / S conversion units 171-M and 17
2-M also functions as the P / S converters 171 and 172 in FIG.

In FIG. 5, the address filter 35-1
35-M may be connected to the time division bus 141 'instead of being connected to the time division bus 34. In this case, each of the input lines 11-1 to 11-N is connected to the output line 120.
An input signal is provided that includes a valid cell with a destination address indicating one of the -1 to 120-M line addresses.

[0038]

As described above, according to the present invention, when time-division multiplexing of signals of N input lines is performed, one dummy input line is added to N inputs, and the speed of the time-division multiplexed signal is increased. Is set to V × (N + 1), the access speed to the FIFO memory can be reduced to the conventional (N + 1) / 2N, and there is an effect that a higher-speed and large-scale ATM switch can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an ATM cell multiplexer according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the ATM cell multiplexer of FIG. 1;

FIG. 3 is a detailed block diagram of the ATM cell multiplexer of FIG. 1;

FIG. 4 is a block diagram of an ATM cell multiplexer according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a modification of the ATM cell multiplexer of FIG. 4;

FIG. 6 is a block diagram of a conventional ATM cell multiplexer.

FIG. 7 is a timing chart for explaining the operation of the ATM cell multiplexer of FIG. 6;

FIG. 8 is a detailed block diagram of the ATM cell multiplexer of FIG. 6;

FIG. 9 is a diagram for explaining the operation of the ATM cell multiplexer of FIG. 6 and the present invention.

[Explanation of symbols]

 11-1 to 11-N Input line 120, 120-1 to 120-M Output line 12-1 to 12-N S / P converter 13 'Multiplexer 14' Time division bus 15, 15-1 to 15-M FIFO memory 16 ', 16 "control unit 17, 17-1 to 17-M P / S conversion unit 20 dummy input line 35-1 to 35-M address filter

Claims (2)

(57) [Claims] 1. A first to N-th (N is an integer of 2 or more) input signals having a speed V, which represent continuous ATM cells divided into valid cells and empty cells, respectively. And the at least one output line, and the first through the Nth input lines and the at least one output line, the first through the Nth input signals having the speed V Processing means for processing the divided multiplexed output signal and sending said time multiplexed output signal to said at least one output line, said processing means comprising: One dummy input line supplied with a dummy input signal having the following, and the first to Nth input signals connected to the first to Nth input lines and the dummy input line. And the dummy input signal is time-division multiplexed, has a speed of V × (N + 1), and has first to N-th multiplexes obtained from the first to N-th input signals and the dummy input signal, respectively. A time-division multiplexing means for outputting a time-division multiplexed signal including cells and dummy multiplexed cells, a first-in first-out memory connected to the time-division multiplexing means, the time-division multiplexing means and the first-in first-out memory Connected to
The valid cells of the first to N-th multiplexed cells are stored in the first-in first-out memory in the first-in first-out memory.
A writing period determined by the N-th multiplexed cell,
Write continuously as cells written at a write speed equal to the speed V × (N + 1), and one of the written cells is removed from the first-in first-out memory
During a read period determined by the dummy multiplexed cells, read signals are read out in the order of arrival at a read speed equal to the speed V × (N + 1) according to a first-in first-out rule, and the time ratio between the write period and the read period is N: 1. Control means for controlling the time-division multiplexed output signal connected to the first-in first-out memory and the at least one output line and read at the speed V × (N + 1). Converting means for converting and outputting to the at least one output line. 2. The first to N-th input signals (N is an integer of 2 or more) having a speed V, which represent continuous ATM cells divided into valid cells and empty cells. And a first to M-th (M is an integer of 2 or more) output lines having different output line numbers, and a dummy input signal having the speed V, which represents a continuous empty cell. One dummy input line and the first through Nth input lines and the dummy input line, and time-division multiplexes the first through Nth input signals and the dummy input signal to obtain a speed V × ( N + 1)
And outputting a time division multiplexed signal including first to Nth multiplexed cells and dummy multiplexed cells obtained from the first to Nth input signals and the dummy input signal, respectively. Division multiplexing means;
The output line number of the corresponding output line is stored as a storage address.
First to Mth cell passing means for receiving the time-division multiplexed signal and passing the valid cell only when an output line address associated with the valid cell included in the time-division multiplexed signal matches the storage address. And first to Mth cells respectively connected to the first to Mth cell passing means.
A first-in first-out memory, the time-division multiplexing means, and the first to the M-th first-in first-out memory, which are connected to the effective cells passing through the first to the M-th cell passing means. In the corresponding first-in first-out memory, the write period is determined by the first to N-th multiplexed cells, and is continuously written as a cell written at a write speed equal to the speed V × (N + 1). A first-in first-out rule from one to the M-th first-in first-out memory at a read speed equal to the speed V × (N + 1) during a read period determined by the dummy multiplexed cell. As a read signal in the order of arrival, and the time ratio between the write period and the read period N: 1 control means, connected between the first to Mth first-in first-out memories and the first to Mth output lines, respectively, The first to the Mth output lines convert the read signal read from the first-in first-out memory at the speed V × (N + 1) into a time-division multiplexed output signal at the speed V and output the converted signal to the first to M-th output lines. An ATM cell multiplexer comprising M-th conversion means.