KR100211024B1 - Multiplexing apparatus in atm switch - Google Patents

Abstract

[TECHNICAL FIELD OF THE INVENTION]

Multiplexing device in an asynchronous transfer mode switch.

[Technical Problems to be Solved by the Invention]

We want to multiplex according to the number of stored cells and service priority.

[Summary of the Invention]

Receiving cells input from a plurality of input ports, storing received cells when bit addresses match, counting stored cells, outputting stored cells if the number of stored cells is controlled by external process control, A plurality of input cell processing means for outputting extracted service priority information if the number of stored cells is less than or equal to a threshold value and a priority sorting means for outputting an input port identifier according to stored cell number information or service priority information from the plurality of input cell processing means And means for reading and multiplexing the cells stored in the input cell processing means according to the priority order.

[Important Application of the Invention]

ATM terminals, and network terminators.

Description

Multiplexing device in an asynchronous transfer mode switch

The present invention relates to a multiplexing apparatus in an Asynchronous Transfer Mode (ATM) switch, and more particularly to a multiplexing apparatus in an asynchronous transfer mode (ATM) switch, in which the width of an internal bus is parallelized to increase a multiplexing speed in an ATM switch, To statistically multiplexing devices.

In recent years, with the development of communication technology, not only continuous service of characteristics such as voice service, but also high-speed data service such as file transmission, variable bit rate (VBR) Asynchronous transfer mode (ATM) broadband integrated information network (B-ISDN) has emerged to meet various traffic acceptance demands such as video service.

In the broadband integrated information communication network, the ATM multiplexing and demultiplexing processing means are essential components in the communication system. Such multiplexing and demultiplexing processing means require a fixed length cell multiplexing and demultiplexing method suitable for the ATM system.

1B is an IGT multiplexer; Fig. 1C is an 8: 1 multiplexer of an IDT company; Fig. 1D is an IGT multiplexer of an IDT; Fig. : 1 multiplexer, respectively.

IDT 77305 (4-port Port Multiplexer (MUX) FIFO (First In First Out) manufactured by Integrated Device Technology (IDT) of FIG. 1a receives inputs of 155 Mbps from four input ports and multiplexes them at 622 Mbps Which is a device. Each input buffer can store two cells of 64 bytes, and the cells stored in each input buffer are scheduled in a round-robin manner and multiplexed in order. This is basically different from the time division multiplexing (TDM) method, and it is difficult to perform the multiplexing function for various services required by the ATM method.

Also, as shown in FIG. 1B, the IGT WAC-185B of IGT (Integrated Telecommunication) also basically performs a 4: 1 multiplexing function. The IGT WAC-185B receives input from each input port in units of cells each having a fixed length of 53 bytes, After storing in a static random access memory (SRAM), cells are read according to their priority order and multiplexed into one cell flow.

To perform the 8: 1 multiplexing function using the IDT and IGT multiplexing chips as described above, it is necessary to implement as shown in FIGS. 1C and 1D, which is complicated.

That is, in order to have 8 physical input ports when implementing an 8: 1 multiplexing device using IDT's multiplexing chip, two chips are used as shown in FIG. 1c, and a 2: 1 multiplexing device .

When IGT's multiplexed chips are used, one chip can be used, but two input ports must be multiplexed using a 2: 1 multiplexer when inputting.

The general multiplexing function means that the transmission efficiency of the transmission link is increased by making a combined cell flow from a plurality of separated inputs. Unlike the conventional time division multiplexing (TDM) scheme in which a service connection allocated to a fixed time slot occupies a transmission channel irrespective of whether or not there is a service traffic, the ATM scheme generates a transmission opportunity according to the statistical frequency of the generated traffic And when there is no traffic, the transmission channel is not occupied, so that the transmission efficiency is maximized.

Therefore, in order to realize this, a multiplexing function of allocating more transmission opportunities to an input port having a high frequency of occurrence of aperiodic traffic received from a plurality of independent inputs is required.

In order to solve the above-described multiplexing function of the present invention, it is necessary to determine whether or not to store the received cell by receiving a cell generated from a plurality of independent inputs, In addition, in order to accommodate traffic with high burst characteristics in the ATM environment, an input buffer, an output buffer, and a reverse flow control signal are provided to prevent overflow of traffic, thereby reducing cell loss And a routing tag having a bit address for the connection is added to the cell to perform a selective cell reception function. Therefore, it is easy to implement a small-scale switch, as well as performs asynchronous input buffer and buffer control, It works regardless of the asynchronous method, and it can integrate by implementing the multiplexer type multiplexer. To provide a multiplexing device has its purpose.

Figs. 1a to 1d are diagrams showing a conventional multiplexing apparatus. Fig.

FIG. 2 is a block diagram of a multiplexing apparatus according to an embodiment of the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

10: Process connection section 11: Input control section

12: input buffer 13: buffer control section

14: Service priority ordering unit 15: Port selection unit

16: multiplexing control unit 17: multiplexing unit

18: Synchronous clock generator 19: Output controller

20: output buffer 21: delay unit

According to an aspect of the present invention, there is provided a method for receiving a cell input from a plurality of input ports, extracting a bit address and a service priority information added to a header of a cell, storing received cells when bit addresses match, If the number of stored cells is equal to or greater than a certain threshold value, the number of stored cells is output. If the number of stored cells is equal to or less than the threshold value, the extracted service priority information is outputted. If the buffer is full A plurality of input cell processing means for outputting a reverse flow control signal to an input port; Priority sorting means for receiving input of stored cell number information or service priority information from the plurality of input cell processing means, sorting input port identifiers according to priority, and selecting and outputting input port identifiers one by one according to a cell synchronous clock; Multiplexing means for receiving an input port identifier according to a priority order from the priority sorting means and reading and multiplexing the cells stored in the input cell processing means and outputting a control signal for storing multiplexed cells; And output means for storing cells multiplexed in accordance with a control signal transmitted from the multiplexing means, counting the number of stored cells, reading out cells stored by an external output control signal, and outputting the cells; Process connecting means for providing an address decoder, a status register, and control registers to provide a process interface function so as to be controllable by an external process; And a synchronous clock generating unit connected to an external process via a process connection bus and generating a cell synchronous clock for synchronizing with the cell synchronous clock in multiplexing according to the priority of the input cell.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIG.

FIG. 2 is a block diagram of a multiplexing apparatus according to the present invention. In FIG. 2, reference numeral 10 denotes a process connection unit, 11 denotes an input control unit, 12 denotes an input buffer, 13 denotes a buffer control unit, 14 denotes a service priority ordering unit, A multiplexing control unit 16, a multiplexing unit 17, a synchronous clock generating unit 18, an output control unit 19, an output buffer 20, and a delay unit 21, respectively.

A multiplexing apparatus according to an embodiment of the present invention includes a process connection unit 10 connected to a process, an input control unit 10 for receiving a fixed length cell from a plurality of input ports and outputting a control signal for storing a cell having a matching bit address, An input buffer 12 for temporarily storing received cell data under the control of the input control unit 11 and a control unit 11 for receiving a write signal and service priority information from the input control unit 11, And outputs one of the count value and the service priority information under the control of an external process. If the input buffer 12 is in the full state, A buffer control unit 13 for outputting a flow control signal to an input port and a buffer control unit 13 for inputting each input port identifier in priority order according to service priority information inputted from the buffer control unit 13. [ A port selection unit 15 for selecting one input port identifier input from the service priority ordering unit 14 and outputting the input port identifiers one at a time, Receives the input port identifier and outputs a read signal to the input buffer 12 and the buffer control unit 13 of the input port, and at the same time, outputs a write signal for storing the control signal for multiplexing and the multiplexed cell data A multiplexing unit 17 for multiplexing a plurality of cell data output from the input buffer 12 under the control of the multiplexing control unit 16 and a multiplexing unit 17 under the control of the multiplexing control unit 16 An output buffer 20 for temporarily storing the cell data output from the multiplexer 17, a number of cells stored in the output buffer 20 in response to a write signal from the multiplexing controller 16, An output control unit 19 for receiving a flow control signal from the control unit 19 and outputting a control signal for reading a cell stored in the output buffer 20 in synchronization with the cell synchronization clock, and a synchronous clock generation unit 18 for generating a cell synchronization clock Respectively.

Hereinafter, the operation of the present invention will be described.

In the present invention, for convenience of description, only an embodiment for multiplexing the eight input ports will be described.

The input control unit 11 receives the input synchronizing signal BCLK and the input data in 8-bit units synchronized with the byte synchronizing clock BCLK through the input bus, a cell enable signal (CEN) signal indicating the effective length of the cell, SOC), receives a fixed-length cell, extracts specified bit address information and service priority information from the header of the cell, filters only cells matching the bit address of the location designated by the external process, and outputs the filtered cell to the input buffer 12 And outputs the write signal and the service priority information extracted from the input cell to the buffer control unit 13. [

In addition, since the fixed length of the cell can be varied according to the value set in the external process, the interface is provided so that it can be used for various applications.

Since the number of external connection pins can be limited in order to integrate into one chip as a functional element, the data width is set to 8 bits. In order to increase the internal operation speed, the input control unit 11 sets the input data to 16 bits And stores it in the input buffer 12.

Since each input port is completely independent of each other, it can have different clock speeds and cell synchronization, and has an independent input control unit 11, an input buffer 12, and a buffer control unit 13 for each input port.

The input buffer 12 is basically synchronized with a first-in-first-out (FIFO). To this end, the input buffer 12 stores a dual port RAM (DPRAM) A counter to generate a write address, a logic to control the write, a counter to generate a read address to control the read, logic to control the read, and a pointer to these buffers according to the number of reads and writes. And a logic for generating various flag signals indicating a full state of an input signal.

For example, if you want to store eight 56-byte cells in the input buffer 12, you need to design a dual-port RAM of 224 words x 17 bits. In this case, 1 bit is larger than 16 bits because cell synchronization is lost if there is garbage in the FIFO, so cell start information is stored at the time of storing to find cell synchronization.

The buffer control unit 13 includes an up-down counter and receives a write signal of the input buffer from the input control unit 11 and increases the number by 1 when a fixed length of bytes corresponding to the cell length is stored in the input buffer 12, When the input buffer reading signal is received from the input buffer 16 and the number of bytes corresponding to the cell length is read from the input buffer 12, that is, when one cell is read, the number of cells stored in the input buffer 12 is It is always maintained to monitor the storage level of the input buffer.

At this time, the write signal is completely asynchronous to the system, and the read signal is synchronized with the system, so that the synchronization is made between them.

Since the cell length can be specified by the process at the initial operation of the system, the counters corresponding to various cell lengths must be variable according to the value specified from the process.

In addition, it receives the cell data and the buffer write control signal, which are converted into 16 bits, from the input control unit 1 to maintain the service priority information, maintains the number of cells stored in the input buffer 12, 12 is less than or equal to a specified value, the service priority order information of the cell is output to the service priority ordering unit 14. [

When the buffer is full, the buffer control unit 13 outputs the reverse flow control signal HALT to the corresponding external input port under the control of the external process, thereby stopping the cell transmission and preventing instant buffer overflow.

The service priority ordering unit 14 classifies the service priority order according to priority information inputted from the buffer control unit 13 of each input port and selects an input buffer 12 from which a transmission opportunity can be obtained. The service priority ordering unit 14 selects at least two input buffers and outputs them to the port selecting unit 15 because the operating speed of the present invention is twice as fast as the operating speed of the input cell.

The buffer controller 13 synchronizes the priority information with the system clock and outputs the same to the service priority ordering unit 14. The service priority ordering unit 14 does not always receive the priority information, Only when there is a cell synchronous clock from the clock generator 18, the service priority ordering unit 14 is not operated at all times, thereby reducing instantaneous operation power consumption.

The port selector 15 receives the port identifier from the service priority ordering unit 14 and selects input port identifiers one by one so that the cell data stored in the selected input buffer 12 can be multiplexed and output to the multiplexing controller 16 do.

The multiplexing control unit 16 receives one port identifier from the port selection unit 15 and outputs a read signal to the input buffer 12 and the buffer control unit 13 of the input port to output the cell stored in the input buffer 12 And outputs multiplexing control signals to the multiplexing unit 17 so that the cells output from the input buffer 12 can be multiplexed by the multiplexing unit 17. The output buffer 20 and the output control unit 19 to store the multiplexed cells output from the multiplexing unit 17 in the output buffer 20 and inform the output control unit 19 of the number of cells stored in the output buffer 20.

The synchronous clock generating unit 18 is connected to an external process via a process connection bus, and generates a cell synchronous clock to synchronize a functional unit for multiplexing input cells with a cell synchronous clock, and outputs the generated cell synchronous clock to each functional unit.

The output control unit 19 receives the write signal from the multiplexing control unit 16 and counts the number of cells stored in the output buffer 20 and receives the output control signal from the outside to receive the cell synchronous clock And outputs the read signal to the output buffer 20 in order to read the cell stored in the output buffer 20. [ At this time, the output control unit 19 reads and outputs the cell data stored in units of 16 bits in units of 8 bits.

The delay unit 21 temporarily delays the data output from the multiplexer 17 and outputs the delayed data to the output buffer 20. The output buffer 20 is controlled by the multiplexing control unit 16, The input multiplexed cells are temporarily stored until output, and are output under the control of the output control unit 19.

The process connection unit 10 includes an address decoder, a status register, and control registers, and provides a process interface function so that the entire circuit unit can be controlled by an external process.

The present invention is configured so that the internal processing cell structure can be commonly used by attaching additional bytes for internal processing from the basic 53 bytes in order to enable not only the function of multiplexing traffic but also the use in all places for the centralization such as exchanger and terminal And a cell filtering function is added so that it can be used as a small scale switch for a local area network (LAN).

In addition, the present invention can be easily implemented as one general-purpose device only if it is implemented as one custom semiconductor, and it is easy to use in any system requiring an asynchronous transfer mode (ATM) multiplexing function. Therefore, A dual port RAM is fabricated using an Embedded Gate Array or a standard cell technology and a gate array is formed in the remaining area, and then the above-mentioned control logic is disposed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. It is not.

The present invention as described above has the following specific effects.

First, it is possible to use a plurality of ATM applications because it can receive a cell generated from a plurality of independent inputs, judge whether or not the received cell is stored, and multiplex it according to the number of stored cells and service priority.

Second, the size of the input buffer is required to accommodate bursts of traffic in the ATM environment, and the internal operation speed must be increased. At the same time, The present invention can provide the size and structure of the input buffer and the output buffer in consideration of the structure of the buffering, By adding a control structure, the cell loss can be prevented and the performance can be improved even in a momentary overload state.

Third, since a writing tag having a bit address for a corresponding connection is placed in front of an input cell, a selective cell reception function for confirming whether or not to receive the multiplexed signal can be applied to the implementation of a small-scale switch.

Fourth, an asynchronous input buffer and a buffer control unit may be provided to have input / output ports that operate independently of the synchronous / asynchronous states of the input cells from the input ports and have different transmission rates.

Fifth, the present invention can be applied to the implementation of the concentrator necessary for implementing the switching center, and can be used in a main system installed in a high-speed information communication network such as an ATM terminal and a network terminating apparatus.

Claims (11)

When receiving a cell input from a plurality of input ports and extracting a bit address and service priority information added to a header of a cell, if the bit addresses match, the received cell is stored, and the number of stored cells is counted, And outputs the extracted service priority information if the number of stored cells is less than or equal to the threshold value and outputs the extracted service priority information if the number of stored cells is equal to or less than the threshold value and outputs the reverse flow control signal to the input port when the buffer is full A plurality of input cell processing means; Priority sorting means for receiving input of stored cell number information or service priority information from the plurality of input cell processing means, sorting input port identifiers according to priority, and selecting and outputting input port identifiers one by one according to a cell synchronous clock; Multiplexing means for receiving an input port identifier according to a priority order from the priority sorting means and reading and multiplexing the cells stored in the input cell processing means and outputting a control signal for storing multiplexed cells; Output means for storing cells multiplexed in accordance with a control signal transmitted from the multiplexing means, counting the number of stored cells, reading out cells stored by an external output control signal, and outputting the cells; Process connecting means for providing an address decoder, a status register, and control registers to provide a process interface function so as to be controllable by an external process; And a synchronous clock generating means connected to an external process via a process connection bus and generating a cell synchronous clock for synchronizing with a cell synchronous clock in a multiplexing operation at a priority level of an input cell, Device. 2. The apparatus of claim 1, wherein the input cell processing means receives a fixed length cell from a plurality of input ports, extracts a bit address and service priority information added to a header of the cell, Input control means for outputting a control signal for storing only cells whose bit addresses match; Input buffering means for temporarily storing received cell data under the control of said input control means and outputting a cell stored by the read signal of said multiplexing means; And a control unit for receiving the write signal from the input control unit and the service priority information extracted from the header of the cell, receiving the read signal from the multiplexing unit, counting the cell data stored in the input buffering unit, And outputting the extracted service priority information to the priority sorting unit when the number of stored cells is equal to or less than a threshold value, And outputs a reverse flow control signal to the input port when the control signal is in the ON state. 3. The asynchronous transfer mode switch according to claim 2, wherein the input control means is configured to receive data in units of 8 bits from an input port and to store the data in the input buffering means in units of 16 bits when one cell is received. . 4. The dual-port RAM according to claim 3, wherein the input buffering means comprises: a dual port random access memory (DPRAM) for storing input cells constituted by a number corresponding to the number of cells to be stored; A first counter for generating a write address for control; A first controller for controlling writing of the dual port RAM; A second counter for generating a read address to control reading of the dual port RAM; A second controller for controlling reading of the dual port RAM; And a logic unit for generating various flag signals indicating an empty state and a full state of the buffer using the pointers of these counters in accordance with the number of read and write operations. Multiplexer in a switch. 5. The dual port RAM according to claim 4, wherein the dual port RAM loses cell synchronization if there is garbage in the memory area, so that data storage unit bits (16 bits ) By one bit larger than that of the non-synchronous transfer mode switch. 3. The apparatus of claim 2, wherein the priority sorting means receives the cell number information or the service priority information stored in the input buffering means in synchronism with the cell synchronization clock from the buffer control means (13) Service priority sorting means for sorting and outputting port identifiers; And port selecting means for selecting one input port identifier input from the service priority sorting means and outputting the selected input port identifier to the multiplexing processing means. 7. The multiplexing apparatus as claimed in claim 6, wherein the service priority sorting means simultaneously outputs at least two input port identifiers. 7. The apparatus of claim 6, wherein the multiplexing processing means receives the input port identifier selected from the port selection means and outputs a read signal to the input buffering means and the buffer control means to output the stored data, A multiplexing control means for outputting a control signal for multiplexing the multiplexed cell data and a write signal for storing the multiplexed cell data; And multiplexing means for multiplexing the data output from the input buffering means under the control of the multiplexing control means. The multiplexing apparatus as claimed in claim 8, further comprising delay means for temporarily delaying and outputting the multiplexed data output from the multiplexing means. 10. The apparatus of claim 9, wherein the output means comprises: output buffering means for temporarily storing data output from the delay means under the control of the multiplexing control means; And a control signal generation unit for receiving a write signal from the multiplexing control unit and counting the number of cells stored in the output buffering unit, receiving a control signal from the outside, synchronizing the cell synchronization clock with a control signal for reading data stored in the output buffering unit And outputting control means for outputting the output of the multiplexing means. 11. The multiplexing apparatus as claimed in claim 10, wherein the output control means reads the data stored in units of 16 bits in units of 8 bits to the output buffering means and outputs the read data.